Concurrent, OA-based Mixed-signal Implementation

Similar documents
Virtuoso Layout Suite XL

DATASHEET VIRTUOSO LAYOUT SUITE FAMILY

AMS DESIGN METHODOLOGY

Will Silicon Proof Stay the Only Way to Verify Analog Circuits?

Cadence Rapid Adoption Kits

Comprehensive Place-and-Route Platform Olympus-SoC

DATASHEET VIRTUOSO LAYOUT SUITE GXL

Best Practices for Implementing ARM Cortex -A12 Processor and Mali TM -T6XX GPUs for Mid-Range Mobile SoCs.

Virtuoso Custom Design Platform GXL. Open Database. PDKs. Constraint Management. Customer IP

Mixed-Signal Design Trends and Challenges

Allegro Design Authoring

Laker 3 Custom Design Tools

Silicon Virtual Prototyping: The New Cockpit for Nanometer Chip Design

Europractice Cadence release. IC Package ASSURA 4.1 ASSURA 4.1 ASSURA 4.1

Synopsys Design Platform

An Incremental Technology Database Structure for Analog/Mixed-Signal Methodologies

Virtuoso - Enabled EPDA framework AIM SUNY Process

ASIC world. Start Specification Design Verification Layout Validation Finish

ASIC Physical Design Top-Level Chip Layout

101-1 Under-Graduate Project Digital IC Design Flow

RTL Coding General Concepts

Beyond Soft IP Quality to Predictable Soft IP Reuse TSMC 2013 Open Innovation Platform Presented at Ecosystem Forum, 2013

IOT is IOMSLPT for Verification Engineers

Digital System Design Lecture 2: Design. Amir Masoud Gharehbaghi

OpenAccess based architecture for Neolinear s Rapid Analog Design Flow

Eliminating Routing Congestion Issues with Logic Synthesis

Expert Layout Editor. Technical Description

Taming the Challenges of 20nm Custom/Analog Design

Laker and Calibre RealTime, an OA Integration Success Story

DFT-3D: What it means to Design For 3DIC Test? Sanjiv Taneja Vice President, R&D Silicon Realization Group

Baseband IC Design Kits for Rapid System Realization

Galaxy Custom Designer LE Custom Layout Editing

High Quality, Low Cost Test

Design Solutions in Foundry Environment. by Michael Rubin Agilent Technologies

Cadence Design Systems

Enabling An Interconnected Digital World Cadence EDA and IP Update. Jonathan Smith Director, Strategic Alliances June 1, 2017

Cadence FPGA System Planner technologies are available in the following product offerings: Allegro FPGA System Planner L, XL, and GXL

Analog, Mixed-Signal, and Advanced-Node Custom Design Scalability, Convergence and Throughput

Physical Placement with Cadence SoCEncounter 7.1

Clockless IC Design using Handshake Technology. Ad Peeters

Agenda. Presentation Team: Agenda: Pascal Bolzhauser, Key Developer, Lothar Linhard, VP Engineering,

Chapter 5: ASICs Vs. PLDs

EE 330 Laboratory Experiment Number 11

Laboratory 6. - Using Encounter for Automatic Place and Route. By Mulong Li, 2013

Hardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University

Case study of Mixed Signal Design Flow

Testable SOC Design. Sungho Kang

Tutorial for Cadence SOC Encounter Place & Route

PDK-Based Analog/Mixed-Signal/RF Design Flow 11/17/05

AMIS CDNLive Paper: A DFII Based Place and Route Interface

OpenPDK Production Value and Benchmark Results

The IIT standard cell library Version 2.1

FishTail: The Formal Generation, Verification and Management of Golden Timing Constraints

EEL 5722C Field-Programmable Gate Array Design

Mentor Graphics Solutions Enable Fast, Efficient Designs for Altera s FPGAs. Fall 2004

Physical Design Implementation for 3D IC Methodology and Tools. Dave Noice Vassilios Gerousis

Laker Custom Layout Automation System

ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS)

Contents 1 Introduction 2 Functional Verification: Challenges and Solutions 3 SystemVerilog Paradigm 4 UVM (Universal Verification Methodology)

Evolution of CAD Tools & Verilog HDL Definition

PrimeTime: Introduction to Static Timing Analysis Workshop

Harmony-AMS Analog/Mixed-Signal Simulator

VCS AMS. Mixed-Signal Verification Solution. Overview. testing with transistor-level accuracy. Introduction. Performance. Multicore Technology

Tutorial 2 Automatic Placement & Routing

Advance Manual ECO by Gates On the Fly

Cadence On-Line Document

Design Compiler Graphical Create a Better Starting Point for Faster Physical Implementation

Virtuoso System Design Platform Unified system-aware platform for IC and package design

PVS Interactive Short Locator: Establishing Efficiency and Predictability in the LVS Short Debug Process for Advanced SoC Design

EECS 627, Lab Assignment 3

Graphics: Alexandra Nolte, Gesine Marwedel, Universität Dortmund. RTL Synthesis

More Course Information

Silicon Photonics Scalable Design Framework:

Electrical optimization and simulation of your PCB design

Cadence/EURORPACTICE 2011/2012 Release. IC Package. Cadence Advanced Encryption Standard-64bit

Overview of Digital Design with Verilog HDL 1

ECE260B CSE241A Winter Tapeout. Website:

Creating Verilog Tutorial Netlist Release Date: 01/13/2005(Version 2)

ALLEGRO DESIGN ENTRY HDL 610

Part B. Dengxue Yan Washington University in St. Louis

Digital VLSI Design with Verilog

Mixed Signal Verification Transistor to SoC

Prepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia Institute of Technology

Model Connection Protocol extensions for Mixed Signal SiP

OpenAccess PCells Ed Petrus VP Engineering V2

Quality Assured SoC Design Using Crossfire. A Fractal whitepaper

Parag Choudhary Engineering Architect

Detailed Presentation

Synthesizable FPGA Fabrics Targetable by the VTR CAD Tool

Evolution of UPF: Getting Better All the Time

Synthesis and APR Tools Tutorial

EEM870 Embedded System and Experiment Lecture 4: SoC Design Flow and Tools

MOSAID Semiconductor

DIGITAL DESIGN TECHNOLOGY & TECHNIQUES

TUTORIAL II ECE 555 / 755 Updated on September 11 th 2006 CADENCE LAYOUT AND PARASITIC EXTRACTION

EE595. Part VIII Overall Concept on VHDL. EE 595 EDA / ASIC Design Lab

ALLEGRO DESIGN ENTRY HDL 610

Fujitsu SOC Fujitsu Microelectronics America, Inc.

DESIGN STRATEGIES & TOOLS UTILIZED

Physical Verification Challenges and Solution for 45nm and Beyond. Haifang Liao Celesda Design Solutions, Inc.

Transcription:

Concurrent, OA-based Mixed-signal Implementation Mladen Nizic Eng. Director, Mixed-signal Solution 2011, Cadence Design Systems, Inc. All rights reserved worldwide.

Mixed-Signal Design Challenges Traditional model Over the Wall Collaborative model Floorplan Architect Results of World-wide MS ToT survey of 561 attendees; Q1-2011 Abstract Floorplan Concurrent block design Analog/Custom group group Integration, ECO, Signoff Integration lead Data translation Setup & maintenance for multiple tools Informal communication of design intent Black-box : no visibility in each other domain Sequential design tasks Increased iterations Prolong TAT Costly ECO Sub-optimal design Increased risk of silicon re-spin Common DataBase for analog and digital Unified technology setup Constraints drive design Full transparency of each domain Concurrent design Relative importance Fewer iterations Shorten TAT Effective ECO Quality design Reduced risk of silicon re-spin 2 2012 Cadence Design Systems, Inc. All rights reserved.

Weighted Importance Biggest Challenges in MS Implementation World-wide survey of 561 MS ToT attendees, Q1-2011 3 2012 Cadence Design Systems, Inc. All rights reserved.

Schematic-driven Mixed-signal Flow Evolution Traditional Separate analog and digital environments Black-box/Abstract/GDS level exchange Data translation OA-integrated Analog-centric Unified database no data translation Full visibility into analog and digital, in separate hierarchy Concurrent Highest level of mixed-signal integration instantiated in layout module hierarchy and bind to schematic at the top level Virtuoso 3 rd Party P&R tool Virtuoso EDI Virtuoso EDI OA Proprietary DB OA OA MS architecture and integration 1 st generation 2 nd generation 30% Gain 30% Gain

Unified Environment for MS Design Area Better floorplanning No Data translation Virtuoso EDI TAT Effective ECO at any design stage No Data translation Quality of Silicon Avoid re-spins by better timing signoff No Data translation Design constraints passing No Data translation OpenAccess Unified Design DataBase No Data translation Efficiency Maintain one instead of two technology setups Unified Library and Technology setup 5 2012 Cadence Design Systems, Inc. All rights reserved.

Mixed-Signal PDK Virtuoso EDI Optional for digital users techlef OA techfile One time consolidation One time effort on consolidating technology information for OA interoperable MS Implementation flows Taking advantage of Incremental Technology Data Base (ITDB) Single, consolidate OA techfile for both Virtuoso and EDI 6 2012 Cadence Design Systems, Inc. All rights reserved.

Mixed-signal Implementation Flows A A/d A/D D/A D/a D Methodology Analog-centric Concurrent -centric Design Top level is analog; standard cell contained in block Analog and standard cell digital mixed at same level. Predominantly digital design with analog integrated as macros Top level connectivity Schematic Schematic and Netlist Netlist Verification SPICE; Mixed-signal simulation, analog behavioral models Mixed-signal simulation; behavioral models; Assertions and MDV simulation with RNM; MDV Floor-planning Controlled, constraint driven Control and automation Highly automated, timing, congestion, power driven Analog content Main/Top Co-designed Separate partition content in separate partition Co-designed Main/Top Routing Custom for top and analog.; timingdriven on-grid for digital Combination of custom of-grid and digital on-grid Top level analog by VSR; all other routing by NR. Chip Integration Custom Environment Custom or environment Full-chip Signoff Mixed-signal parasitic simulation STA and/or Mixed-signal parasitic simulation STA 7 2012 Cadence Design Systems, Inc. All rights reserved.

OpenAccess DFM AMS IP Implementation Flow Top Level Floorplan RTL netlist Library Constraints Analog/Custom Blocks Top Level Synthesis DFT Test Insertion Floor planning Power Planning Placement Low Power Optimization Chip Integration & Signoff Clock Tree Synthesis Timing optimization Routing Physical Verification 8 2012 Cadence Design Systems, Inc. All rights reserved.

Mixed-signal Floorplanning Top Level Floorplan in Virtuoso Encounter and Virtuoso interoperate on refining floorplan using constraints: Pin fixed or locked Halo Density screen Group and region Placement status of an instance Timing driven Placement and pin Optimization Block floorplan in Encounter 9 2012 Cadence Design Systems, Inc. All rights reserved.

Mixed-Signal Constraint Interoperability Specification and capture of MS design integration intent Hierarchical manipulation of integration constraints Storage and delivery through OA db Implementation support within both EDI System and Virtuoso Signoff validation using PVS Phase 1 support for MS routing constraints 10 2012 Cadence Design Systems, Inc. All rights reserved.

Timing & SI Signoff Analysis for Mixed-Signal Challenge: Full chip STA signoff should cover paths through digital embedded in AMS blocks No visibility into AMS black-box during integration Timing model for AMS blocks are inaccurate, do not account for SI and hard to generate Solution: Bring AMS blocks to EDI system via OA Expose its digital content (instances, layout routing) and stitch it to top level Extract and time full chip design including digital from AMS blocks Perform SI analysis No need for timing (.lib) models for AMS blocks (besides std. cells) 11 2012 Cadence Design Systems, Inc. All rights reserved.

ECO steps ECO for Mixed-Signal SoC Design Pre-Mask ECO Flow Analog PCell Stdceell OA Libraries Pre and post mask ECO functionality available in EDI Post-mask use spare cells, and limits eco routing to only specific layers Performed on design s unified OA database Save time by avoiding block level changes and repeating integration Highly automated No manual work EDI does re-mapping Full OA DB Connects the global net Connections for new instances If new Tie Hi/Tie Lo Connections are required Load (OA) design (restoreoadesign) Output and edit Verilog netlist Set OA update mode setoaxmode -UpdateMode true ecooadesign applyglobalnets addtiehilo ecoplace addfiller ecoroute Save design (saveoadesign) 12 2012 Cadence Design Systems, Inc. All rights reserved.

Benefits of Cadence MS Implementation Solution Predictability TAT TAT TAT Predictability Predictability Mature, Proven Analog and design platforms Common OA Database and unified technology setup Constraint driven methodology Easy to adopt and use Powerful Floorplanning/Pin-optimization Integrated analysis/signoff Automated ECO flow Strong Ecosystem Ability to serve entire scope (A<>A/d<>A/D<>D/a<>D) Support and Services Modern Mixed-signal design raises new challenges, Cadence is your best partner in addressing them. 13 2012 Cadence Design Systems, Inc. All rights reserved.

14 2012 Cadence Design Systems, Inc. All rights reserved.

15 2012 Cadence Design Systems, Inc. All rights reserved.