INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)

INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECNOLOGY (IJECET) International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 976 6464(Print), ISSN 976 6472(Online) Volume 3, Issue 1, January- June (212), IAEME ISSN 976 6464(Print) ISSN 976 6472(Online) Volume 3, Issue 1, January- June (212), pp. 3-31 IAEME: www.iaeme.com/ijecet.html Journal Impact Factor (211):.85 (Calculated by GISI) www.jifactor.com IJECET I A E M E NAND-NOR TYPE 4T LOADLESS SRAM BASED AREA AND POWER EFFICIENT YBRID Kuludip Kumar Gupta 1, Er.Nitin Kr.Tiwari 2, Dr. R.K Sarin 3 Department of Electronics & Communication 1,2,3 Dr. B. R. Ambedkar National Institute of Technology Jalandhar guptakuld@gmail.com 1, nitin.vd25@gmail.com 2, sarinrk@nitj.ac.in 3 ABSTRACT Content Addressable Memory is used in hardware look up table for data matching for its corresponding match location. ybrid type is combination of NAND and NOR type with control circuit. In this paper we proposed and implement four transistor store unit SRAM based. The proposed 1 32 bit array contains control circuit in between NAND type and NOR type. The results of the hybrid design are compared with conventional hybrid in CMOS.18um technology. It is found that the proposed design is having less area, power and energy as compared to the conventional. Keywords- Four transistor loadless SRAM based,or and NOR. I INTRODUCTION Content-Addressable Memory () is used to compare the search data with the stored data in parallel. Due to its fastest parallel search operation it is used in router.other applications of are parametic curve extraction, hough transformation, uffman coding/decoding and image coding. Fig 1 is simplified block diagram of [1] array which consist of 4 words and 4 bits. The match line of every in a word is shorted to matchline sense amplifier. The matchline is precharge to high before the data is put on search drivers as in Fig.1.If the search data matches with all bits in a word then the matchline will remain high otherwise it discharges to ground. The sense amplifier detects the matchline results and generate the corresponding Addresses for high value of matchline.the design are divided in two types NOR-type and NAND-type s. The NOR-type has best search performance at the cost of high power. 3

1 1 1 1 SA 1 1 SA 1 1 1 1 1 Search Data registers /drivers SA 1 Fig 1 array While the NAND-type has low power consumpution but has large delay. In this paper we implemented hybrid type in CMOS.18um technology which is combination of the NOR and NAND type with control circuit between them. The design is of 1 32 I.e 1 words with 32 bit. In this paper we vary the length of SEG_1 i.e NAND-type block to 1 bit and SEG_2 i.e NOR-type block to 31 bit.similiarly SEG_1 to 2 bit and SEG_2 to 3 bit and comparison has occur for various hybrid type. The rest of this paper is organized as follows Section II reviews brief discription of the OR NOR.In this we proposed four transistor SRAM store unit based of OR and NOR type.in Section III, we briefly describe the working of hybrid type [4].Next the experimental results are given in section V and Section IV gives some brief conclusions. II DESIGN CONCEPT OF Content Addressable Memory[2] consists of store unit,compare unit and match unit. The store unit stores the data,compare unit compares the search data with that of stored data and arrange in such a way that can be either OR or NOR type.match unit decides whether the stored data and search data is matched or not.the input of the is Search_Data(), Stored Data and Output is as shown in Fig.1 Search_Data() Stored SEARC STORE DATA() DATA 1 1 1 1 1 1 Fig.1(a) OR TYPE 31

Search_Data() Stored SEARC STORE DATA() DATA 1 1 1 1 1 1 Fig.1(b) NOR TYPE A. Traditional Nine Transistor The store unit of traditional in Fig. 2 consist of six transistor SRAM. The two transistor M1 and M2 are used as pass transistor which compares the stored data with the search data and the result is fed into gate of match unit transistor M3 which makes it on or off. If stored and search data matches,then = in OR shown in Fig 2(a).So there is no path for matchline() to discharge else is shorted to ground i.e =1. STORE WL M1 M2 M3 Fig.2(a) OR (6 T SRAM) owever in NOR in Fig.2(b) there will be a path for a matchline() to discharge if stored data and search data () matches to i.e =1. For mismatch there is no path for matchline to get discharged as =. 32

STORE a. NOR (6 T SRAM) B. PROPOSED Seven Transistor The proposed consists of loadless 4T SRAM[3] store unit. The difference in 4T SRAM with that of 6T SRAM is, The bit lines are charged to ground instead of Vdd in read mode.with the help of this 4T SRAM we implement OR and NOR type shown in Fig.4 WL STORE Vdd Fig.4(a) OR type (4 T SRAM) WL STORE Vdd Fig.4(b) NOR type (4 T SRAM) 33

C. NOR-Type The can be arranged in two ways either NOR type or NAND type. In NOR type Fig.6 the pull down NMOS transistor use for matching, is arranged in NOR fashion.the used is OR type. It provides best search performance as matchline discharges to ground when mismatch i.e = 1. So NOR type can be used for best search performance. D.NAND type The matchline are highly capactive in NOR-Type due to its parallel nature and hence OR OR.... OR OR PRE.... Fig. 6(a) NOR type NOR NOR NOR NOR........ Fig. 6(b) NAND type PRE results in more power dissipation. So to reduce the power we use NAND type in which the pull down NMOS transistor are arranged in NAND fashion as shown in fig.6(b). The is NOR type. The matchline capacitance is small so power consumption is very less during match condition i.e =1.owever The pull down path is too long to increase the discharging delay in match case. III YBRID-TYPE DESIGN A. Overview NOR-type has best search performance and NAND-type has less power dissipation. In hybrid type [4] we combine these two types with an additional control circuit.i.e SEG_1,control circuit,seg_2 as shown in Fig.7.In SEG_1 the used is NOR type, the pull down transistors are arranged in NAND fashion denoted as NAND TYPE BLOCK. In SEG_2 the used is OR type and the pull down transistor are arranged in NOR fashion denoted as NOR 34

NOR... NOR NAND-TYPE BLOCK P4 OR... OR PRE P3 T1 PRE N1 P1 M1 N4 NOR-TYPE BLOCK M2 P2 T3 PRE T2 N2 N3 SEG_1 CONTROL SEG_2 Fig.7 Word structure of 32 bit of hyrbrid design (ref [4]) NOR TYPE BLOCK. The NAND type block is matched only when it is connected to the ground i.e when all NOR cam output are 1. The NOR-type block is in matched state when all matchline is disconnected from the ground i.e =.. B Search Operation ybrid has two phases precharge phase and match evaluation phase irrespective to conventional that works in three phases. 1 Precharge phase. In this phase PRE signal is asserted low which makes M1,M2 and Matchline () charged to high. NMOS N2,N1,N3 are off so there is no path for T1,T2,T3 to discharge is mismatched. Therefore if one of OR is mismatched in NOR type block there will be no path for M2 to discharge through T3. Same for NAND type block, i.e. if =1 for all,there will no path for M1 to discharge. Because of this there is no searchline precharge phase in which bitlines are discharged to ground to prevent unexpected results. 2. Match Evaluation Phase Case I-In this case one of the NOR of NAND type of SEG_1 is mismatched and all or one of OR of NOR type of SEG_2 is either matched or mismatched.so M1 retains high which makes N2 and N3 transistor off which disconnect the pull down path T2 and T3. So whether NOR type is matched or mismatched still remains high due to no pull down path to discharge Case 1 Case 2 Case 3 Match Match Table -1 SEG_1 SEG_2 Match T1 PAT T2 T3 Each Node Voltages of ybrid KEY M1 L L L NODE M2 L RESULT Match 35

CASE I: SEG_1 is mismatched SEG_2 is mismatched CASE II: SEG_1 is matched SEG_2 is mismatched 36

CASE I: SEG_1 is mismatched SEG_2 is matched Case III: SEG_1 is matched SEG_2 is matched (Fig.8 Simulated waveform for Seven Transistor (The waveform signal 1.PRE 2.Cellx 3.M14. M2 5. ) Case II In this case NOR cam s of NAND type of SEG_1 is matched and one of OR cam s of NOR type of SEG_2 is mismatch. So M1 discharge to that turns on N1 and N3 and due to mismatch in NOR type block of SEG_2 the M2 discharge to ground.so N4 is off and remains high. Case III. In this case the NAND type block of SEG_1 and NOR type block of SEG_2 are matched. So M1 discharge to ground which turns on the transistor N1 and N3.Since NOR type of SEG_2 is mismatched, the M2 remains high which turns on N4 so the is discharged to ground either through T1 or T2 path. As T1 path is the shortest path to discharge the to ground ence this design is the best in search performance also. 37

V EPERIMENTAL RESULTS In this paper,we use CMOS.18 um technology for our design.we have compared the matchline delay and power between the Matchline delay is delay between when PRE signal is asserted IG and when matchline() discharges to ZERO. In hybrid type we vary the SEG_1 length 1 to 2 correspoinding SEG_2 length is 31 and 3. In this paper we have taken average power[5],[6],[7] which is equal to P av = [(1/T) T ( V I) dt. The delay and power of hybrid has been taken when both SEG_1 and SEG_2 is matched. (6T SRAM store unit) (4T SRAM store unit) OR (Power NOR (Power uw) AREA (OR or uw) NOR) 3.47 2.956 9.769.45 2.642 2.661 9.18 7.28 Table 2 Comparison of 9T and 7T Delay (ns) ybrid (6T SRAM ) ybrid (4T SRAM) 1.499.328 2.533.388 Table 3 ybrid Delay comparison Power (mw) ybrid (6T SRAM ) 1.149.924 2.866.779 ybrid (4T SRAM) Table 4 ybrid Power comparison Energy (fj) ybrid (6T SRAM ) ybrid (4T SRAM) 1 5.234 3.31 2 4.616 3.22 Table 5 ybrid Energy comparison 38

Fig 9 Layout of OR of conventional VI CONCLUSION Fig 1 Layout of OR (of 4T loadless SRAM based ). The hybrid- design of conventional has low power consumption comparison to other. In this paper the proposed seven transistor loadless SRAM based has low area and power as compared to the conventional hybrid. REFERENCES [1].. Miyatake, M. Tanaka, and Y. Mori, A design for high speed lowpower CMOS fully parallel contentaddressable memory macros, IEEE J. Solid-State Circuits, vol. 36, pp. 956 968, June 21. 39

[2] K. Pagiamtzis and A. Sheikholeslami, Content- addressable memory () circuits and architectures: A tutorial and survey, IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 712 727, Mar. 26 [3] Jinshen Yang, Li Chen A New Loadless 4-Transistor SRAM Cell with a.18 um CMOS technology IEEE 27 [4] Yen-Jen Chang and Yuan ong Liao ybrid-type design for both power and performance efficiency in VLSI systems,vol No:8 Aug 28 [5]www.egr.msu.edu/classes/ece41/mason/files/guidepower.pdf [6]http://www.ece.ncsu.edu/asic/ece733/hw/energy.pdf [7]http://www.ece.cmu.edu/~ee52 power.html 31