Low-Power SRAM and ROM Memories

Transcription

1 Low-Power SRAM and ROM Memories Jean-Marc Masgonty 1, Stefan Cserveny 1, Christian Piguet 1,2 1 CSEM, Neuchâtel, Switzerland 2 LAP-EPFL Lausanne, Switzerland Abstract. Memories are a main concern in low-power and high-speed designs. In a processor based SoC (System on Chip), they limit most of the time the speed and are the main part of the power consumption. For SRAM memories in 0.25µm, several improved low-power techniques have been applied, such as divided word lines at word level, physically split bitlines and a new asymmetrical RAM cell. Furthermore, to be capable of working at any supply voltage, and to take advantage of the new cell, sense amplifiers have been removed. This simple solution avoids noise problems, and in spite of the full swing on bitlines, the results show that power consumption performances are quite interesting: for a 8 Kbytes SRAM, at 0.8 Volt, the access time is 74 ns while consuming 7 ua/mhz (at 2.5 Volts, the access time is 3.5 ns and the power consumption 22 ua/mhz). 1 Introduction For innovative portable and wireless devices, Systems on Chip (SoCs) containing several processors, memories and specialized modules are obviously required. Performances but also low-power are main issues in the design of such SoCs. In deep submicron technologies, SoCs contain several millions of transistors and have to work at lower and lower supply voltages to avoid too high power consumption. Consequently, digital libraries as well as ROM and SRAM memories have to be designed to work at very low supply voltages and to be very robust while considering wire delays, signal input slopes, noise and crosstalk effects. Low-power SoCs will be based on low-power components, such as processor cores, memories and libraries that are available with nice performances, i.e to MIPS/watt [1] for some cores (using low-power techniques such as gated clocks). However, memories are the main consumers on a SoC [2, 3] and several techniques at the architecture and electrical levels have to be applied to reduce their power consumption (generally based on caches, DWL, bitline splitting, low swing).

2 Low-Power SRAM and ROM Memories Memories at the Architecture Level Memory organization is very important in systems on a chip. Generally, memories consume most of the power. So it comes immediately that memories have to be designed hierarchically. No memory technology can simultaneously maximize speed and capacity at lowest cost and power. Data for immediate use is stored in expensive registers, in cache memories and less used data in large memories. For each application, the choice of the memory architecture is very important. One has to think to hierarchical, parallel, interleaved and cache memories, sometimes several levels of cache, to try to find the best tradeoff. The application algorithm has to be analyzed from the data point of view, the organization of the data arrays, how to access these structured data. As memories in SoCs are larger and larger, the ratio between power consumption of memories to the power consumption of emb edded processors is significantly increased. Several solutions have been proposed at the memory architecture level, such as, for instance, cache memories, loop buffers and hierarchical memories, i. e. to store a frequently executed piece of code in a small embedded ROM memory and large but rare executed pieces of code in a large ROM memory [4]. It is also possible to read the large ROM in 2 or 4 clock cycles as its read access time is too large for the chosen main frequency of the microprocessor. Cache memories are widely used for high-performance microprocessors. In SoCs, application software is stored in embedded memories, ROM, flash or EEPROM. If a conventional N-way Set-Associative cache is used, one has to compare the energy used for a ROM access and the energy for a SRAM cache access. While reading N tags and N blocks of the selected cache line just to select one instruction (hundreds of bits), one can see that a conventional cache consumes much more power than a ROM access. The only way to save power is to use unconventional cache memories such as small L0 caches or buffers, which store only some instructions that are reused frequently from the cache. Such a scheme is used for some DSP processors to capture loops. 3 Electrical Design of Low Power SRAM Memories Low power and fast SRAM memories have been described in many papers [5]. Very advanced technologies have been used with double VT. RAM cells are designed with high VT and selection logic with low VT transistors [6]. Some techniques such as low swing and hierarchical sense amplifiers have been used. One can also use the fact that a RAM memory is read 85% of the time and written only 15% of the time. 3.1 New SRAM cell Low-power RAM memories designed by CSEM are based on a new SRAM cell (patent pending). This RAM cell is based on non-symmetrical ways to read and to

3 7.4.3 J.M.Masgonty et al. write the memory. The idea is to write in a conventional way while using the true and inverted bitlines, but to read only through a single bitline (Fig. 1). The advantages are the following: - as it is the case in the conventional scheme, it is possible to write at low Vdd since both true and inverted bitlines on both sides of the cell are used. - the use of only one bitline for reading (instead of two) decreases the power consumption. - since the read condition (to achieve a read and not to overwrite the cell) has only to be effective on one side of the cell, some transistors can be kept minimal. It decreases the capacitance on the inverted-bitline and the power consumption when writing the RAM. Furthermore, minimal transistors result in a better ratio between cell transistors when reading the memory, resulting in a speed-up of the read mechanism. - due to a read process only on one side of the cell, one can use more easily the split bitlines concept (Fig. 3). wr ite Vdd wr ite Sel P1 P2 Sel 1 S N1 2 N S2 Inverted Bitline re ad Figure 1. Asymmetrical SRAM cell Vs minimal sized MOS 3.2 SRAM Architecture The architecture of the SRAM memory is based on the precharge of the bitlines. The address decoder is implemented in reliable static logic. However, for large memories, without any speed-up technique, the precharge and access time could be very long. After the bitlines precharge, the access time consists of the time necessary to select the SRAM cells by the wordlines, of the time necessary to discharge the selected bitlines and the time necessary to read the value of the selected word on the bitlines. Many techniques have been used to speed-up existing SRAM memories:

4 Low-Power SRAM and ROM Memories to split the memory in several arrays, - divided word lines (DWL), - to divide the bit line, - to precharge only the useful bitlines, - partial swing with sense amplifiers. Some of these techniques were optimized in the presented SRAM memories as described in the following. 3.3 Divided Wordlines at the Word Level In order to minimize power and maximize speed, the well-known DWL (divided word line) principle is used fro the CSEM SRAM memories. With each main wordline (a row) divided into local wordlines (local row decoders for each block), only the cells of a block are selected in a given row. Furthermore, DWL with a block size equal to a word is implemented in order to switch the minimum number of bitlines (x bitlines for x bits in a word) for minimum power consumption (Fig. 2). There is an improvement also for the selection due to a reduced capacitance of the main wordline. Word selection Row selection address decoders Column selection RAM cell Figure 2. Divided Word Line at the word level 3.4 Physically Split Bitlines Since a large part of the access time is due to the discharge of the bitlines, split bitlines are used in the SRAM memory architecture. Figure 3 presents the split bitlines principle as used here with three sub-bitlines as example. Each bitline is split in subbitlines but they are not connected to the main bitline with additional transistors (as it is generally the case, with a negative impact on the speed). The SRAM cells are

5 7.4.5 J.M.Masgonty et al. connected directly to a sub-bitline that is a single metal line. Since only a fraction of the SRAM cell select transistor drains are connected to a given sub-bitline, the capacitance to be discharged is significantly reduced. After precharge, all sub-bitlines are at Vdd. As soon as a word is selected, only the corresponding sub-bitline can switch to Vss if the selected cell is programmed accordingly (transistor N1 is on in Figure 1), else all sub-bitlines stay high (Fig. 3). At precharge, only the sub-bitlines, which discharged to Vss at read, need to be charged back to Vdd. A NAND gate detects the read value. In this solution, each "read" bitline is split "physically" in the layout, not "logically" as in other solutions with local decoders. Bit array Vdd Physically Split bitlines Vdd Vdd Sub bitlines Result Figure 3. Split Bitlines 3.5 No Sense Amplifier The third technique aims at removing the sense amplifiers. It allows the SRAM memory to be capable of working at any supply voltage and to take advantage of the asymmetrical cell with only one read bitline. Noise problems are therefore strongly reduced, as sense amplifiers are very sensitive to noise. Furthermore, it is a very simple solution, as there is no need to detect when the read operation is finished to disable the sense amplifiers. Even if without sense amplifiers the bitlines have to switch a full swing, which is bad for the power consumption, their absence makes possible the more important power saving techniques related to the asymmetrical cell

6 Low-Power SRAM and ROM Memories with the single physically split read bitlines. The results show that power consumption is reduced, as shown in the next Section. 4 Results Tables 1, 2, 3 and 4 show some simulated results depending on the supply voltage. The power consumption for the 64K*16 memories are not simulated but estimated. The speed and power consumption shown in these tables compare well with results of other memories. Table 5 shows some comparison with other SRAM memories. As mentioned, the CSEM SRAM memory achieves a full swing without any sense amplifier. Size Vdd Access_time Frequency Consumption SRAM 4k * V 3.0 ns 167 MHz 33 ua/mhz SRAM 8k * V 3.5 ns 143 MHz 22 ua/mhz SRAM 64k * V 7.5 ns 67 MHz 49 ua/mhz Table 1. Performances of CSEM SRAM Memory at 2.5 V. and 0.25 µm Size Vdd Access_time Frequency Consumption SRAM 2k * V 2.2 ns 225 MHz 10 ua/mhz SRAM 4k * V 4.4 ns 110 MHz 22 ua/mhz SRAM 8k * V 5.3 ns 95 MHz 15 ua/mhz SRAM 64k * V 11 ns 45 MHz 39 ua/mhz Table 2. Performances of CSEM SRAM Memory at 1.8 V. and 0.25 µm Size Vdd Access_time Frequency Consumption SRAM 4k * V 11 ns 45 MHz 14 ua/mhz SRAM 8k * V 13 ns 38 MHz 10 ua/mhz SRAM 64k * V 26 ns 19 MHz 24 ua/mhz Table 3. Performances of CSEM SRAM Memory at 1.2 V. and 0.25 µm Size Vdd Access_time Frequency Consumption SRAM 4k * V 65 ns 7.7 MHz 9 ua/mhz SRAM 8k * V 74 ns 6.7 MHz 7 ua/mhz SRAM 64k * V 180 ns 2.8 MHz 18 ua/mhz Table 4. Performances of CSEM SRAM Memory at 0.8 V. and 0.25 µm

7 7.4.7 J.M.Masgonty et al. Company techno size supply access time power Virage Logic [7] 0.25 µm 2K * V. 2.5 ns 116 µa/mhz CSEM 0.25 µm 4K * V. 3 ns 33 µa/mhz Ref. [8] 0.5 µm 256* V. 20 ns 26 µa/mhz Ref [9] 0.25 µm 8K * V. 3 ns 125 µa/mhz CSEM 0.25 µm 4K * V. 10 ns 14 µa/mhz Ref [9] 0.25 µm 8K * V. 5.5 ns 85 µa/mhz CSEM 0.25 µm 4K * V. 65 ns 9 µa/mhz Table 5. Performance Comparison of SRAM memories in 0.25 µm 5 Electrical Design of Low-Power ROM Memories There are few papers describing very low-power ROM structures [10, 11]. A ROM memory is an array of transistors (a transistor means a logical bit 0 ). Each bit is connected to a bitline to read the ROM and controlled by a wordline. Precharge technique is used for the bitlines, but the address decoder is implemented in reliable static logic. First the address is provided then decoded as well as the bit array is precharged and finally the ROM is read. For the design of very low-power ROM memories, the same techniques presented above for the SRAM, i.e. DWL at the word level, physically split bitlines and removal of sense amplifiers, have been used. Without sense amplifier, there is no supply voltage dependency. There is some area penalty due to the DWL blocks. However, good speed performances for large size memories are obtained and power consumption is kept low. Table 6 shows the results in power and speed in a 0.25 µm process. techno size Supply access time power Ref. [10] 0.18 µm 8K * V. NA 110 µa/mhz Ref. [10] 0.18 µm 64K * V. NA 355 µa/mhz CSEM 0.25 µm 64 Kbytes 2.5 V. 3 ns 20 µa/mhz Table 6. ROM Memories power consumption Comparison

8 Low-Power SRAM and ROM Memories Conclusion Some innovative and patented features have been introduced in the design of lowpower ROM and SRAM memories, such as the removal of sense amplifiers and an asymmetrical RAM cell, providing interesting results in speed and power consumption in a 0.25 µm technology. References [1] C. Arm, J-M. Masgonty, C. Piguet, Double-Latch Clocking Scheme for Low-Power I.P. Cores, PATMOS 2000, Goettingen, Germany, September 13-15, [2] J-M. Puiatti, E. Sanchez, J. Llosa, C. Piguet, "Low-Power Embedded VLIW Processors: A High-Level Evaluation", ESSCIRC'98, September 21-24, 1998, Den Haag, The Netherlands, pp [3] F. Rampogna, J-M. Masgonty, C. Piguet, Hardware-Software Co-simulation and Power Estimation Environment for Low-Power ASICs and SoCs, DATE 2000, Proc. User Forum, pp , Paris, March [4] C. Piguet et al. "Low-Power Design of 8-bit Embedded CoolRISC Microcontroller Cores", IEEE JSSC, Vol. 32, No 7, July 1997, pp [5] K. Itoh at al. Trends in Low-Power RAM Circuit Technologies, Proc. IEEE, Vol. 83, No 4, April 1995, pp [6] H. Morimura et al. «A Shared-Bitline SRAM Cell Architecture for 1-V Ultra Low-Power Word-Bit Configurable Macrocells, Proc. ISLPED 1999, San Diego, USA. [7] [8] N. Tzartzanis et al. «A Low-Power SRAM with Resonantly Powered Data, Address, Word and Bit Lines, Proc. ESSCIRC 2000, Sept , 2000, Stockholm, pp [9] Private Communication [10] A. Turier et al. «Générateurs de ROMs basse consommation», FTFC 99, May 26-28, 1999, Paris, pp [11] A. Turier, Ph.D. Thesis, «Etude, Conception et Caractérisation de mémoires CMOS, faible consommation, faible tension en technologies submicroniques», University of Paris VI, Pierre et Marie Curie, France, December 13, 2000.