FeRAM Circuit Technology for System on a Chip

Transcription

1 FeRAM Circuit Technology for System on a Chip K. Asari 1,2,4, Y. Mitsuyama 2, T. Onoye 2, I. Shirakawa 2, H. Hirano 1, T. Honda 1, T. Otsuki 1, T. Baba 3, T. Meng 4 1 Matsushita Electronics Corp., Osaka, Japan 2 Osaka Univ., Osaka, Japan 3 Panasonic Technologies Inc., Cupertino, CA 4 Stanford Univ., Stanford, CA Abstract The ferroelectric memory (FeRAM) has a great advantage for system on a chip, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM. To enhance the applicability of FeRAM for embedded reconfigurable hardware, three circuit technologies are discussed in this paper. Simulation and measurement data confirmed that both power consumption and memory area can be substantially reduced, making FeRAM the most promising new technology for implementing high-performance, lowpower reconfigurable hardware. lose data after power-off. As for EEPROM, long write times and high supply voltages prevent them from delivering practical system-on-a-chip solutions. In this paper, we demonstrate the use of ferroelectric non-volatile memory (FeRAM) as a novel reconfigurable engine, which not only allows a fast write time and low power consumption, but also leads to high efficiency of memory usage. As shown in Fig. 1, the memory in a FeRAM-based reconfigurable hardware can be used for storing the logic configuration data, the instructions for embedded processors, and at the same time serves as a RAM for data accessing. 1 Introduction Hardware programmability is indispensable for ULSIs today in terms of flexibility for multiple applications and redundancy against design failures. Recently, both academia and industry have been actively engaged in the development of a variety of architectures, design strategies, and system integration of reconfigurable logic technology. For example, the Garp architecture [1], which integrates reconfigurable logic with a general-purpose processor, aims to accelerate the execution of signal processing applications. IRAM [2], which combines memory with vector processing, can be categorized as another form of reconfigurable logic, while ARCA [3] focuses on the aspect of fault tolerance. Recently, a multi-context reconfigurable architecture based on 3-Transistor DRAM [4] has been demonstrated to have a relatively short reconfiguration time. In the conventional reconfigurable logic, a memory such as SRAM, DRAM or EEPROM is embedded in the system to store the logic configuration data. SRAM and DRAM are not suitable for portable devices because these memories Fig.1 Advantage of FeRAM Embedded Reconfigurable Hardware An array of reconfigurable elements based on FeRAM can be arranged as shown in Fig.2, where a microprocessor unit (MPU) is located at the center of the chip, while reconfigurable array elements are located around the rest of the chip. The switching elements connect the reconfigurable array elements to each other. A set of multiple configuration data for each array

2 ferroelectric capacitor which stores the data H and that of data L (see Fig.3(a)), which cannot be easily accommodated due to the temperature dependency and process margin. Therefore the 1T/2C (1 transistor and 2 capacitors per cell) memory cell [7] and self-reference reading scheme [8] were reported recently using complementary sense amplifiers. As a result, the reconfiguration data has to be read twice from the FeRAM into the latch circuit and lookup table (LUT) in the reconfigurable logic shown in Fig.2. Fig.2 Architecture of FeRAM Embedded Reconfigurable Hardware element is stored locally in the FeRAM. We have reported a FeRAM embedded reconfigurable hardware using multi-mode and multi-level technologies that contributes low power consumption and small chip area size [5]. In this paper, a fast reconfiguration technology which is suitable for system on a chip is proposed. Our FeRAM embedded reconfigurable hardware has the following three features: 1) a novel read circuit to achieve fast reconfiguration; 2) two (ROM and RAM) operating modes designed for lower power consumption; and 3) multi-level memory technology to increase the efficiency of memory usage. 2 Fast Reconfiguration Circuit Figure 3 illustrates the comparison between the proposed and conventional read circuits of FeRAM, in which the measured V-Q hysteresis curves of the ferroelectric capacitor and the HSPICE simulation waveforms are depicted. In the conventional reading scheme [6], the threshold voltage has to be generated precisely between the bitline voltage charged from the Fig.3(a) Conventional Reading Scheme

3 On the contrary, the read circuit shown in Fig. 3(b) uses the gate input sense amplifier and cell plate (CP) pulse input to solve this problem. The bitline (BL) and CP are pre-charged to a certain voltage before reading the charge from ferroelectric capacitors. As shown in Fig.3(b), since the pre-charged voltage becomes the threshold voltage after reading the stored charge of the memory capacitor, stable threshold voltage can be provided without any precise control. In other words, the voltage of t3(l) is always lower than the pre-charge voltage and the voltage of t3(h) is always higher than the pre-charge voltage. Consequently, the duration of a configuration update is halved comparing to the conventional 1T/1C FeRAM scheme. The new read circuit also reduces power consumption since the charge and discharge of bitline are only half of that of the conventional one, which needs to perform the read function twice using complementary bitlines. 3 Design of Low-Power ROM and RAM Modes Our architecture offers two special operating modes, the ROM mode and RAM mode, to reduce power consumption. Since the majority of power is consumed in the charge and discharge of bitlines, we designed the FeRAM to adopt the following power reduction approach. The state transitions of the ferroelectric capacitor hysteresis during ROM/RAM reads and writes are shown in Fig.4(a)-(d) by using the measured hysteresis data. As shown in Fig.4(a), ROM data have to be written at a high saturation voltage in order to hold the data after power-off. However, RAM data need not be written at such a high voltage (Fig.4(b)). As evident in Figs. 4(c) and 4(d), read operations in either the ROM or RAM mode do not require high voltages as well, since the circuit only needs to detect the difference between data H and data L. Therefore, the power supply voltage can be adjusted and only be raised to a high voltage when a ROM write is performed. By using separate ROM/RAM modes, the total power consumption can be reduced since the ROM write operation occurs in a much lower probability than that of the ROM write and RAM operations. Fig.4 (a) ROM Write Mode (b) RAM Write Mode (c) ROM Read Mode (d) RAM Read Mode Fig.3(b) Proposed Reading Scheme

4 4 Multi-Level Logic Architecture Multi-level technology is extremely effective in the case where memory space is limited. Figure 5(a) shows an example of 4-level logic memory which contains 2 bits/cell. In this technology, RAM data are stored upon ROM data as shown in Fig.5(a), by using the characteristics that FeRAM can be operated at a low voltage in the RAM mode. That is, in reading or writing a RAM bit when the ROM bit holds a high level, the RAM cell converges to either the state 3(1,1) or the state 2(1,0), depending on the value of the RAM bit. In a similar fashion, when the ROM bit holds a low level, the RAM cell converge to either the state 1(0,1) or the state 0(0,0). Consequently, RAM data can be read at a low voltage while the information of the overlapped ROM data is kept in the high energy potential during the operation. This method reduces the power consumption compared with the method that reads all data at a high voltage, as shown in Fig.5(b). One problem with the above scheme is that the RAM bit can be erased after a ROM access, since the RAM data are stored in the low energy potential. We implemented a 3-pulse accessing scheme that uses only one latch circuit to store the RAM data temporally, as shown in Fig.5(c). The RAM data can be re-written over the ROM data after its accessing. This multi-level technology contributes to highly efficient memory space usage. It also has the advantage of low power consumption in the case where RAM operations occur more frequently than ROM operations. Fig.5(c) 3-pulse accessing scheme 5 Experiment Data Fig.5(a) Proposed 4-Level FeRAM (A RAM data is superimposed on a ROM data) To demonstrate the practicability of the FeRAM reconfigurable hardware, a number of experiments have been conducted. The comparisons of power consumption are summarized in Table 1, which were obtained through HSPICE simulations in conjunction with the measured hysteresis curves in Figs. 3 and 4. As can be seen from Table 1, power consumption is considerably reduced in the case of RAM operations. The data in Table 1 were obtained from simulating a 128x32 FeRAM at 10MHz frequency. Multi-level technology contributes significantly to area efficiency. Furthermore, the multi-level logic also reduces the total power consumption by approximately 30%, assuming that the same amounts of ROM and RAM operations are used. Fig.5(b) 4-Level FeRAM (All data are read at a high voltage)

5 Table 1 Comparison of Power Consumption Acknowledgments The authors thank K. Arita and T. Takayama for their measurements and helpful discussions. The authors appreciate to G. Kano, M. Kazumura, and T. Chikamura for their encouragement. The members of Osaka University, Stanford University and Matsushita Electronics Corporation are also appreciated for their support. References Fig.6 Comparison among ROM/RAM Mode, Multi- Level and Conventional Scheme [1] J.R. Hauser and J. Wawrzynek, Garp: A MIPS processor with a reconfigurable coprocessor, in Proc. IEEE Symp. FCCM 97, April [2] D. Patterson et. al., A case for intelligent RAM: IRAM, IEEE Micro, April [3] A. Shibayama et al., An autonomous reconfigurable cell array for fault-tolerant LSIs, ISSCC Digest of Tech. Papers, [4] E. Tau et al., A first generation DPGA implementation, in Proc. Third Canadian Workshop of Field-Programmable Devices, May [5] K. Asari et al., Multi-Mode and Multi-Level Technologies for FeRAM Embedded Reconfigurable Hardware, ISSCC Digest of Tech. Papers, [6] T. Sumi, Ferroelectric nonvolatile memory technology, IEICE Trans. Electron., Vol. E79-C, no.6, pp , June [7] N. Tanabe et. al., High Tolerance Operation of 1T/2C FeRAMs for the Variation of Cell Capacitors Characteristics, Symposium on VLSI Technology Digest of Technical Papers, 1998 [8] J. Yamada, A Self-Reference Read Scheme for a 1T/1C FeRAM, Symposium on VLSI Technology Digest of Technical Papers, Conclusions We have demonstrated three novel technologies for the FeRAM embedded reconfigurable hardware in this paper. The first feature is a fast reconfiguration by using a constant precharged voltage for the threshold level of 1T/1C type FeRAM. The second feature is the multioperating modes (ROM and RAM mode) for low power consumption. At last, the multi-level memory technology realizes high efficient memory usage and also achieves lower power consumption against the conventional method. These three features improve the performance of the reconfigurable hardware.