HT655 SPP/EPP/ECP Controller Features Multi-mode parallel port controller Standard mode: IBM PC/XT, PC/AT and PS/ compatible bidirectional parallel port General Description The Parallel Port Controller incorporates one IBM XT/AT compatible parallel port and support the PS/ type bidirectional parallel port, the enhanced parallel port (EPP) and the extended capabilities port (ECP) modes. Refer to the Hardware/Software configuration description for information on changing the base address, selecting the mode of operation and setting the FIFO threshold that is used in ECP operation. EPP retains complete backward compatibility with the existing XT/AT and PS/ compatible Enhanced parallel port (EPP) mode Extended capabilities port (ECP) mode Support 6 base address 68-pin PLCC package functions and interface. EPP can provide high performance for bidirectional block mode data transfer. This is largely accomplished through hardware handshake. ECP is software and hardware-compatible with existing parallel ports. It provides an automatic high-burst bandwidth channel that supports DMA for ECP in both the forward and reverse directions. This chip supports 6-byte FIFO to smooth data flow and improves the bandwidth requirement. It also supports run-length encode (RLE) decompression in hardware. 0th Jan 96
HT655 Block Diagram Pin Assignments 0th Jan 96
HT655 Pin Description Pin No. Pin Name I/O Description ~8, ~4 5~7, 9~ SA [0:0] SD [7:0] I/O 4 IORDY O I These host address bits determine the I/O address to be accessed during IORZ and IOWZ cycles. The ISA data bus used by the host microprocessor to transmit data to or from this chip. Normally, this pin used as IORDY to extended the read/write command in EPP mode. 5 IOWZ I This active low signal is issued by the host microprocessor to indicate a write operation. 8 CLK/TESTI I 4.8 MHz OSC input or 4MHz crystal input. 9 TESTO O 4 MHz crystal output. IORZ I TC I DACKZ I 4 DRQ O 6 IRQ O This active low signal is issued by the host microprocessor to indicate a read operation. This signal indicates to this chip that DMA operation data transfer is complete. An active low input acknowledging the request for a DMA transfer of data. This active high output is the DMA request for byte transfers of data to the host. This pulse low output is the interrupt request signal. Note that this signal needs an external pull-up resistor connected. 7 AEN I Active low address enable indicates microprocessor operations on the host data bus. 8 RESET I Active high input signal that resets this chip. 9~4 BA[:0] I 4 BUSY I 45 ACKZ I 46 PE I 47 SLCT I 48 ERRZ I Parallel port base address select inputs for hardware initial setup. This is a status input from the printer, high indicating that the printer is not ready to receive new data. A low active input from the printer indicating that it has received the data and is ready to accept new data. A status input from the printer, high indicating that the printer is out of paper. This high active output from the printer indicates that it has power on. A low on this input from the printer indicates that there is an error condition at the printer. 0th Jan 96
HT655 Pin No. Pin Name I/O Description 49 STRBZ O A low active pulse on this output is used to strobe the printer data into the printer. 50 AFDZ O This output goes low to cause the printer to automatically feed one line after each line is printed. 5 INITZ O This is used to initiate the printer when low. 5 SLTINZ O This active low output selects the printer. 54~59, 6,6 PD [7:0] I/O The bi-directional parallel data bus is used to transfer information between CPU and peripherals. 6,64 PMODE[:0] I Parallel port mode select inputs for hardware initial setup. 65 TEST I This input pin is for test. It must be pulled low. 66 NUMID I This input pin decides the chip number ID. Refer to hardware configuration for use of this pin. It is pulled up internally. 67~68 NC 9,6,0, 4,60 VDD Positive power supply inputs.,0,8,7, 5,44,5 VSS Ground reference power supply inputs. Absolute Maximum Ratings Supply Voltage....V to 5.5V Input Voltage... V SS 0.V to V DD+0.V Storage Temperature... 50 C to 5 C Operating Temperature... 0 C to 70 C 4 0th Jan 96
HT655 DC Characteristics (Ta=0 to 70 C, V DD=5V±5%, V SS=0V) Symbol Parameter Test Condition V DD Condition Min. Typ. Max. Unit V IL Input Low Voltage 5V 0. 0.8 V V IH Input High Voltage 5V.0 V DD+0. V I LIH Input High Leakage 5V V IN=V DD 0 µa I LIL Input Low Leakage 5V V IN=0V 0 µa V OL Output Low Voltage 5V I sink=6ma 0.4 V V OH Output High Voltage 5V I sour=6ma.4 V DD V C IN Input Capacitance 5V 5 PF C Output Capacitance 5V 0 PF I STBY Stand-by Current 5V 0 µa V T Threshold Voltage of CLK/TESTI Pin 5V.5 V I PULL-UP Input with Internal Pull-High current 5V V IN=0 50 500 µa Note : Stand-by current is measured with input gating, output unloading and CLK/TESTI=0. 5 0th Jan 96
HT655 Configuration Description Hardware Configuration Hardware configuration are defined through conditioning of PMODE [:0] and BA [:0] pins during power-on reset. PMODE PMODE 0 Parallel Port Mode 0 0 ISA Compatible 0 PS/ Compatible 0 EPP ECP BA BA BA0 Base Address 0 0 0 78 H 0 0 78 H 0 0 BCH 0 Disable 0 0 68H 0 6CH 0 7CH Disable When the chip is disabled, the ISA-interface output pins will become tri-state. Two controller chips can be used simultaneously on a board by pulling up or NC the NUMID pin as controller # and pulling low the NUMID pin as controller #. Refer to software configuration for use of this pin. for setting up the configuration registers are described as follow: To enter configuration mode * Write 55H to FAH twice. * Followed by writing AAH to FAH twice (if NUMID =), or writing 55H to FAH twice (if NUMID =0). To program configuration register * Write XXH to FAH, where XXH is the configuration register index * Followed by writing YYH to FAH, where YYH is the data for configuration register XXH. To exit from configuration mode Write 0FH to FAH, then write any value to FAH. The following describes the bit functions of each configuration register. Note that the configuration registers are all write only. Index 00: ECP FIFO threshold register (default value=00h) 0 0 0 0 0 Index 0: Parallel port mode register 0 PMODE PMODE0 0 0 ISA Compatible 0 PS/ Compatible 0 EPP ECP Software Configuration After RESET the default values will be loaded into the configuration registers. The procedures 6 0th Jan 96
HT655 * SPP data register read and write modes CTR5 IORZ IOWZ Result ISA Compatible X 0 Data written to PD[0:7] X 0 Data read from the output latch 0 0 Data written to PD[0:7] PS Compatible 0 Data written is latched 0 0 Data read from the output latch 0 Data read from PD[0:7] * EPP data register read and write modes CTR5 IORZ IOWZ Result X 0 Data written to PD[0:7] X 0 Data read from PD[0:7] Index 0: Base address register 0 BA BA BA0 0 0 0 78H 0 0 78H 0 0 BCH 0 Disable 0 0 68H 0 6CH 0 7CH Disable Note that the base address BCH, 6CH and 7CH cannot be selected for EPP mode. 7 0th Jan 96
Configuration example The following is an example of configuration program in 80X86 assembly language. ; ------------------------------------------------------------ ; Enter configuration mode ; ------------------------------------------------------------,, D X, FAH 55H FAH AAH ; if NUM ID= ; ------------------------------------------------------------ ; Program configuration registers ; ------------------------------------------------------------,,,,,, FAH 00H FAH YYH FAH 0H FAH YYH FAH 0H FAH YYH ; ------------------------------------------------------------ ; Exit configuration mode ; ------------------------------------------------------------,, FAH 0FH FAH XXH HT655 Note that if two controller are used, the configuration of controller # should begin after exiting the configuration mode of controller #. In EPP mode, if a time-out (0µs approximately) occurs, the current EPP cycle is abort and the time-out condition is indicated in Status register bit 0 as a logic. To clear this time-out bit just write any value to Status register. 8 0th Jan 96
HT655 Timing Diagram Parallel port timing Parameter Min. Max. Units Notes t PD[7:0] delay from IOWZ inactive 60 ns t STRBZ, AFDZ, INITZ, SLTINZ delay from IOWZ inactive 00 ns t IRQ delay from ACKZ 70 ns t4 IRQ active low pulse width 800 ns t5 IRQ delay from ERRZ 80 ns 9 0th Jan 96
HT655 EPP address or data WRITE cycle timing Parameter Min. Max. Units Notes t IOWZ asserted to IORDY asserted 0 80 ns t IOWZ asserted to STRBZ asserted 40 40 ns t IOWZ asserted to PD[7:0] valid 50 ns t4 time out 0 µs t5 STRBZ asserted to AFDZ, SLTINZ asserted 70 80 ns t6 AFDZ, SLTINZ asserted to BUSY asserted 0 ns t7 BUSY asserted to IORDY deasserted 70 40 ns t8 BUSY asserted to AFDZ, SLTINZ deasserted 70 40 ns t9 AFDZ, SLTINZ deasserted to BUSY deasserted 0 t0 BUSY deasserted to STRBZ deasserted 70 40 ns t BUSY deasserted to PD[7:0] invalid 40 ns 0 0th Jan 96
HT655 EPP address or data READ cycle timing Parameter Min. Max. Units Notes t IORZ asserted to IORDY asserted 0 80 ns t IORZ asserted to STRBZ deasserted 0 ns t IORZ asserted to PD[7:0] Hi-Z 0 70 ns t4 time out 0 µs t5 PD[7:0] Hi-Z to AFDZ, SLTINZ asserted 40 0 ns t6 AFDZ, SLTINZ to PD[7:0] valid 0 ns t7 PD[7:0] valid to BUSY asserted 0 ns t8 BUSY asserted to IORDY deasserted 70 40 ns t9 BUSY asserted to AFDZ, SLTINZ deasserted 70 40 ns t0 AFDZ, SLTINZ deasserted to PD[7:0] Hi-Z 0 ns t PD[7:0] Hi-Z to BUSY deasserted 0 ns 0th Jan 96
HT655 ECP parallel port FIFO mode timing Parameter Min. Max. Units Notes t PD[7:0] valid to STRBZ active 500 ns t STRBZ active pulse width 500 ns t PD[7:0] hold from STRBZ inactive 500 ns t4 BUSY inactive to STRBZ active 900 ns ECP parallel port forward timing Parameter Min. Max. Units Notes t PD[7:0] valid to STRBZ asserted 0 80 ns t AFDZ valid to STRBZ asserted 0 70 ns t STRBZ asserted to BUSY asserted 0 ns t4 BUSY asserted to STRBZ deasserted 70 40 ns t5 STRBZ deasserted to BUSY deasserted 0 ns t6 BUSY deasserted to PD[7:0] changed 40 70 ns t7 BUSY deasserted to STRBZ asserted 560 850 ns. Maximum value only applies if there is data in the FIFO waiting to be written out. 0th Jan 96
HT655 ECP parallel port reverse timing Parameter Min. Max. Units Notes t PD[7:0], BUSY valid to ACKZ asserted 0 ns t ACKZ asserted to AFDZ deasserted 40 0 ns t AFDZ asserted to ACKZ deasserted 0 ns t4 ACKZ deasserted to AFDZ asserted 00 50 ns t5 AFDZ asserted to PD[7:0] changed 0 ns t6 AFDZ asserted to ACKZ asserted 0 ns. Maximum value only applies if there is room in FIFO and a terminal count has not been received. 0th Jan 96
HT655 Application Circuit IRQA IRQB J6 RESET IRQ9 IOWZ IORZ DACKZ DRQ DACKZ DRQ IRQ7 IRQ6 IRQ5 IRQ4 IRQ TC CLK 4 5 6 7 8 9 40 4 4 4 44 45 46 47 48 49 50 5 5 5 54 55 56 57 58 59 60 6 6 SLOT B B B B4 B5 B6 B7 B8 B9 B0 B B B B4 B5 B6 B7 B8 B9 B0 B B B B4 B5 B6 B7 B8 B9 B0 B SLOT-6P A A A A4 4 A5 5 A6 6 A7 7 A8 8 A9 9 A0 0 A A A A4 4 A5 5 A6 6 A7 7 A8 8 A9 9 A0 0 A A A A4 4 A5 5 A6 6 A7 7 A8 8 A9 9 A0 0 A N UM I D T ES T R7 4.7K R6 4.7K R8 0K R6 0K R7 0K I I I OR RQ RQ D A B Y J5 4 5 6 7 8 9 0 HEADER 6X IRQ IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 J 4 5 6 7 8 9 0 HEADER 6X IRQ IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 J5 J4 J J R5 R4 R R 0K 0K 0K 0K N T P S S S S S S S UM ES MOD A4 A5 A6 A7 A8 A9 A I T 0 D E 00 P MO D E0 PD00 PD0 9 8 7 6 5 4 6 6 6 6 6 6 6 6 8 7 5 4 U SD7 SD6 SD5 SD4 SD SD SD SD7 SD0 SD6 IORDY SD5 AEN SD4 SD SD SD SA0 SA9 SA8 SA7 SA6 SA5 SA4 SA SA SA SA0 SA SA SA SA0 SD0 IORDY IOWZ CLK 0 V S S S S S S S V N N N T P P P P VSS DD A4 A5 A6 A7 A8 A9 A SS C C UM ES MO MO D0 D SA 0 I T D D SA D E0 E 4 SA SA0 5 6 SD7 SD6 7 8 SD5 HT-655 9 VSS (68-pin PLCC) SD4 0 SD SD C SD LK 4 SD0 / 5 IORDY TE T D R IOWZ ES I AC ES B 6 VDD V S V OR D V I A B B B US V SS TI T DD T K RQ SS RQ EN E A A A0 DD O Z C Z T Y 4 4 4 4 7 8 9 0 4 5 6 7 8 9 0 R4 0K C LK I C LK O I OR Z T D D I A R C AC RQ RQ EN ES K ZA A A E T B A0 B A0 B A0 0 B US Y 0 VDD PD PD PD4 PD5 PD6 PD7 SLTINZ VSS INITZ AFDZ STRBZ ERRZ SLCT PE ACKZ VSS 44 45 46 47 48 49 50 5 5 5 54 55 56 57 58 59 60 J7 J4 D RQ D RQ D RQ D RQ D RQ A D RQ B J6 J D AC K Z D AC D AC K K Z ZA SA SA SA SA0 SD7 SD6 D SD5 AC SD4 K Z SD SD SD SD0 IORDY D D IOWZ AC AC K Z K ZB 9 N T P P S S S S S S S UM ES MOD MO A4 A5 A6 A7 A8 A9 A I T D 0 D E E 0 PD0 PD 8 7 6 0 V S S S S S S S V N N N T P P P P VSS DD A4 A5 A6 A7 A8 A9 A SS C C UM ES MO MO D0 D SA 0 I T D D SA D E0 E 4 SA 5 SA0 SD7 6 7 SD6 8 SD5 HT-655 VSS 9 (68 Pin PLCC) 0 SD4 SD SD C SD LK SD0 4 / 5 IORDY TE T D R 6 IOWZ ES I AC ES B VDD V S V OR D V I A B B B US V SS TI T DD T K RQ SS RQ EN E A A A0 DD O Z C Z T Y 4 4 4 4 7 8 9 0 4 5 6 7 8 9 0 5 4 6 8 6 7 6 6 6 5 6 4 6 6 6 U VDD PD PD PD4 PD5 PD6 PD7 SLTINZ VSS INITZ AFDZ STRBZ ERRZ SLCT PE ACKZ VSS 44 45 46 47 48 49 50 5 5 5 54 55 56 57 58 59 60 C I T D D I A R B B B B LK OR C AC RQ RQ EN ES A A A US O Z K B B E 0 Y ZB T J J0 J9 J8 J7 R R R R R0 R9 0K 0K 0K 0K 0K 0K PMODE00 PMODE0 BA00 BA0 BA0 PMODE0 PMODE BA0 BA BA C9.uF C0.uF C.uF PD0 PD0 PD04 PD05 PD06 PD07 SLTINZ0 INITZ0 AFDZ0 STRBZ0 ERRZ0 SLCT0 PE0 ACKZ0 PD PD PD4 PD5 PD6 PD7 SLTINZ INITZ AFDZ STRBZ ERRZ SLCT PE ACKZ C C4.uF.uF C 0uF C C C0 C9 C8 C7 C6 C5 80PX8 STRBZ PD0 PD PD PD PD4 PD5 PD6 PD7 ACKZ BUSY PE SLCT C8 C7 C6 C5 C4 C C C 80PX8 C5 0uF RP 4.7K 7 6 5 4 98 CN STRBZ0 PD00 PD0 PD0 4 PD0 56 PD04 PD05 7 PD06 89 PD07 ACKZ0 0 BUSY0 PE0 SLCT0 4 5 6 7 8 9 0 4 5 AFDZ0 ERRZ0 INITZ0 SLTINZ0 DB5 CLKO X CLKI 4MHZ R5 00K C C4 5P 5P RP 4.7K 7 6 5 4 98 J 4 5 6 7 8 9 0 4 5 6 7 8 9 0 4 5 6 HEADER X AFDZ ERRZ INITZ SLTINZ Base addr. J9(J4) J0(J5) J(J 78H 78H BCH Disable 68H 6CH 7CH Disable - - - - - - - - - - - - - - - - - - - - - - - - PP Mode J7(J) J8(J) SPP PS/ EPP ECP - - - - - - - - 4 0th Jan 96