VHDL Examples By Mohamed Zaky (mz_rasmy@yahoo.co.uk) 1
Half Adder The Half Adder simply adds 2 input bits, to produce a sum & carry output. Here we want to add A + B to produce Sum (S) and carry (C). A B HALF ADDER Sum (S) Carry (C) Truth Table A B S C 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Designing Logic Circuit S = AB + AB (XOR) C = AB (AND) VHDL code HALF ADDER Entity entity HALFADD is port ( A,B : in bit; S,C : out bit ); end HALFADD; Architecture architecture struct of HALFADD is begin S <= A xor B; C <= A and B; end struct; MZ 2
Full Adder (1 bit) The Full Adder operates on 3 inputs to produce a sum & carry output. C IN A B FULL ADDER Sum (S) C OUT We can design the Full Adder by using truth table and get its logic expression; but it s better to use the Half Adder we just designed to build the Full Adder. Since the Half Adder adds only 2 inputs while the Full Adder adds 3 inputs; then we can use 2 Half Adders to construct Full Adder. A B HALF ADDER 1 I2 I1 HALF ADDER 2 I3 Sum (S) C IN I2 OR C OUT Full Adder using 2 Half Adders & 1 OR gate To add a an already designed component to a new design First, add it as follows: 3
Syntax component ENTITYNAME (of the desired component) port (INPUTS : DATATYPE; OUTPUTS : DATATYPE); end component; Second, use the added component as a ready, functioning block (don t write its VHDL code again) Just use it as a block, having inputs & outputs. This is done using Port map, as follows: Syntax Label: ENTITYNAME (of the desired component) port map (INPUTS & OUTPUTS) It s that simple!! VHDL code FULL ADDER (1 bit) Entity entity FULLADD is port ( A,B,CIN : in bit; COUT,S: out bit); end FULLADD; Architecture architecture struct of FULLADD is Signals signal I1,I2,I3 : bit; use HALF ADDER component HALFADD port (A,B : in bit; S,C : out bit ); end component; Begin!! begin HA1:HALFADD port map (A,B,I1,I2); HA2:HALFADD port map (I1,CIN,S,I3); COUT <= I3 or I2; end struct; 4
MZ Full Adder (2 bit) We first made 2 bit Full Adder to make the idea of n-bit Full Adder clear. We made the 2 bit Full Adder using 2 (1 bit) Full Adders. Here is a simple block diagram of 2 bit Full Adder (In the case of 8 bit Full Adder we will have 8 Full Adder (FA#0 to FA#7)) a0 a1 co FA #0 c1 s0 FA #1 c2 s1 b0 b1 VHDL code 2 bit FULL ADDER Entity entity FULLADD2 is port (a0,b0,a1,b1,c0 :in bit; c2,s0,s1 :out bit); end FULLADD2; Architecture architecture struct of FULLADD2 is Signals signal c1:bit; use 1 bit FULL ADDER component FULLADD port ( A,B,CIN :in bit ; S,COUT : out bit); end component; Begin!! begin FA1:FULLADD port map(a0,b0,c0,s0,c1); FA2:FULLADD port map(a1,b1,c1,s1,c2); end struct; 5
MZ 4 bit Full Adder To understand this code, just draw its Block diagram exactly like 2 bit Full Adder (of course you will use 4 Full Adders) You can extend this code to any N bit Full Adders See Digital Electronics Reference of second year (Tocci) page 289. VHDL code 4 bit FULL ADDER Entity entity FULLADD4 is port (a0,b0,a1,b1,a2,b2,a3,b3,c0 :in bit; c4,s0,s1,s2,s3 :out bit); end FULLADD4; Architecture architecture struct of FULLADD4 is Signals signal c1,c2,c3 :bit; use 1 bit FULL ADDER component FULLADD port ( A,B,CIN :in bit ; S,COUT : out bit); end component; Begin!! begin FA1:FULLADD port map(a0,b0,c0,s0,c1); FA2:FULLADD port map(a1,b1,c1,s1,c2); FA3:FULLADD port map(a2,b2,c2,s2,c3); FA4:FULLADD port map(a3,b3,c3,s3,c4); end struct; MZ 6
DFF (flip flop) The new thing in this code is that we use CLK input. In VHDL, if you want to use CLK input then put it in a Process. Syntax PROCESS(clk) IF ( clk = '1') AND ( clk'event ) THEN here we work on positive going transition q <= d; END IF; END PROCESS; In the beginning of the code we wrote LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; The IEEE introduced many new Data Types, Here we used (std_logic_1164) which has a main benefit; that is its values are (1or High, 0 or Low & Don t Care). Here we might not want Don t Care condition; frankly I m not sure if we need this declaration or not. Any way it s better to call IEEE library (just as you call header files in C). 7
VHDL code D Flip-Flop LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; Entity ENTITY dff IS PORT( d, clk : IN std_logic; q : OUT std_logic); END dff; Architecture ARCHITECTURE structdff OF dff IS Begin!! PROCESS(clk) IF ( clk = '1') AND ( clk'event ) THEN q <= d; END IF; END PROCESS; END structdff; MZ 8
Shift Register (4 bit) A shift register is a group of Flip Flops (FFs) arranged so that the binary numbers stored in the FFs are shifted from one FF to the next for every clock pulse. We made a 4-bit Shift Register using DFFs. 4-bit Shift Register Block Diagram 9
VHDL code Shift Register LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; Entity ENTITY shiftreg IS PORT( a, clk : IN std_logic; b : OUT std_logic); END shiftreg; Architecture ARCHITECTURE structshift OF shiftreg IS COMPONENT dff PORT( d, clk : IN std_logic; q : OUT std_logic); END COMPONENT; SIGNAL z : std_logic_vector( 0 TO 4 ); z(0) <= a; dff1: dff PORT MAP( z(0), clk, z(1) ); dff2: dff PORT MAP( z(1), clk, z(2) ); dff3: dff PORT MAP( z(2), clk, z(3) ); dff4: dff PORT MAP( z(3), clk, z(4) ); b <= z(4); END structshift; 10
Multiplexer ( 4 in ; 2 select ; 1 out!! ) MUX VHDL code Multiplexer ( 4 in ; 2 select ; 1 out!! ) Entity ENTITY mux1 IS PORT ( a, b, c, d : IN BIT; s0, s1 : IN BIT; x : OUT BIT); END mux1; Architecture ARCHITECTURE seqmux OF mux1 IS Begin!! process (a, b, c, d, s0, s1 ) IF s0 = '0' and s1 = '0' THEN x <= a; ELSIF s0 = '1' and s1 = '0' THEN x <= b; ELSIF s0 = '0' and s1 = '1' THEN x <= c; ELSE x <= d; END IF; END process; END seqmux; MZ 11