MIPS Instructions: 64-bit Core Subset

MIPS Instructions: 64-bit Core Subset Spring 2008 General notes: a. R s, R t, and R d specify 64-bit general purpose registers b. F s, F t, and F d specify 64-bit floating point registers c. C d specifies 32-bit coprocessor 0 registers d. PC (Program Counter specifies the instruction address register and contains address of instruction in execution e. Square brackets ([] indicate the contents of f. I specifies part of instruction and its subscripts indicate bit positions of sub-fields g. indicates concatenation of bit fields h. << indicates shift left i. >> indicates shift (arithmetic or logicalright j. Superscripts indicate repetition of a binary value k. M{i} is contents of the doubleword (64 bits at the memory address i l. m{i} is contents of the byte (8 bits at the memory address i m. mm{i} is contents of the word (32 bits at the memory address i n. all integers are in 2 s complement representation if not indicated as unsigned 1. Doubleword Add: DADD 00000 101100 [R s ] + [R t (If overflow then exception Assembly format: DADD R d 2. Doubleword Add Unsigned: DADDU As DADD instruction, except Funct=45 dec and overflow ignored Note: the term unsigned in the instruction name is a misnomer. 3. Doubleword Subtract: DSUB 00000 101110 [R s ] - [R t (Overflow exception possible Assembly format: DSUB R d 4. Doubleword Subtract Unsigned: DSUBU As DSUB instruction, except Funct=47 dec and overflow ignored Note: the term unsigned in the instruction name is a misnomer. 1

5. Doubleword Multiply: DMULT 00000 00000 011100 Effects: Hi Lo [R s ] * [R t Assembly format: DMULT R s 6. Doubleword Multiply Unsigned: DMULTU As DMULT instruction, except: - Funct = 29 dec - contents of R s and R t are considered as unsigned integers 7. Doubleword Divide: DDIV 00000 00000 011110 Effects: Lo [R s ] / [R t ]; Hi [R s ]mod[r t (Note: No exception on zero divide, and results is unpredicable Assembly format: DDIV R s 8. Doubleword Divide Unsigned: DDIVU As DDIV instruction, except: - Funct = 31 dec - contents of R s and R t are considered as unsigned integers 9. Set on Less Than: SLT 00000 101010 Effects: if [R s ] < [R t ] then R d 0 63 1 else R d 0 64 ; PC [PC] + 4 Assembly format: SLT R d 10. Set on Less Than Unsigned: SLTU As SLT instruction, except: - Funct = 43 dec - contents of R s and R t are considered as unsigned integers. 2

11. Logical And: AND 00000 100100 [R s ] AND [R t Assembly format: AND R d 12. Logical Or: OR As AND instruction, except: - Funct=37 dec - or function performed instead of logical and 13. Logical Not Or: NOR As AND instruction, except: - Funct=39 dec - nor function performed instead of logical and 14. Logical Exclusive Or: XOR As AND instruction, except: - Funct=38 dec - exclusive or function performed instead of logical and 15. Doubleword Add Immediate: DADDI I-type format: 011000 R s immediate Effects: R t [R s ] + ([I 15 ]; PC [PC] + 4 (Overflow exception possible Assembly format: DADDI R t,immediate 16. Doubleword Add Immediate Unsigned: DADDIU As DADDI instruction, except Op-code=25 dec and overflow ignored Note: the term unsigned in the instruction name is a misnomer. 3

17. Set on Less Than Immediate: SLTI I-type format: 001010 R s immediate Effects: if [R s ]<([I 15 ] 48 [I 15..0 ] then R t 0 63 1 else R t 0 64 PC [PC] + 4 Assembly format: SLTI R t,immediate 18. Set on Less Than Immediate Unsigned: SLTIU As SLTI instruction, except: - Op-code = 11 dec - contents in the comparison are considered as unsigned integers. 19. Logical And Immediate: ANDI I-type format: 001100 R s immediate Effects: R t [R s ] AND (0 48 [I 15..0 ]; PC [PC] + 4 Assembly format: ANDI R t,immediate 20. Logical Or Immediate: ORI As ANDI instruction, except: - Op-code=13 dec - or function performed instead of logical and 21. Exclusive Or Immediate: XORI As ANDI instruction, except: - Op-code=14 dec - exclusive or function performed instead of logical and 22. Doubleword Shift Left Logical: DSLL R-type format 000000 00000 SA 111000 [R t ] << SA; (0 s shifted in on right PC [PC]+4 Assembly format: DSLL R d,sa 4

23. Doubleword Shift Left Logical Variable: DSLLV 00000 010100 [R t ] << [R s ]; (0 s shifted in on right PC [PC]+4 Assembly format: DSLLV R d 24. Doubleword Shift Right Logical: DSRL R-type format 000000 00000 SA 111010 [R t ] >> SA ; (0 s shifted in on left PC [PC]+4 Assembly format: DSRL R d,sa 25. Doubleword Shift Right Logical Variable: DSRLV As DSLLV instruction, except Funct=22 dec, shift right & 0 s shifted in on left 26. Doubleword Shift Right Arithmetic: DSRA R-type format 000000 00000 SA 111011 [R t ]>>SA; (sign bit shifted in on left; PC [PC]+4 Assembly format: DSRA R d,sa 27. Doubleword Shift Right Arithmetic Variable: DSRAV As DSLLV instruction, except Funct=23 dec, shift right & sign bit shifted in on left 28. Load Doubleword: LD I-type format: 110111 R s Effects: R t M{[R s ]}; PC [PC] + 4 Assembly format: LD R t 5

29. Store Doubleword: SD I-type format: 111111 R s Effects: M{[R s ]} [R t Assembly format: SD R t 30. Load Byte Unsigned: LBU I-type format: 100100 R s Effects: R t 0 56 m{[r s ]}; PC [PC] + 4 Assembly format: LBU R t 31. Load Byte: LB As LBU instruction, except: - leftmost 56 bits of R t set to a value of leftmost bit of byte - Op-code =32 dec 32. Load Halfword Unsigned: LHU As LBU instruction, except: - 16 bits from memory loaded into R t plus 48-bit zero-extend - Op-code =37 dec 33. Load Halfword: LH As LB instruction, except: - 16 bits from memory loaded into R t plus 48-bit sign-extend - Op-code =33 dec 34. Load Word Unsigned: LWU As LBU instruction, except: - 32 bits from memory loaded into R t plus 32-bit zero-extend - Op-code =39 dec 35. Load Word: LW As LB instruction, except: - 32 bits from memory loaded into R t plus 32-bit sign-extend - Op-code =35 dec 6

36. Store Byte: SB I-type format: 101000 R s Effects: m{[r s ]} [R t ] 7..0 ; PC [PC] + 4 Assembly format: SB R t 37. Store Halfword: SH As SB instruction, except: - rightmost 16 bits from R t stored into memory - Op-code =41 dec 38. Store Word: SW As SB instruction, except: - rightmost 32 bits from R t stored into memory - Op-code =43 dec 39. Load Doubleword to Floating Point: L.D I-type format: 110101 R s F t Effects: F t M{[R s ]}; PC [PC] + 4 Assembly format: L.D F t 40. Store Doubleword from Floating Point: S.D I-type format: 111101 R s F t Effects: M{[R s ]} [F t Assembly format: S.D F t 41. Load Word to Floating Point: L.S I-type format: 110001 R s F t Effects: F t mm{[r s ]} 0 32 ; PC [PC] + 4 Assembly format: L.S F t 7

42. Store Word from Floating Point: S.S I-type format: 111101 R s F t Effects: mm{[r s ]} [F t ] (only 32 most significant bits taken PC [PC] + 4; Assembly format: S.S F t 43. Load Upper Immediate: LUI I-type format: 001111 00000 immediate Effects: R t [I 15 ] 32 [I 15-0 ] 0 16 ; PC [PC] + 4 Assembly format: LUI R t,immediate 44. Branch on Less Than or Equal to Zero: BLEZ I-type format: 000110 R s 00000 Effects: if [R s ] 0 then PC [PC] + 4 + ([I 15 ] 46 [I 15..0 ] 0 2 else PC [PC] + 4 If condition satisfied, the instruction that follows the branch instruction, in branch delay slot, is executed before branching. Assembly format: BLEZ R s,offset or BLEZ R s,label 45. Branch on Greater Than Zero: BGTZ As BLEZ instruction, except branch if [R s ]>0 and Op-code = 7 dec 46. Branch on Less Than Zero: BLTZ As BLEZ instruction, except branch if [R s ]<0 and Op-code = 1 dec 47. Branch on Greater Then or Equal to Zero: BGEZ As BLEZ instruction, except branch if [R s ] 0, Op-code=1 dec & R t =1 8

48. Branch on Equal: BEQ I-type format: 000100 R s Effects: if [R s ]==[R t ] then PC [PC]+4 +([I 15 ] 46 [I 15..0 ] 0 2 else PC [PC] + 4 If condition satisfied, the instruction that follows the branch instruction, in branch delay slot, is executed before branching. Assembly format: BEQ R s,offset or BEQ R s,label 49. Branch on Not Equal: BNE As BEQ instruction, except branch if [R s ]! [R t ] and Op-code = 5 dec 50. Jump: J +--------+-----------------------------------------+ J-type format 000010 jump_target +--------+-----------------------------------------+ Effects: PC [PC 63..28 ] [I 25..0 ] 0 2 The instruction that follows the jump instruction, in the branch delay slot, is executed before executing the jump itself. Assembly format: J jump_target or J label 51. Jump and Link: JAL +--------+-----------------------------------------+ J-type format 000011 jump_target +--------+-----------------------------------------+ Effects: R 31 [PC] + 8; PC <-- [PC 63..28 ] [I 25..0 ] 0 2 The instruction that follows the jump instruction, in the branch delay slot, is executed before executing the jump itself. Assembly format: JAL jump_target or JAL label 9

52. Jump Register: JR 00000 00000 00000 001000 Effects: PC [R s ] The instruction that follows the jump instruction, in the branch delay slot, is executed before executing the jump itself. Assembly format: JR R s 53. Jump and Link Register: JALR 00000 00000 001001 [PC] + 8; PC [R s ] The instruction that follows the jump instruction, in the branch delay slot, is executed before executing the jump itself. Assembly format: JALR R d 54. Move From HI Register: MFHI R-type format 000000 00000 00000 00000 010000 [Hi Assembly format: MFHI R d 55. Move From LO Register: MFLO R-type format 000000 00000 00000 00000 010010 [Lo Assembly format: MFLO R d 10

56. Move from Coprocessor 0 Register: MFC0 R-type format 010000 00000 C d 00000 000000 Effects: R t [C d ] (32-bit sign-extended; PC [PC] + 4; Assembly format: MFC0 R t,c d C 12 = Status Register; C 13 = Cause Register; C 14 = EPC Register; 57. Move to Coprocessor 0 Register: MTC0 R-type format 010000 00100 C d 00000 000000 Effects: C d [R t ] (32-rightmost bits taken; PC [PC] + 4; Assembly format: MTC0 C d 58. Floating Point Add Single Precision: ADD.S R-type format 010001 10000 F t F s 000000 Effects: F d <-- [F s ] + [F t ]; PC <-- [PC]+4 (FP overflow or underflow exception possible Assembly format: ADD.S F d,f t 59. Floating Point Add Double Precision: ADD.D R-type format 010001 10001 F t F s 000000 Effects: F d [F s ] + [F t (FP overflow or underflow exception possible Assembly format: ADD.D F d,f t 60. Floating Point Subtract Single Precision: SUB.S As ADD.S instruction, except subtract and funct = 1 61. Floating Point Subtract Double Precision: SUB.D As ADD.D instruction, except subtract and funct = 1 11

62. Floating Point Multiply Single Precision: MUL.S As ADD.S instruction, except multiply and funct = 2 63. Floating Point Multiply Double Precision: MUL.D As ADD.D instruction, except multiply and funct = 2 64. Floating Point Divide Single Precision: DIV.S As ADD.S instruction, except divide, funct = 3, and in addition zero division exception possible 65. Floating Point Divide Double Precision: DIV.D instruction As ADD.D instruction, except divide, funct = 3 and in addition zero division exception possible 66. Floating Point Move Single Precision: MOV.S R-type format 010001 00000 00000 F s 000110 Effects: F d [F s Assembly format: MOV.S F d 67. Floating Point Move Double Precision: MOV.D R-type format 010001 00001 00000 F s 000110 Effects: F d [F s Assembly format: MOV.D F d 68. System Call: SYSCALL R-type format 000000 code 001100 Effects: Syscal exception caused; the field code, ignored by hardware, is available for use as a software parameter and can be obtained only by loading the contents of the memory word containing the instruction. 12

69. Break Point: BREAK As SYSCALL instruction, except: - Break point exception caused - Funct = 13 dec 70. Exception Return: ERET R-type format 010000 10000 00000 00000 000000 011000 Effects: PC [EPC]; CPU mode is switched in user mode 71. Trap if Egual: TEQ code 110100 Effects: if [R s ]=[R t ] then Trap exception caused; the field code, ignored by hardware, is available for use as a software parameter and can be obtained only by loading the contents of the memory word containing the instruction. Assembly format: TEQ R s 72. Trap if Greater or Equal: TGE 73. Trap if Greater or Equal Unsigned: TGEU 74. Trap if Less Than: TLT 75. Trap if Less Than Unsigned: TLTU 76. Trap if Not Equal: TNE 77. Convert to Double Floating Point from Long Integer: CVT.D.L R-type format 010001 10101 00000 F s 100001 Effects: The value in F s, interpreted in 2 s complement format, is converted to a value in double floating point format and stored in F d ; PC [PC] + 4 Assembly format: CVT.D.L F d 13

78.Convert to Double Floating Point from Single Floating: CVT.D.S R-type format 010001 10001 00000 F s 100001 Effects: The value in F s, interpreted in single floating point format, is converted to a value in double floating point format and stored in F d ; PC [PC] + 4 Assembly format: CVT.D.S F d 79. Convert to Single Floating Point from Long Integer: CVT.S.L R-type format 010001 10101 00000 F s 100000 Effects: The value in F s, interpreted in 2 s complement format, is converted to a value in single floating point format and stored in F d ; PC [PC] + 4 Assembly format: CVT.S.L F d 80.Convert to Single Floating Point from Double Floating: CVT.S.D R-type format 010001 10001 00000 F s 100000 Effects: The value in F s, interpreted in single floating point format, is converted to a value in double floating point format and stored in F d ; PC [PC] + 4 (FP overflow or underflow exception possible Assembly format: CVT.S.D F d 81. Convert to Long Integer from Single Floating Point: CVT.L.S R-type format 010001 10000 00000 F s 100101 Effects: The value in F s, interpreted as in single floating point format, is converted to a value in 2 s complement format and stored in F d ; PC [PC] + 4 (Overflow exception possible Assembly format: CVT.L.S F d 82. Convert to Long Integer from Double Floating Point: CVT.L.D As CVT.L.S instruction, except double floating format converted and value in the second instruction field is 17 dec 14

83. Branch on Less Than or Equal to Zero Likely: BLEZL I-type format: 010110 R s 00000 Effects: if [R s ] 0 then PC [PC] + 4 + ([I 15 ] 46 [I 15..0 ] 0 2 else PC [PC] + 4 If condition satisfied, the instruction that follows the branch instruction, in branch delay slot, is executed before branching. If the branch is not taken, the instruction in the delay slot is not executed. Assembly format: BLEZL R s,offset or BLEZL R s,label 84. Branch on Greater Than Zero Likely: BGTZL As BLEZL instruction, except branch if [R s ]>0 and Op-code = 23 dec 85. Branch on Less Than Zero Likely: BLTZL As BLEZL instruction, except branch if [R s ]<0, Op-code=1 dec & R t =2 dec 86. Branch on Greater Then or Equal to Zero: BGEZL As BLEZL instruction, except branch if [R s ] 0, Op-code=1 dec & R t =3 dec 87. Branch on EqualLikely: BEQL I-type format: 010100 R s Effects: if [R s ]==[R t ] then PC [PC]+4 +([I 15 ] 46 [I 15..0 ] 0 2 else PC [PC] + 4 If condition satisfied, the instruction that follows the branch instruction, in branch delay slot, is executed before branching. If the branch is not taken, the instruction in the delay slot is not executed. Assembly format: BEQL R s,offset or BEQL R s,label 88. Branch on Not Equal Likely: BNEL As BEQL instruction, except branch if [R s ]! [R t ] and Op-code =21 dec 15