SERIAL PERIPHERAL INTERFACE (SPI) George E Hadley, Timothy Rogers, and David G Meyer 2018, Images Property of their Respective Owners
OUTLINE SPI Theory SPI Implementation STM32F0 SPI Resources System Overview Registers SPI Application Initialization Interface Examples
SPI THEORY Motivation USART can be used for asynchronous serial communication between two devices Question: Are there alternatives? Answer: Consider the concept of synchronous serial communication Synchronous serial communication is similar to asynchronous serial communication, except the devices share a common clock signal Advantages: Higher communication speeds (8-16x oversampling of signal not required, start/stop bits not required, packets can vary in length) Disadvantages: Hard to transmit data over long distances (signal integrity issues); SPI generally limited to board-level communication and short cable runs
SPI THEORY Masters and Slaves Serial Peripheral Interface (SPI) peripherals utilize the concept of master and slave devices to moderate communications Master: Initiates sending data or requests that data be sent (only one device may be master in traditional SPI protocols); also supplies the clocking signal Slave: Responds to those requests (can be multiple slave devices within system) Based on these roles, SPI peripherals commonly feature the following lines: Master Out/Slave In (MOSI): transmitting data (master) or receiving data (slave) Master In/Slave Out (MISO): receiving data (master) or transmitting data (slave) SPI System Clock (SCK): Shared clock for synchronous data transfer Slave Select (SSx): One or more (optional) control signals used for differentiating among multiple slave devices
SPI THEORY SPI Structure Single Slave SS SPI feature: Data is transferred simultaneously between master and slave devices
SPI THEORY SPI Structure Multiple Slaves Here, the slave select signals are provided by GPIO pins
SPI THEORY SPI Communications and Errors SPI Communication Structure: SPI Communication Errors: Overrun Error: Data is received by a master or slave device before previous received data has been read
STM32F0 SPI Resources Course microcontroller features two SPI peripherals: Default mode of operation is Motorola SPI Integrated I 2 S functionality (option for high quality stereo audio interface using an external CODEC) Master or slave operation 4-16 bit programmable frame size Multi-master mode capability Interrupt capability and DMA operation
STM32F0 SPI Subsystem Overview
Basic Configuration for Full Duplex Operation (Single Master, Single Slave) Here, the assertion or negation of the NSS pin indicates master or slave operating mode
Simplex Single Master/Single Slave Application Here, data is only transferred one direction: from the master to the salve (master is transmitonly, slave is receive-only)
Half-Duplex Single Master/Single Slave Application Here, the direction of (half-duplex) communication can be changed; master remains the clocking source
Multiple Independent Slaves Here, the NSS input of each slave is used to select (enable) it; the slave select outputs of the master are generated by GPIO pins
NSS Pin Logic If the SPI is configured for master mode and the NSS input is low (Vss), then an error is flagged
Clock Mode Phase/Polarity The combination of clock phase (CPHA) and clock polarity (CPOL) settings determine how the serial data stream is sampled The SPI clock divisor is 2 (1+BR[2:0])
COLLABORATIVE CLICKER QUIZ (CCQ) Question 1 1. The synchronous aspect of an SPI interface means: A. data can only be transmitted in one direction B. data can be transmitted in both directions, but not at the same time C. data can be transmitted in both directions simultaneously D. data transmission requires an accompanying clock signal E. none of the above
COLLABORATIVE CLICKER QUIZ (CCQ) Question 2 2. The minimum SPI clock divisor possible is: A. 1 B. 2 C. 4 D. 8 E. none of the above
COLLABORATIVE CLICKER QUIZ (CCQ) Question 3 3. Based on a 48 MHz system clock, the maximum SPI data transfer rate possible (in bits/second) is: A. 6,000,000 bps B. 8,000,000 bps C. 12,000,000 bps D. 24,000,000 bps E. none of the above
COLLABORATIVE CLICKER QUIZ (CCQ) Question 4 2. The maximum SPI clock divisor possible is: A. 128 B. 256 C. 512 D. 1024 E. none of the above
COLLABORATIVE CLICKER QUIZ (CCQ) Question 5 3. Based on a 48 MHz system clock, the minimum SPI data transfer rate possible (in bits/second) is: A. 46,875 bps B. 93,750 bps C. 187,500 bps D. 375,000 bps E. none of the above
Clock Mode Phase/Polarity Clock format for CPHA = 0 and CPOL = 0 ( sample data on odd-numbered positive clock edges )
Clock Mode Phase/Polarity These are all the permutations possible with clock phase and polarity control note that the bit order can be programmed as well (i.e., MSB first or LSB first) The reason all these different modes are provided is due to the wide variety of SPI compatible devices on the market
Data Alignment Data alignment when data length is not equal to 8-bit or 16-bit the minimum data length is 4 bits
Data Packing Illustration of data packing in FIFO for transmission and reception
STM32F0 SPI Registers SPI Control Register 1 (SPIx_CR1): Control and configuration information for the SPI peripheral Significant Fields: Frame Format (LSBFirst): Indicates endianness of SPI SPI Enable (SPE): Enables/disables SPI peripheral Baud Rate Control (BR[2:0]): SPI clock divisor Master Selection (MSTR): Specifies master or slave mode
STM32F0 SPI Registers SPI Control Register 2 (SPIx_CR2): More control and configuration information for the SPI peripheral Significant Fields: Data Size (DS[3:0]): Sets SPI frame size (4-16 bits) TX Interrupt Enable (TXEIE): Enable for TX interrupt RX Interrupt Enable (RXNEIE): Enable for RX interrupt SS Output Enable: Used to enable/disable SPI operation in a multi-master environment
STM32F0 SPI Registers SPI Status Register (SPIx_SR): More control and configuration information for the SPI peripheral Significant Fields: Busy Flag (BSY): Indicates if SPI peripheral is in use Overrun Flag (OVR): Indicates FIFO overrun Underrun Flag (UDR): Indicates FIFO underrun TX Buffer Empty (TXE): Indicates transmitter is free RX Buffer Not Empty (RXNE): Indicates data is available
STM32F0 SPI Registers Other SPI Registers: SPI Data Register (SPIx_DR): Contains data to be received or transmitted (RX data and TX data contained in separate FIFOs, both accessed through this register) SPI CRC Registers (SPIx_CRCPR, SPIx_RXCRCR, SPIx_TXCRCR): Registers used for cyclic redundancy checking (CRC), a more advanced form of error checking compared to USART parity checking
SPI APPLICATION Basic Initialization The master or slave configuration steps are nearly identical outlined here are the basic steps for standard communication
SPI APPLICATION Constant Current LED Driver Use of constant current LED drivers eliminates the need for current limiting resistors many of the ICs designed for this purpose utilize an SPI compatible (simplex) interface The output enable (OE ) input can be driven by a PWM output to control LED intensity The latch enable (LE) input is used to control when the display is updated (asserted after new data is shifted in)
Questions?