Hardware in the Loop Functional Verification Methodology

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Transcription:

OMG's Third Software-Based Communications Workshop: Realizing the Vision Hardware in the Loop Functional Verification Methodology by Pascal Giard Jean-François Boland, Jean Belzile M.Ing. Student École de technologie supérieure

Motivation: Overview Heterogeneous designs Multiple languages, tools and abstraction levels Incremental design Multiple refinements toward the target Chip TestBuilder/ Vera/e SystemC/SystemVerilog VHDL/Verilog C/C++ Matlab/UML HW RTL Verif. System Design System Modeling Domains Requires co-simulation OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 2

Motivation: Software Defined Radio Complex heterogeneous design Segmented implementation process Software Communication Architecture (SCA) Hardware Design Flow System Specifications Algorithm Design & Analysis System Design & Modeling HW Specs Preliminary Modeling HW/SW Partitioning HW/SW co verification IP Reuse SW Specs Software Design Flow TARGET Validation or Functional Verification OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 3

Goals: Part 1 Reduce time spent on verification Code reuse Early hardware verification Open standards Support multiple Modeling languages Levels of abstraction OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 4

Goals: Part 2 Support co-simulation Different languages Different abstraction levels Different physical locations Flexible and expendable framework: Allow extensions for other 3 rd party tools Allow external contributions 3 rd party comp. 3 rd party comp. PC Sim. Inhouse Comp. HW 3 rd party comp. 3 rd party comp. Inhouse Comp. OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 5

Outline Problems Proposed Methodology Proposed Framework Open issues Conclusions and Future Work OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 6

Problems: Part 1 Core of verification: Communication Verification methodologies: PC simulation In-Circuit Emulation (ICE) OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 7

Problems: Part 2 COTS tools: Expensive Hard to customize Close standards Incompatible Inflexible COTS A Proto 1 COTS B HW Proto 2 OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 8

Outline Problems Proposed Methodology Proposed Framework Open issues Conclusions and Future Work OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 9

Proposed Methodology: Part 1 Reduce simulation time with distributed processing Use traditional verification flow Top-down approach From specifications to final implementation Multiple refinements toward target OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 10

Proposed Methodology: Part 2 Use distributed object architecture for: Verification/simulation communication Internal DUV communication Golden Reference Data Analysis Data Generator DUV SystemC DUV HDL DUV... VHDL DUV Verilog DUV Algorithmic level tool Multi Abstraction Level Modeling Language... Communication interface HW prototype OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 11

Outline Problems Proposed Methodology Proposed Framework Open issues Conclusions and Future Work OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 12

Proposed Framework: Overview An ORB for everyone FPGA for Hardware In the Loop (HIL) verification 2 phases: Initial version First expansion OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 13

Proposed Framework: Models Tool 1 Component 1 Component 2 Comp. A ORB wrapper Comp. B ORB wrapper ORB 1...... Comp. X ORB wrapper Application environment Tool 2 ORB Comp. 3 ORB wrapper Tool A ORB 2 ORB wrapper Tool B...... ORB wrapper Tool X Tools environment OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 14

Proposed Framework: First phase Design spreads across two locations Communication via ORB FPGA hardware Multiple languages and abstraction levels OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 15

Proposed Framework: 2 nd phase Deploy on multiple nodes Broader tool base Cluster Cluster SystemC Matlab FPGA Adapter ORB Transport Adapter ORB Transport... Adapter ORB Transport GIOP OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 16...

Outline Problems Proposed Methodology Proposed Framework Open issues Conclusions and Future Work OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 17

Open issues: Part 1 Large deployment E.g. Using a Cluster for HDL simulation OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 18

Open issues: Part 2 Communication performance Latency Throughput Fragmentation Etc. OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 19

Outline Problems Proposed Methodology Proposed Framework Open issues Conclusions and Future Work OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 20

Conclusion: Part 1 Distributed object architecture verification Hardware In the Loop Cluster farms Etc. Promotes open standards Promotes code reuse Promotes early hardware verification OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 21

Conclusion: Part 2 Seamless integration of multiple: levels of abstraction design languages physical location Allows progressive refinements towards target platform Provides an expendable framework Supports traditional verif. flow OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 22

Future Work Short term: Complete implementation Other application areas Mid term: Performance evaluation Support more 3 rd party tools Long term: Integration with the GreenSocs project OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 23

Questions? Thank you for listening! Contact me at Pascal.Giard.1@ens.etsmtl.ca

Hidden slides

Related works VirginiaTech s CARH Service-Oriented Architecture for Validating System-Level designs Integrates CORBA to OSCI SystemC Requires modifications to OSCI SystemC compiler Not meant for hardware component interoperability different scope OMG: SBC Workshop 2007 Pascal Giard, École de technologie supérieure 26

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