Chapter 9 Basics of SOC Testing Jin-Fu Li Advanced Reliable Systems (ARES) Lab Department of Electrical Engineering National Central University Jhongli, Taiwan
Outline Introduction SOC Test Challenge SOC Test Access Mechanisms SOC Test Control Architectures t Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2
What is an SOC? Definition Integration of multiple cores (e.g., microprocessor, digital signal processor, RAM, ROM, flash memory, I/Os, and analog components which make a complete system) onto a single chip ADC FPGA Flash Memory CPU UDL DSP MPEG SRAM SRAM DRAM Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3
What are Cores? Definition Predefined, pre-verified complex functional blocks, also known as IPs, virtual components Examples Processor Cores: ARM, MIPS, IBM PowerPC PC Peripherals: MMU, DMA Controller Interface: PCI, USB, UART Multimedia: JPEG compression, MPEG decoder Networking: Ethernet Controller, MAC Various core description levels Soft cores: register-transfer level (synthesizable HDL) Firm cores: gate-level netlist (Verilog netlist) Hard cores: layout (GDS2) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4
Traditional & Core-Based IC Design Traditional IC design IC is designed from scratch Reuse of small modules: standard-cell library and memory modules Core-based IC design Reuse of large modules: cores, IP, virtual components Divide-and-conquer design methodology Definition of standards to make reuse easy Reduce time-to-market Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5
Difference Between SOB and SOC System-on-Board (SOB) IC Design IC Verification System-on-Chip (SOC) Core Design Core Verification IC Manufacturing IC Test Analogy Reuse of predeisgned components in a system SOB Design SOB Verification SOB Manufacturing SOB Test SOC Design SOC Verification SOC Manufacturing SOC Test Difference Cores in SOC are fabricated and tested in the final system [Zorian, et al.-itc97] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6
What are The Test Challenges? Distributed design and test development Mixed technologies: logic, processor, memory, analog Need various ATPG/DFT/BIST/other techniques Multiple hardware description levels for cores Need test plan for the various levels Different core providers and SOC test t developers Need standard for test integration Deeply embedded cores Need electronic test access mechanism Core/test reuse Need plug-and-play l test t mechanism Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7
What are The Test Challenges? Hierarchical core reuse Need hierarchical test management SOC-level test optimization Test time can be extremely large Need parallel testing or test scheduling Test power must be considered Need low-power design or test t scheduling Testable design automation Need new testable design tools and flow Test economic consideration Need to determine e test strategy and overall test plan SOC yield improvement Large amount of defect-sensitive memory cores Need cost-effective repair techinques Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8
Generic Test Access Structure ADC FPGA Wrapper Flash Memory Source CPU UDL Test Access Mechanism (TAM) DSP TAM Sink MPEG SRAM SRAM DRAM [Y. Zorian, et al.-itc98] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9
1500 Test Scalable Structure Source User Defined Parallel TAM Sink TAM-in TAM-out TAM-in TAM-out 1500 Wrapper 1500 Wrapper Fin Core1 Fout Fin CoreN Fout WSI WIR WSO WSC WSI WIR WSO User-Defined Test Controller Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10
1500 Parallel TAM Configuration WPC Daisychained TAM WPI WPO ENA WPP ENA WPP ENA WPP Core Core Core WSI Wrapper WSP Wrapper WSP Wrapper WSP WSO WSC Standardized Plug & Play Wrapper Serial Ports Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11
1500 Parallel TAM Configuration WPC Bussed TAM WPI WPO ENA WPP ENA WPP ENA WPP Core Core Core WSI Wrapper WSP Wrapper WSP Wrapper WSP WSO WSC Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12
1500 Parallel TAM Configuration WPC WPI WPO WPC WPI Direct Access TAM WPO WPO WPC WPI ENA WPP ENA WPP ENA WPP Core Core Core WSI Wrapper WSP Wrapper WSP Wrapper WSP WSO WSC Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13
TAM Implementations Many TAM implementation have been reported Examples: Multiplexed access Reused system bus (AMBA) Transparency Boundary Scan Scalable TAMs (Test bus, TestRail) On one SOC, different TAMs may co-exist Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14
Multiplexed Access [E. J. Marinissen, ITC98] (a): Multiplexing architecture; (b) daisy-chain architecture; (c) Distributed architecture Core A N Core A na Core A N Core B Core B Core B nb Core C Core C nc Core C IC IC IC (a) (b) (c) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15
Test Shell/TestRail [E. J. Marinissen, ITC98] Every core is wrapped with a TestShell The TestShell is the test data transport mechanism TCM is a standardized test control mechanism in the TestShell The host is the environment in which the core is embedded TCM host TestShell TCM TestShell TCM TestRail IP A IP B Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16
Test Shell/TestRail [E. J. Marinissen, ITC98] host Shell TCM TCM TestRail 1 16 16 Core A 16 Shell TCM Shell TCM 16 16 Core B Core C 16 16 Shell TCM Shell TCM 2 Core E Shell TCM TestRail 2 10 Core D 8 Core F 10 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17
SOC Test Control Architectures TAP Linking Module (TLM) architecture I C B S R NTC CBSR CBSR CBSR NTC NTC TAP1 TAP ed Core TAP ed Core TAP ed Core X Y Z TAP2 TAP3 TAP4 SEL ENA SEL ENA SEL ENA SEL ENA TAP Linking Module (TLM) I C B S R TDI TCK TMS TRST* TDO [Lee Whetsel, ITC97] The TLM operates to enable and connect one or more TAPs to be accessed via the IC s test pins Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18
SOC Test Control Architectures TLM architecture [Lee Whetsel, ITC97] TAP TLM: SEL TAP1 LC2 TAP2 LC3 TAP3 LC4 TAP4 Enable 1,2,3,4 TLM TAP: LC ENA SEL1 SEL2 SEL3 SEL4 TAP Linking Module (TLM) TDO4 TDO3 TDO2 TDO1 ENA1 ENA2 ENA3 ENA4 Reset* TDO TAPSEL0,1 TLM-Select M U X 3 S M U X Enable TDI TCK TMS TRST* TDO The TLM communicates with TAPs via select (SEL), enable (ENA) and Link Control (LC). After power up, or test reset, the TLM defaults to connecting TAP1 to the test pins Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19
SOC Test Control Architectures Modified state diagram TMS=1 Test Logic Reset ENA:TMS=1:0 Or TMS=0 ENA:TMS=0:x Run Test/ ENA:TMS=1:1 Idle Unlinked Stroble State ENA=0,TAP disable ENA=1,TAP enable ENA:TMS=1:1 Data Register Scan ENA:TMS=1:0 Or ENA:TMS=0:x Select DRS Capture DR Shift DR Update DR Instruction Register Scan TMS=1 Select IRS Link change state TMS=1 Capture IR Shift IR Update IR TMS=0 TMS=1 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20
Hierarchical Test Methodology [J.-F. Li, et al., IEEE Micro 02] TDI_UP TMS_UP TRST_UP TCK_UP TDO_UP HTM1 TDI_C ECS TDI_H TCS_DN TDO_H TDO_C WCI Core 1 (P1500) WCI MBI Core 2 (BISTed RAM) WCI Core 3 (P1500) HTM2 TAM 2 WCI Core 4 (P1500) TAP Core 5 (JTAG) TAM 1 TAM input TAM output Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21
Hierarchical Test Procedure [J.-F. Li, et al., IEEE Micro 02] Test Configuration Load the instructions for the wrappers and memory BIST interfaces (MBIs) TAM Specification Specify the cores to be tested by the TAM Test Transportation Import the test patterns and export the test responses Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22
An Example TDI_UP TMS_UP TRST_UP TCK_UP TDO_UP HTM1 TDI_C ECS TDI_H TCS_DN TDO_H TDO_C WCI Core 1 (1500) WCI MBI Core 2 (BISTed RAM) WCI Core 3 (1500) HTM2 TAM 2 WCI Core 4 (1500) TAP Core 5 (JTAG) TAM 1 TAM input TAM output Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23
Hierarchical Test Manager Test Manager Boundary Register Selection Register Bypass Register Instruction Decoder Instruction Register FSM WCS Encoder ECS0 ECS1 ECS2 TMS TCK TRST TDI TMS TCK TRST TDI TMS_N TCK_N TRST_N TDI_UP TDO_UP Hierarchical Test Interface Switch Box TDI_C TDI_H TDO_C TDO_H Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24