Chapter 8 Test Standards. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
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1 Chapter 8 Test Standards Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
2 Outline standard for system-on-board 1500 standard for system-on-chip Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2
3 Overview System-on-Board System-on-Chip System-on-Chip Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3
4 (JTAG) Standard Purpose of the standard Let test instructions and test data be serially fed into a component-under-test (CUT) JTAG can operate at chip, PCB, & system levels Let system interconnect be tested separately from components Let components be tested separately from wires Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4
5 System Test Logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5
6 Instruction Register Loading Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6
7 System View of Interconnect Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7
8 Boundary Scan Chain View Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8
9 Elementary Boundary Scan Cell Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9
10 Serial Board/MCM Scan Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10
11 Parallel Board/MCM Scan Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11
12 Independent Board/MCM Scan Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12
13 Signals of the TAP Controller Test Access Port (TAP) includes these signals: Test Clock Input (TCK) -- Clock for test logic Can run at different rate from system clock Test Mode Select (TMS) -- Switches system from functional to test mode Test Data Input (TDI) -- Accepts serial test data and instructions -- used to shift in vectors or one of many test instructions Test Data Output (TDO) -- Serially shifts out test results captured in boundary scan chain (or device ID or other internal registers) Test Reset (TRST) -- Optional asynchronous TAP controller reset Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13
14 State Diagram of the TAP Controller Load Instruction Test Application Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14
15 Mandatory Instruction Bypass Purpose: bypasses scan chain with 1-bit register Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15
16 Mandatory Instruction Sample/Preload Purpose: Get snapshot of normal chip output signals (Sample) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16
17 Mandatory Instruction Sample/Preload Purpose: Put data on boundary scan chain before next instruction (Preload) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17
18 Mandatory Instruction Extest Purpose : Test off-chip circuits and board-level interconnections Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18
19 Mandatory Instruction Intest Purpose : Shifts external test patterns onto component External tester shifts component responses out Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19
20 System On Chip Advances in IC design methods and manufacturing technologies allow to integrate complete systems onto a single IC, called system on chip (SOC) Compared with traditional multi-chip equivalents, SOC offers advantages such as Higher performance, lower power consumption, and smaller volume and weight Many SOCs are designed by embedding large reusable building blocks, called cores Design reuse speeds up the design and allows import of external expertise Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20
21 Test Reuse Design reuse becomes an indispensable condition to the design productivity optimization The same is valid for efficient test of nonmergeable cores, because this would require test reuse The test of these cores can become a challenge, with various types of difficulties including automation and test plug-and-play A core-level solution to facilitate test integration and test reuse is required Standardization Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21
22 1500 Test Wrapper Test stimuli Functional data WPI WBR Core WBR WPO Test response Functional data WBY WSI WIR WSO WSC Source: Y. Zorian, et al.-jetta2002 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22
23 1500 Wrapper Component Wrapper Instruction Register (WIR) Controls operation of Wrapper Controlled directly from WIP signals Instruction loaded via WSI-WSO Wrapper Bypass Register (WBY) Mandatory bypass for serial TAM (between WSI-WSO) Wrapper Boundary Register (WBR) Controllability/obervability on core terminals Test data loaded from WSI-WSO or WPI-WPO Built from library of wrapper cells Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23
24 Wrapper Interface Ports [Y. Zorian, et al.,itc03] User Defined Port for Test Flexibility Wrapper Parallel Input WPI Wrapper Parallel Control WPC Optional Wrapper Parallel Port (WPP) Wrapper Parallel Output WPO Core WSI Wrapper Serial Input Required Wrapper Serial Port (WSP) Wrapper WSC Wrapper Serial Control WSO Wrapper Serial Output Standardized Port for Plug & Play Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24
25 Wrapper Interface Ports Functional I/Os Core s functional inputs/outputs Wrapper Serial Control (WSC) A 7-bit control port for WIR and Wrapper Wrapper Serial Port (WSP) Mandatory serial interface is used for two purposes Wrapper control: loading instructions into the WIR Low-bandwidth test data access to WBR Wrapper Parallel Control (WPC) User defined port for test flexibility Wrapper Parallel Port (WPP) Optional parallel interface is used for test data access to WBR with user-defined, scalable bandwidth Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25
26 Wrapper Operation Modes Core Normal Mode Core Test Mode (Internal test) Core Interconnection Test Mode (External test) Core Isolation Mode Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26
27 Wrapper Serial Control (WSC) WSC functions: Control the operation of the WIR Control together with the WIR instruction the operation of the wrapper WSC Controls & Clock WRST WCLK SelectWR Capture Shift Update Transfer Core Wrapper Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27
28 WSC Signals WCLK WRST SelectWR Shift Capture Update Transfer Wrapper clock, dedicated P1500 clock signal for WIR, WBY, and WBR Wrapper reset, dedicated P1500 reset signal for WIR Select WIR as register between WSI-WSO Enable shift operation for selected register Enable capture operation for selected register Enable update operation for selected register Enable transfer operation for selected register Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28
29 Serial Interface Layer (SIL) SIL architecture WDRs WBR CDR 1-N Gn Core Data Registers G1 Bypass WSO WSI WIR SelectWIR WSC Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29
30 An Example of Wrapper Cell Shift Normal cfi cti wclk shift SE cfo cto Mode: Normal mode: normal=1 Shift mode : shift=1 Controllability: normal=>value in SE is driven onto CFO Observability: shift=>value at CFO is captured into SE Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30
31 Wrapper Instruction Set [Y. Zorian, et al.,jetta02] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31
32 Wrapper in Normal Mode [Y. Zorian, et al.,jetta02] WPI[2:0] d[0] d[1] d[2] m3 m2 m5 m6 d[0] d[1] d[2] Scan chain 0 Scan chain 1 Core q[0] q[1] m6 m7 m9 m10 WPO[2:0] q[0] q[1] d[3] d[4] m1 d[3] d[4] sc clk q[2] m8 q[2] WBY WSI WIR Wrapper SelectWIR m12 m11 WIP Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32 WSO
33 Wrapper in Bypass Mode [Y. Zorian, et al.,jetta02] WPI[2:0] d[0] d[1] d[2] m3 m2 m5 m6 d[0] d[1] d[2] Scan chain 0 Scan chain 1 Core q[0] q[1] m6 m7 m9 m10 WPO[2:0] q[0] q[1] d[3] d[4] m1 d[3] d[4] sc clk q[2] m8 q[2] WBY WSI WIR Wrapper SelectWIR m12 m11 WIP Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33 WSO
34 Wrapper in WCoreTestS [Y. Zorian, et al.,jetta02] WPI[2:0] d[0] d[1] d[2] m3 m2 m5 m6 d[0] d[1] d[2] Scan chain 0 Scan chain 1 Core q[0] q[1] m6 m7 m9 m10 WPO[2:0] q[0] q[1] d[3] d[4] m1 d[3] d[4] sc clk q[2] m8 q[2] WBY WSI WIR Wrapper SelectWIR m12 m11 WIP Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34 WSO
35 Wrapper in WExTestS [Y. Zorian, et al.,jetta02] WPI[2:0] d[0] d[1] d[2] m3 m2 m5 m6 d[0] d[1] d[2] Scan chain 0 Scan chain 1 Core q[0] q[1] m6 m7 m9 m10 WPO[2:0] q[0] q[1] d[3] d[4] m1 d[3] d[4] sc clk q[2] m8 q[2] WBY WSI WIR Wrapper SelectWIR m12 m11 WIP Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35 WSO
36 Wrapper in WCoreTest [Y. Zorian, et al.,jetta02] WPI[2:0] d[0] d[1] d[2] m3 m2 m5 m6 d[0] d[1] d[2] Scan chain 0 Scan chain 1 Core q[0] q[1] m6 m7 m9 m10 WPO[2:0] q[0] q[1] d[3] d[4] m1 d[3] d[4] sc clk q[2] m8 q[2] WBY WSI WIR Wrapper SelectWIR m12 m11 WIP Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 36 WSO
37 Wrapper in WExTestP [Y. Zorian, et al.,jetta02] WPI[2:0] d[0] d[1] d[2] m3 m2 m5 m6 d[0] d[1] d[2] Scan chain 0 Scan chain 1 Core q[0] q[1] m6 m7 m9 m10 WPO[2:0] q[0] q[1] d[3] d[4] m1 d[3] d[4] sc clk q[2] m8 q[2] WBY WSI WIR Wrapper SelectWIR m12 m11 WIP Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37 WSO
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