Silicon Photonics for Next Generation System Integration Platform

NEW PARADIGMS IN OPTICAL COMMUNICATIONS AND NETWORKS Silicon Photonics for Next Generation System Integration Platform Yasuhiko Arakawa, The University of Tokyo Takahiro Nakamura, Yutaka Urino and Tomoyuki Fujita, PETRA ABSTRACT New semiconductor technologies such as many-core processors and 3D memories are being researched in order to overcome the limitations of electronics in the near future. Here, we first discuss some drawbacks of current technologies, and then show that silicon photonics will solve those interconnection problems. Next, we describe our studies toward realizing a system integration platform based on photonics and electronics convergence, and show that an optical interposer is the most efficient way to cope with the various problems that a purely electronic system may encounter. Our recent advances in silicon photonic devices are also described, and their integration into the hybrid interposer is reported through an early prototyping result. Finally, a surface mounted components approach for silicon photonics technology is discussed, which may prove useful in the computer and communication markets. NEW TRENDS IN SYSTEM COMPONENTS Recently, the technique of system in package (SiP), in which a number of integrated circuit chips are enclosed in a single package, has been used for reducing size and supporting multiple functions. This has brought a number of benefits such as the shortening of development periods and the reduction of development costs compared to the technique of system on chip (SOC). Furthermore, using SiP, the integration of CPUs with various types of memory can easily be realized in one package, whereas with SOC technologies it is difficult to integrate CPUs with flash memory or DRAM. Similar to SiP, it is expected that on-chip server technology will become a reality around 2020. Each component in the on-chip server will become progressively miniaturized and offer higher performance than present ones. The current trend in electronic system components is a downsizing of their footprint by utilizing threedimensional (3D) packages []. For example, 3D technology by through silicon via (TSV) has been successfully introduced for memories. In processor technology, multicore technology has been introduced, and both many-core and 3D manycore technology will be introduced in the near future. In storage technology, solid state drives (SSDs) are emerging as a key storage device instead of hard disc drives (HDDs). SSDs will be further enhanced in the future as 3D-SSDs. Our ultimate goal is to realize the on-chip server (a miniaturized sever-board in a single chip) in the near future. The required throughputs per distance of various interconnects are shown in Fig.. In the figure, the current chip-to-chip interconnections are shown as solid line boxes; most of these interconnections are performed electronically. However, after the implementation of the various expected technological advances (challenges for semiconductors), the interconnections require much faster speeds (as shown in the dashed line box). These high-speed connections are required to realize an on-chip server. In the following section we provide a more detailed discussion on each type of interconnection. In processor technology, core-to-core communication will be enhanced from multicore to many-core communications (more than 6 cores). Since each core operates at speeds of several tens of gigabits per second, an intra-chip interconnect will have to be able to handle speeds of several hundred gigabits per second, or terabits per second in total (proportional to the number of cores). The photonic interconnection will achieve such ultra-high speeds because its signal propagation mechanism is completely different from the electrical one and will not cause any signal interference (crosstalk) or power consumption problems [2]. For memory technology, memories will be stacked in a 3D manner (3D-MEM). While Gb/s per each signal line is considered to be the upper bound for an electrical interconnect, a much faster interconnect technology (proportional to the number of memory stacks in 3D- MEM) will be required for the advanced system. While each memory device may not achieve the 72 063-6804/3/$25.00 203 IEEE IEEE Communications Magazine March 203

top speed, an advanced pipelining mechanism based on photonic interconnection will achieve the expected performance for consecutive memory access of large-volume data. For storage technology, the change from HDD to SSD will allow for the integration of much smaller memory components, and further facilitate substantially higher performance and much lower power consumption. Terabytes of storage will be mounted on a chip as a 3D-SSD in the near future. For off-chip peripheral components, PCI- Express for data communication and Display Port for raw data communication are the key s to the system. Both will require much faster interconnects to cope with, for example, increased image resolution provided by Super HiVision class monitors and cameras. Peripheral s are similar to the memory s, but operate at much longer connection distances. If the various peripheral components can connect via the same optical, the number of cables will be reduced to a minimum. Finally, for server-to-server communication, EXA-scale computing, where thousands of processors communicate with each other in a very quick manner, will require terabit-per-second class interconnections. From the above discussions, it is clear that such 3D technologies will demand interconnecting throughputs almost proportional to the number of stacks. Indeed, the throughput of interconnects will increase rapidly to speeds that are several tens/hundreds of times as high as the ones that are presently used. The high throughputs of these interconnects will further demand an increase in pin density and data transfer rate. This will be very difficult to realize with electrical connections, due to limitations imposed on speed, density, and power. Therefore, in order to overcome the limits of electronics, the interconnects for future on-chip servers will be achieved in an optical manner. Silicon photonics has recently become a subject of intense interest because it offers various interconnect solutions for low cost, low power consumption, high bandwidth, and high density. Although there have been many optical link demonstrations [3 6], there are no high-density systems integrated with light sources on a single silicon chip without our activities [7]. PHOTONICS-ELECTRONICS CONVERGENCE SYSTEM FOR INTERCHIP INTERCONNECTS In order to develop the interconnects for future on-chip servers, in Japan, Photonics and Electronics Convergence System Technology (PECST) project was started in March 20, as one of the 30 Funding Program for World Leading Innovative R&D on Science and Technology (FIRST) projects supported by the Council for Science and Technology Policy in the Cabinet Office. This project is being carried out for four years, and involves the University of Tokyo, Bandwidth (Gb/s) 0. Optical interconnection 2 High-speed peripheral Peripheral Electrical interconnection 3D-Mem Memory 2 3 /Distance (m ) CPU-CPU (ManyCore) Inter-Chip (high-speed) CPU-CPU (MultiCore) Inter-Chip connection Figure. Trends of chip-to-chip throughput as a function of interconnection distance in current (solid boxes) and future (dashed boxes). PETRA, and Advanced Industrial Science and Technology (AIST). PECST aims to establish a chip-to-chip interconnect technology with a bandwidth density of Tb/s/cm 2. In addition, innovative photonic devices based on nanotechnology, such as quantum dot lasers on silicon, are explored. Figure 2 shows our proposed on-chip server that may be realized in the 2020s. A many-core CPU, 3D-memory, and 3D-SSD are integrated on a silicon optical interposer supporting terabitper-second-class optical interconnects among the components. In this section, we describe the fabrication of the photonics-electronics convergence system for realizing the on-chip servers. There are three main points to be considered in order to optimally exploit the between electronics and photonics: The physical structure for combining photonics and electronics circuits The laser source arrangement The method of mounting the large-scale integrations (s) on the interposer Basically, these three issues will dominate the operating speed, size, temperature dependence, and crosstalk of the device. The cross-section of a silicon optical interposer is shown in Fig. 2. The silicon optical interposer is formed as follows. Optical splitters, optical modulators, and PDs are monolithically integrated on a silicon substrate, arrayed laser diodes (LDs) are integrated on the substrate as a hybrid structure, and these optical components are optically linked to each other via silicon optical waveguides. A many-core CPU, 3D-MEM, and 3D-SSD are mounted on the optical interposer by flip-chip bonding, and are electrically connected to the optical modulators and PDs. As shown in Fig. 2, the on-chip server is mounted on a printed circuit board (PCB) for electrical connection. High-speed optical signals for inter-server interconnects are directly transmitted to or received from the optical fibers. Low-speed electric interconnects to the PCB and electric power supply are performed through TSVs. It is clear that such 3D technologies will demand interconnecting throughputs almost proportional to the number of stacks. Indeed, the throughput of interconnects will increase rapidly to speeds that are several tens/hundreds of times as high as the ones that are presently used. IEEE Communications Magazine March 203 73

Three types of layered sandwich structure are feasible for the implementation of integrating photonic and electronic circuits: front-end integration, back-end integration, and flipchip bonding. The first two are monolithic integrations, and the third is a hybrid integration. Cache Many-core CPU 3D-MEM 2 inch 3D-SSD On-chip server @ 2022 Arrayed LD Silicon optical interposer Si optical modulator 3D-MEM Ge photodetector Processor interconnection multi-core many-core Memory interconnection flat-mem 3D-mem Storage interconnection HDD 3D-SSD Many-core CPU Si waveguide Cross-sectional view TSV PCB Semiconductor challenges BGA 9 inch Peripheral interconnection HDMI super HiVision Server board @ 202 Server interconnection EXA-scale computing Figure 2. On-chip server. INTEGRATION STRUCTURE Three types of layered sandwich structure are feasible for the implementation of integrating photonic and electronic circuits: front-end integration, back-end integration, and flip-chip bonding. The first two are monolithic integrations, and the third is a hybrid integration. The hybrid integration allows us to choose the most suitable technology nodes separately for both photonics and electronics circuits, which enables us to design, fabricate, and test them separately before combining them. On the other hand, monolithic integration, especially front-end integration, is expected to provide higher speeds and a lower assembly cost than hybrid integration, but requires very strict complementary metal oxide semiconductor (CMOS) compatibilities in terms of design, fabrication, and testing. In our project, hybrid integration is applied to a SiP substrate, and monolithic integration is applied to electrical-to-optical (E/O) or optical-toelectrical (O/E) conversion for an ultra-high-speed to special devices such as the 3D-MEM. LIGHT SOURCE INTEGRATION In order to minimize the total length (and hence losses) of waveguide lines on the interposer, the on-chip sources can be located near the modulators, where all the modulators must be connected to one of the light sources. In our case, butt-coupled lasers are integrated on silicon substrate of silicon-on-insulator (SOI) with a passive alignment technique [8] to provide enough optical output power for power splitting and facilitate heat dissipation for hightemperature operation. MOUNTING S ON AN INTERPOSER The mount stage on the surface of the interposer is designed as shown in Fig. 3 [7]. Bare chips are mounted on the interposer and are electrically connected to the optical modulators and photo detectors (PDs) by flip-chip bonding. That is, electric circuits (the bare chips) and photonic circuits (the optical interposer) are integrated as a hybrid structure. The inter-chip interconnects/silicon optical interposers operate as follows. Arrayed LDs are driven simultaneously by DC current, and the continuous waveform (CW) light from each LD is divided by an optical splitter and launched into an optical modulator. The optical modulators are directly driven by transmitter circuits in one. The modulated optical signals propagate along inter-chip optical waveguides and are detected by PDs under other s. The electrical signals from those PDs input to receiver circuits in the above the PDs. This system enables us to replace the conventional electronic wires on a printed circuit board (PCB) with the optical interconnects on a silicon substrate, which are th of the size (i.e., from a 30 30 cm 2 board to a 3 3 cm 2 chip). This silicon optical interposer has wide bandwidth capabilities due to the properties of the optical signals. Since the silicon substrates can be fabricated using a CMOS-compatible process, they have quite high density and are low in cost to manufacture. Furthermore, because this system is optically complete and closed without any optical inputs or outputs, users do not have to worry about any optical issues, such as optical coupling, reflection, or polarization dependence. 74 IEEE Communications Magazine March 203

FABRICATION OF SILICON OPTICAL INTERPOSERS The silicon optical interposers were fabricated from SOI wafers by CMOS process technology. The silicon optical waveguides were formed by electron beam lithography and dry etching, and the epitaxial germanium mesas for the PDs were selectively grown on the silicon waveguides by chemical vapor deposition. The waveguides, modulators, and PDs were then covered with the SiO 2 upper cladding layer by chemical vapor deposition. The waveguide end faces and the pedestals for the LD mount were formed by dry etching before an arrayed LD chip was integrated on the substrate with a passive alignment technique [8]. Optical components for the interposer in SiP are required to be temperature independent due to their positioning near the s. Furthermore, for the small and highly efficient O/E or E/O converters, it is important to design the structures that have strong interaction between the optical field and electrical carriers. For realizing optical modulators with both small size and high efficiency, the interaction between the optical field and the electrical carriers is maximized by strong confinement of them. Therefore, we chose to implement a channel waveguide with large optical confinement, and formed a side-wall grating along the waveguide for carrier injection and confinement, as shown in Fig. 4a [9]. This waveguide structure generally has the trade-off between waveguide loss and operation speed. The grating pitch should be carefully designed so that the wavelength of the input light would be outside the stop-band formed on the spectrum. Furthermore, we applied a Mach- Zehnder interferometer for both temperatureand wavelength-independent operation. Arrayed LD chip 8-ch optical transmitter array 8-ch optical receiver array Figure 3. Mounting s on an interposer. Flip-chip pads for Silicon optical waveguides bare chip For the Germanium (Ge) photodiodes, we used a PIN structure as shown in Fig. 4b []. The thickness of Ge was optimized for effectively applying electric fields to carriers produced by light absorption. This enabled us to realize efficient optical absorption with a small (less than 30 mm long) Ge mesa. Figure 4c shows a photograph of the fabricated silicon optical interposer on a 5 mm 5 mm substrate. An SSC array, a 4 optical splitter, an optical modulator array, and a PD array were all monolithically integrated onto a single silicon substrate. A 3-channel arrayed LD chip was Silicon optical interposer x 8-splitter 8-ch modulator array : 8-ch PD array Signals from neighbor Platform for LD mount Arrayed LD chip bare chip CW light form LD Signals to neighbor Aluminum electrode SiO 2 Arrayed LD Modulator array PD array AI AI (a) MMI coupler Silicon waveguide Metal p-si Si n + Si P + Box Ge n + -Ge SSC array 5 mm x 4 splitter Optical waveguide array (b) 5 mm Figure 4. Fabrication of a silicon optical interposer: a) modulator; b) photo detector; c) photograph of a silicon optical interposer. (c) IEEE Communications Magazine March 203 75

integrated onto the substrate as a hybrid structure, and these optical components were optically linked to each other via the silicon optical waveguide array. The measured eye data of the PD output on the silicon optical interposer at 2.5 Gb/s nonreturn to zero (NRZ) with a 2 7 pseudo-random binary sequence (PRBS) via the 4 optical splitter is shown in the inset of Fig. 5. The clear eye opening suggests that the optical links were capable of data transmission at 2.5 Gb/s. The measured bit error rates (BERs) for the 2.5 Gb/s PRBS are plotted in Fig. 5. We confirmed that the BER was less than 2 when the PD input power was more than.8 dbm. Error-free transmission at 2.5 Gb/s via the 4 optical splitter was therefore successfully achieved. The total footprint was 0.9 mm 2 per channel, meaning that we could achieve a bandwidth density of 6.6 Tb/s/cm 2 with a channel line rate of 2.5 Gb/s. We note here that about two-thirds of the total footprint was actually occupied by the electrode pads, and we can expect to improve the bandwidth density further by using smaller pads in the near future. The overall inter-chip bandwidth for high-end servers is expected to reach around the Tb/s level by the late 20s [2]. The typical CPU die size will be about 2 cm 2 (related to the yields or the costs), and therefore, a bandwidth density of around Tb/s/cm 2 will be required by the late 20s for chip-to-chip interconnects. Figure 6 shows the throughput of various types of optical modules against their inverse area. In general, interconnects for shorter distance have smaller footprints and wider bandwidths (i.e., higher bandwidth densities). From this figure, we can see that Tb/s/cm 2 is perhaps a reasonable target for chip-to-chip interconnects in a high-end server application. Bit error rate -3-4 -5-6 -7-8 -9 - - -2-3 -5 - -5 PD input power (dbm) Figure 5. Bit error rates for 2.5 Gb/s NRZ PRBS with eye diagram. Bandwidth (Gb/s) 0 0.0 Gb/s/cm 2 Gb/s/cm 2 LAN-WAN Gb/s/cm 2 Inter-racks Tb/s/cm 2 Inter-boards Tb/s/cm 2 Chip-to-chip Commercially available Under R&D 0. /module area (cm -2 ) Interposer Figure 6. Bandwidth per area for interconnection modules. 2.5 Gb/s 2 7 - PRBS Packaging density available to realize interposer Tb/s interconnection to bare chip SILICON PHOTONICS AS SURFACE MOUNTED COMPONENTS A set of surface mounted components has been envisaged and designed to be used by system engineers without deep knowledge of photonics technology (Fig. 7). The three components are designed to provide photonic interconnection seamlessly. The first is a micro active optical cable (AOC), which will connect any point on the board (with an electrical ) to another point using a connector size of 5 mm 2, much smaller than a conventional AOC. Inside the connector, small high-speed silicon photonic circuits, operating at 25 Gb/s to 40 Gb/s, provide E/O and O/E s. The micro AOC will achieve throughputs of 200 Gb/s to Tb/s per cable. Second, an mounted hybrid AOC will provide optical and electrical interconnection. The component provides high-frequency signal lines through optical fiber ribbons as well as electronic wiring connection in low speed. When we apply a field programmable gate array (FPGA) or graphic processing unit (GPU) as an, this approach will behave like a special accelerator for image processing, pattern recognition, object understanding, and so on. Third, the on-chip server will provide high speed, low power, and a very small footprint by utilizing both photonics and electronics. The photonics interconnection will reduce the total power consumption of the server by more than 30 per cent as our target, since the photonics wiring will reduce the power consumption generated by electrical wiring. CONCLUSION We have discussed recent advances in semiconductor technology and the subsequent requirements that future chip-to-chip interconnections should exhibit speeds times higher than those used today. To meet those requirements, a photonics-electronics convergence system with a silicon optical interposer has been proposed to 76 IEEE Communications Magazine March 203

solve the bandwidth bottleneck problem that chip-to-chip electronic interconnects have. Key technologies for the integration and development of the photonic devices are described. A fabricated prototype device employing a high-density optical interposer using silicon photonics integrated with these optical components on a single silicon substrate was described and shown to demonstrate error-free data transmission at 2.5 Gb/s and a bandwidth density of 6.6 Tb/s/cm 2. Finally, a surface mounted components approach was introduced so that a system engineer without special photonics knowledge could utilize the system. ACKNOWLEDGMENTS This research is partly supported by the Cabinet Office through its Funding Program for World- Leading Innovative R&D on Science and Technology (FIRST) Program, and partly supported by the Ministry of Economy, Trade and Industry through its Future Pioneering Project. REFERENCES [] R. Jammy, Evolution of Device Technologies and Revolution needed in Manufacturing, Int l. Symp. Semiconductor Manufacturing 2, Tokyo, Japan. [2] I. A. Young et al., Optical Technology for Energy Efficient I/O in High Performance Computing, IEEE Commun. Mag., vol. 48, no., Oct. 20, pp.84-9. [3] P. D. Dobbelaere et al., Si Photonics Based High-Speed Optical Transceivers, ECOC 2, We..E.5, 202. [4] S. Assefa et al., A 90 nm CMOS Integrated Nano-Photonics Technology for 25 Gb/s WDM Optical Communications Applications, IEEE IEDM 2, 33.8, 202. [5] X. Zheng et al., 2-pJ/bit (On-Chip) -Gb/s Digital CMOS Silicon Photonic Link, IEEE Photonics Technology Letters, vol. 24, no. 4, 202, p. 260. [6] A. Alduino, Demonstration of a High Speed 4-Channel Integrated Silicon Photonics WDM Link with Hybrid Silicon Lasers, Hot Chips 22, Session 3, 20. [7] Y. Urino et al., First Demonstration of High Density Optical Interconnects Integrated with Lasers, Optical Modulators and Photodetectors on Single Silicon substrate, Opt. Exp., vol.9, no.26, B59-B65, Dec. 20. [8] N. Fujioka, T. Chu, and M. Ishizaka, Compact and Low Power Consumption Hybrid Integrated Wavelength Tunable Laser Module Using Silicon Waveguide Resonators, IEEE J. Lightwave Tech., vol. 28, no. 2, Nov. 20, pp. 35 20. [9] S. Akiyama et al., 2.5-Gb/s Operation with 0.29-V cm VpL Using Silicon Mach-Zehnder Modulator Based on Forward-Biased Pin Diode, Opt. Exp., vol. 20, no. 3, Jan. 202, pp. 29 23. [] J. Fujikata et al., 45 GHz Bandwidth of Si Waveguide- Integrated PIN Ge Photodiode, and Its Zero-Bias Voltage Operation, Proc. Int l. Conf. Solid State Devices and Materials, A-7-3, Sept. 202. BIOGRAPHIES YASUHIKO A RAKAWA [F] (arakawa@iis.u-tokyo.ac.jp) received his B.S., M.S., and Ph.D. degrees in electronics and electrical engineering from the University of Tokyo in 975, 977, and 980, respectively. In 980, he joined the University of Tokyo as an assistant professor and became a full professor in 993. He is currently the director of the Center for Photonics Electronics Convergence (CPEC), Institute of Industrial Science, and also the Bandwidth density (Tb/s/cm 2 ) 0. 0.0 μ-aoc Active optical cable with small connectors (20 m ~ cm) (205) mounted hybrid AOC High speed signals are connected through optical cables (fiber ribbons) (50 cm ~ 5 cm) (2020) Figure 7. Surface mounted components for photonic interconnection. director of the Institute for Nano Quantum Information Electronics (Nano Quine), University of Tokyo. He is a member of the Science Council of Japan, a Vice President of ICO, the Asian Regional Editor in Chief of NJP, and a member of the Joint APL-JAP Editorial Board. He has been made a Fellow of OSA, JSAP, and IEICE. His major research fields include physics, growth, and photonics applications of the quantum dot. He is leading a national project named Photonics and Electronics Convergence System Technology (PECST) of the FIRST program. He has received several major awards including the Leo Esaki Award (2004), the IEEE/LEOS William Streifer Award (2004), the Fujiwara Award (2007), the Prime Minister Award (2007), the Medal with Purple Ribbon (2009), the IEEE David Sarnoff Award (2009), the C&C Award (20), the Welker Award (20), and the OSA Nick Holonyak Jr. Award (20). TAKAHIRO NAKAMURA (t-nakamura@petra-jp.org) received B.E., M.E., and D.E. degrees in electrical engineering from Osaka University, Japan in 986, 988, and 2005, respectively. He joined NEC Corporation in 988, where he has been engaged in the research and development of laser diodes. He is currently a temorary chief manager in PETRA. He is a member of the IEICE. YUTAKA URINO (y-urino@petra-jp.org) received his B.E. degree in communication engineering and M.E. degree in electronic engineering from Tohoku University, Japan, in 985 and 987, respectively. He joined NEC Corporation, where he has been engaged in the research and development of optical waveguide device subsystems. He is currently a temporary chief researcher at PETRA. He is a member of the IEICE. TOMOYUKI FUJITA [M] (t-fujita@petra-jp.org) received his B.E. and M.E. degrees in electronics and communication engineering from Waseda University, Japan, in 976 and 978, respectively. He joined NEC Corporation in 978 as a researcher of computer aided design and became a research manager in 989. He was a visiting researcher at the University of California at Berkeley in 983 through 984. He was a director of the planning office at NEC Central Research Labs in 999 and a deputy managing director of NEC China Labs in Beijing in 2003. He has been an executive director of PETRA since 2009. He is a member of the IEICE and IPSJ. On-chip server Photonics and electronics converged Si interposer with many-core, 3D-MEM and 3D-SSD. (50 cm ~ 5 mm) (2025) 0 /Distance (m - ) (Year) IEEE Communications Magazine March 203 77