Simulation of Simultaneous All Optical Clock Extraction and Demultiplexing for OTDM Packet Signal Using a SMZ Switch

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1 Simulation of Simultaneous All Optical Clock Extraction and Demultiplexing for OTDM Packet Signal Using a SMZ Switch R. Ngah, and Z. Ghassemlooy, Northumbria University, United Kingdom Abstract In this paper we report the simulation results of simultaneous all optical clock extraction and demultiplexing from 4x10 GHz asynchronous optical time division multiplexed (OTDM) packet signals using a single symmetric Mach-Zehnder (SMZ) switch. In highspeed OTDM systems clock recovery, the address recognition and the payload routing are all should be carried out in the optical domain in order to avoid the bottleneck due to the optoelectronics conversion. Simulation results demonstrate that clock recovery, and payload demultiplexing is possible with high on-off ratio. Bit error rate performance shows that penalty free is achieved for 40-10Gb/s all-optical demultiplexing. 1.0 Introduction With ever-increasing amount of data traffic over the existing network due to the recent advancements in multimedia computing and communication technologies, the need for switching and routing data in all optical domain is increasingly becoming important. Alloptical packet switching overcomes the speed bottleneck due to electronics and potentially offering larger capacity, increased flexibility and format transparency, and low cost in the long run [1-2]. In packet-switched OTDM networks, there is a need for clock and address extraction from the payload at the network node level. The recovery of the clock signal for synchronization will determine the performance of ultra-fast OTDM networks. For asynchronous packet-switched networks, synchronization can be achieved by sending at least one optical clock pulse with every OTDM packet transmitted. Selfsynchronization schemes are attractive for optical packet networks because of reduced hardware cost and control complexity [3], and only require a single pulse in the first bit position of the packet that corresponds to the clock pulse. The clock signal could be at different wavelengths [4], polarizations [5], bit rates [6], or intensities [7] in relation to the remaining signals in the packets. Clock extraction schemes using all-optical switches have been extensively investigated for the implementation of self-synchronization schemes [8][9][12]. All optical switches based on cross-phase modulation (XPM) in conjunction with interferometric arrangement are now well founded, offering efficient switching using low control pulses energy compared with the passive devices [9]. Among various interferometer based switch configurations, the SMZ structure provide the most flexibility, shortest switching window, compact size, thermal stability and low-power operation. A single SMZ switch with electro-optic feedback loop has been employed for simultaneous all-optical clock

2 recovery and demultiplexing of OTDM signal [10]. However it uses additional components such as a high-q filter and a mode-locked laser diode in the electro-optic loop oscillator configuration to generate control signals at different wavelength compared with the OTDM data signal. These schemes have a number of drawbacks such as: complex packets generation and transmission, and loss of timing relation between the clock and other pulses in the same packets after propagating a long distance [11]. In this paper, we simulate simultaneous all-optical clock recovery and demultiplexing using a single SMZ switch with an optical feedback. Since the same intensity, polarization, width and wavelength have been used for the entire packet including the clock pulse; there is no requirement for additional filter and laser in the optical feedback loop. 2.0 Clock Recovery Scheme Figure 1 shows the proposed clock and data an extraction module that is composed of OFDLs, a SMZ in combination with an optical feedback, a polarization controller (PC) and a polarization beam splitter (PBS). As mentioned in the previous section, in a selfsynchronization scheme, the clock pulse positioned at the head of incoming OTDM packet first enters the SMZ module via an input 3-dB coupler, splits into two components, with a π/2 phase shift due to the input coupler, and propagate through physically separate arms of the interferometer. Since there is no control pulse present within the loop, initially the two clock pulses experience the same relative phase shift during propagation and recombine at the output 3-dB coupler before re-emerging from the reflected output port 2. CS 1 OFDL Clock + data packet in SOA1 Transmitted port (Port 1) PBS Demultiplexed Channel OFDL CS 2 SOA2 Reflected port (Port 2) Extracted clock pulse PC SOA Fig.1 Block diagram for clock extraction and demultiplexing The reflected clock pulse is amplified and passed through a PC before being fed back via an OFDL into the control ports of the interferometer orthogonally polarized to the data packet. OFDLs are used to create the delay time T delay between the two input control pulses. With the control signals present a differential phase shift is introduced between the two arms of the interferometer, thus causing the data pulses to be switched to the transmitted port (port 1). In order to achieve a complete switching an 180 o phase shift must be attained by introducing a first control signal (CS 1) into SOA1 to set the switching window. The second control signal (CS 2) delayed by T delay is applied into

3 SOA2, which result in the same phase shift induced in lower arm, thereby resetting the switch. Therefore, the SMZ switch-on-and-off time is controlled by the fast optical excitation process hence slow relaxation time can be overcome. Note that T delay determines the nominal width of the switching window of SMZ. At the output port 1 of the SMZ a PBS is used to separate the outgoing data and the control pulses. With this approach, the synchronization is achieved by inserting only a single clock pulse that has the same width, wavelength, polarisation and amplitude as the pulses in the payload within the OTDM packets. 3.0 Simulation of Clock Recovery Using VPI and Results The proposed SMZ clock recovery shown in Fig. 1 is simulated using VPI simulation software package as shown in Fig. 2. All relevant simulation parameters are shown in Table 1. Fig. 2 A schematic of clock recovery using VPI software Table 1 Simulation parameters Parameters Values Data and control pulses Data bit rate per channel 10 Gb/s Clock pulse FWHM width 1 ps Address bit FWHM width 1 ps Data bit FWHM width 1 ps Control and data wavelength 1550 nm Data pulse peak power 1.0 mw Control pulse peak power 1.2 W SOA Injection current 0.15 A Length 0.3 mm Active area 3.0x10-13 m 2 Transparent carrier density 1.0x10 24 m -3 Confinement factor 0.15 Differential gain 2.78x10 20 m 2 Linewidth enhancement 4.0 Recombination coeff. A 1.43x10 8 1/s Recombination coeff. B 1.0x10-16 m 3 /s Recombination coeff. C 3.0x10-41 m 6 /s Initial carrier density 2.8x10 24 m -3

4 Figure 3 shows an OTDM packet composed of a clock pulse (first bit), followed by an address (a single bit) and payloads (two bits). All the signals have the same amplitude, polarization and wavelength. The aggregate bit rate is 40 Gb/s, and each bit is represented by a very-low duty cycle pulse of 1 ps full-width at half-maximum (FWHM). As described in the previous section, the clock pulse is extracted from the incoming OTDM pulse stream using SMZ1, and the result is shown in Fig. 4. From the figure, we can observe that more than 15 db intensity contrast ratio has been achieved utilizing the self-synchronization scheme. Fig. 3 OTDM input packet Fig. 4 Extracted clock signal The extracted clock is first passed through a 90 o polarizer to distinguish it from the data pulse since both are at the same wavelength of 1550 nm, followed by amplification before being fed back into the control port of the SMZ. OFDLs are used for time synchronization between the control and data pulses. T delay of 30 ps is used to create a switching window for extraction of 10Gb/s, the last payload from the remaining data packet (address bit and payload bit) via the transmitted output port 1 of the interferometer as shown in Fig. 5. Is is shown that using this technique, clock recovery and demultiplexing from a 40 Gb/s OTDM packet signal into a 10 Gb/s can be performed simultaneously by using a single SMZ switch. Fig. 5 Demultiplexing 10 Gb/s signal from 40 Gb/s OTDM signal Next we consider the bit error rate (BER) performance of the proposed clock recovery and demultiplexing module by means of VPI simulation. The baseline bit rate is 10 Gb/s

5 and all the sensitivity measures are referred to an average BER of A total of 2048 packets were used for the BER measurement. Figure 6(a) shows the receiver sensitivity of 38 db is achieved for the baseline detection without the SMZ switch. Penalty free demultiplexing at 40 to 10 Gb/s and 0.3 db power penalties for 80 and 160 to 10 Gb/s is achieved as shown in Fig back-to-back 10Gb/s SMZ 4x10Gb/s SMZ 8x10 Gb/s SMZ 16x10 Gb/s BER Received power (dbm) Fig. 6 BER against the average received power for (a) baseline without demultiplexer, (b) Gb/s demultiplexing, (c) Gb/s demultiplexing and (d) Gb/s demultiplexing 4.0 Conclusions We have proposed a simultaneous self-synchronization scheme and demultiplexing for OTDM packet networks using a single all-optical SMZ switch with a simple optical feedback loop. Also presented was the simulated BER performance for the module. Error free Gb/s demultiplexing is achieved and a small power penalty of 0.3 db is recorded for 80 and 160 to 10 Gb/s demultiplexing. References [1] Q.Yang et al., WDM Routing in Photonic Packet Switch, Lasers and Electro-Optics Society 2000 Annual Meeting, 2000, 13 th Meeting, IEEE Vol.1, pp , 2000 [2] O. Komolafe et al., Deployment of Architectures for Future High Speed Packet Switched Optical Networks, IEE 16 th UK Teletraffic Symposium (UKTS), May [3] X.C. Yuan et al., A Novel Self-Routing Address Scheme for All-Optical Packet-Switched Networks With Arbitrary Topologies, J. Lightwave Technol. Vol. 21, pp , Feb [4] Y. Shimazu et al., Ultrafast Photonic ATM Switch with output Buffers, IEEE J. Lightwave Technol., 10, pp , [5] K. L. Deng, et al., Unbalanced TOAD for Optical Data and Clock Separation in Self-clocked Transparent OTDM Networks, IEEE Photon. Technol. Lett. Vol.9, pp , 1997.

6 [6] D. Cotter, et al., Self-routing of 100 Gbit/s Packets using 6 bit Keyword Address Recognition, Electron. Lett. Vol.31, pp , Dec [7] R.A. Barry, et al., All-optical Network Consortium-ultrafast TDM Networks, IEEE J. Select. Areas Commun., Vol 14, pp , [8] J.M.Tang, et al., Ultrafast Optical Packet Switching using Low Optical Pulse Energies in a Selfsynchronization Scheme, J. Lightwave Technol. Vol. 18, pp , Dec [9] P. Toliver, et al., All-optical Clock and Data Separation Technique for Asynchronous Packet-switched Optical Time-division-multipled Networks, Opt. Commun., Vol.173, pp , Jan [10] T. Miyazaki, et al., Simultaneous Demultiplexing and Clock Recovery for 160-Gb/s OTDM Signal Using a Symmetric Mach-Zehnder Switch in Electrooptic Feedback Loop, IEEE Photon. Technol. Lett. Vol.15, pp , Jul [11] Z. Xiang et al., Theory of Ultrahigh-Speed Clock Extraction with Phase Lock Loop Based on a Terahertz Optical asymmetric Demultiplexer, Optical Communication, No.159, pp , [12] M. C. Cardakli, and A. E. Willner, Synchronization of a Network Element for Optical Packet Switching using Optical Correlators and Wavelength Shifting, IEEE Photon. Technol. Lett. Vol.14, pp , Sep R. Ngah, and Z. Ghassemlooy Optical Communication Research Group, School of Engineering & Technology, Northumbria University, Newcastle Upon Tyne, NE1 8ST United Kingdom Tel: , Fax: , razali.ngah@unn.ac.uk, and fary.ghassemlooy@unn.ac.uk

Simulation of an all Optical Time Division Multiplexing Router Employing Symmetric Mach-Zehnder (SMZ)

Simulation of an all Optical Time Division Multiplexing Router Employing Symmetric Mach-Zehnder (SMZ) Razali Ngah, Zabih Ghassemlooy, and Graham Swift Optical Communications Research Group, School of Engineering,