EE 3170 Microcontroller Applications Lecture 4 : Processors, Computers, and Controllers - 1.2 (reading assignment), 1.3-1.5 Based on slides for ECE3170 by Profs. Kieckhafer, Davis, Tan, and Cischke Outline Digital System Preliminaries Digital System Definitions Controller Implementations Programmable Control The Instruction Fetch/Execute Cycle More Definitions processor computer micro-what?? EE3170/CC/Lecture#4 1 EE3170/CC/Lecture#4 2 Digital System Preliminaries Combinational Logic Functions Combinational Logic Functions Sequential Logic Functions Registers Combinational Logic = any function such that: current values of the output variables depend only on current values of the input variables Properties: there are no internal (or state) variables or memory values of outputs are history-independent Busses Memory Representations: Truth tables Karnaugh Maps Boolean algebraic equations A network of logic gates EE3170/CC/Lecture#4 3 EE3170/CC/Lecture#4 4 1
Standard Logic Gates Sequential Logic Functions You should already know the truth tables and Boolean equations for each of the following: Sequential Logic = any function such that: current values of the output variables depend on both: current values of the input variables and stored values of state variables Properties: values of the outputs are history-dependent state variables imply storage of previous information Representations: State transition diagrams State transition tables A network of logic gates EE3170/CC/Lecture#4 5 EE3170/CC/Lecture#4 6 Edge-Triggered D Flip-Flop Registers Function Latches input only on one edge of the CK signal As diagrammed: triggers on rising edge Alternative: trigger on falling edge A collection of flip flops that are clocked as a unit. Together, flip flops remember several binary signals that represent a binary number Gated Registers Clock signal is ANDed with an ENABLE signal Register latches ONLY when permitted by ENABLE Very few registers are unconditionally enabled Problem in fast processors due to clock skew State Transition Table Many FF Variations Exist SR, Toggle (T), JK, D EE3170/CC/Lecture#4 7 EE3170/CC/Lecture#4 8 2
Busses Memory Bus = a group of one-bit lines (wires) that collectively carry a binary number where each wire transmits one bit of a number generally controlled and operated as a single unit a transfer gate is an AND gate used to pass (or block) a binary signal to another wire (pp.20:figure1-9) Notation: A Memory: a collection of registers made from flip flops One register is accessed at a time, each register is assigned a binary code number (addr) by memory hardware A Memory = a collection of data words such that: each word contains a fixed number of stored bits each word has a unique address (I.D. number) each word can be accessed individually by specifying its address to the memory device Words are typically bytes but not always Alternative Model A memory is an array of fixed-size entries The address is the array index e.g. Mem[8A] specifies the word at address 8A EE3170/CC/Lecture#4 9 EE3170/CC/Lecture#4 10 Memory Interfacing Synchronous Sequential Networks N = num. of bits in address = log 2 (num. of words) w = word width = num. of bits in one word A logic network containing sequential devices A circuit made from a CLN and clocked flip-flops E.g., pp.24: figure 1-12 A State-based net with a common global clock signal clock = periodic square wave signal all state changes in state occur on a clock edge State Variables: A set of binary variables defining the current state Stored in a set of state flip-flops all are triggered with the same clock-edge EE3170/CC/Lecture#4 11 EE3170/CC/Lecture#4 12 3
State Transition Diagram A directed graph defining system behavior Vertices = states edges = allowable state transitions E.g., pp.25: figure1-13 Visually Defines: The set of all states The values of all output variables The allowable state transitions The input variable value (s) which cause each state transition Notation E.g., pp.25: figure 1-13 State = circle labeled with values of state variables transition = vector labeled with input variable value(s) which cause this transition output variable value(s) for the state being left Notation: inputs/outputs Trivial example: D Flip-Flop Two states (0,1) One input variable One output variable EE3170/CC/Lecture#4 13 EE3170/CC/Lecture#4 14 Digital System What is meant by Control? Digital System: A system comprising: Combinational Logic Registers: a collection of flip-flops A Synchronous Sequential Controller: CLNs+ flip-flops Analyzes inputs, Sequences the state transitions, Sends control signals to the other components Structure of the controller is the critical feature Hardwired control Programmable (instruction-based) control State Transitions!!! A Microprocessor is a VERY complex FSM Inputs : Current Instruction, Register Contents, System State Outputs : Next State, Address of next instruction, Updated Register Contents How do we go from 1 (very complex) state to the next (also very complex) state State Transition Tables Instruction Sequencing The instruction number tells the control unit which sequence of states to follow EE3170/CC/Lecture#4 15 EE3170/CC/Lecture#4 16 4
Hardwired Control Programmable Control State Transition Rules are embedded into the controller hardware State machine responds to inputs Function of state machine does not change Small finite number of states Example: serial communication unit (Miller, Fig 1-15) Reading assignment: pp.26-33 A 16-bit shift register managed by control unit Control Unit responds to a sequence of instructions stored in memory. State machine actions (some require >1 cycle) Fetch an instruction from memory Decode the instruction Execute the instruction Sequence and issue control signals to other components Calculate address of next instruction Microcode (older terminology) or Micro-op approach taken w/ CISC ISA micro s w/ RISC core(s) EE3170/CC/Lecture#4 17 EE3170/CC/Lecture#4 18 Control Example (skipped) Digital System Partitioning Control Unit State machine to implement instruction cycle fetch, decode, execute, calc next address Control registers and bussing Memory interface for instructions Data Unit Arithmetic & Logic Unit (ALU) to manipulate data Actual function determined by control signals Data registers and bussing Memory interface for data EE3170/CC/Lecture#4 19 EE3170/CC/Lecture#4 20 5
Very Simple Example A Few Notes (Skipped) Uses OR gates to share bus access CLN Alternative: Tri-state drivers Each driver has an enable pin IF: enable = 1 THEN: output = input ELSE: output = High-Z state (disconnected) Reading assignment: pp.28-33 SSN Alternative: Wired-OR bus IF: all outputs to the bus = 0 THEN: bus value = 0 ELSE: bus value = 1 EE3170/CC/Lecture#4 21 EE3170/CC/Lecture#4 22 Instruction Sequencing Fetch an Instruction Steps in the execution of a single instruction May be pipelined or not Read the Program Counter (PC) Special purp. register containing address of instruction Access the memory Send contents of PC to memory on address bus Send read command to memory on control bus Intel P6 Generation (Pentium Pro, Pentium II & Pentium III) have >20 steps Receive the instruction Instruction comes from memory over data bus Store instruction in Instruction Register (IR) EE3170/CC/Lecture#4 23 EE3170/CC/Lecture#4 24 6
Decode the Instruction Execute the Instruction Interpret the instruction in the IR Instruction will have several functional fields OPCODE: identifies the operation to be executed (Add, Sub, etc) identifies structure of rest of the instruction OTHER STUFF: e.g. Data value(s) IDs of the register(s) containing the data Memory address(es) of the data Generate & sequence control signals to data unit Route data to the ALU Send command signals to the ALU Route data to its destination Implement any memory accesses for data Implement any I/O actions EE3170/CC/Lecture#4 25 EE3170/CC/Lecture#4 26 Calculate Address of Next Instruction Usually just increment the Program Counter (PC) Normal sequential flow through the program Exception: a Branch instruction tells the control Unit to alter the next address new address is embedded in the branch instruction controller writes the new address into the PC Decision to alter flow may be data-dependent, e.g. IF: the previous ALU output = 0 THEN: load the new address into the PC ELSE: just increment the old address in the PC EE3170/CC/Lecture#4 27 Instruction Set The set of operations a machine can carry out Each identified w/ a particular instruction code in mem. Instruction set of general purpose computer Load & Store: Load data from mem. Into reg. or store data from a reg. to memory Test & Branch: Make decision based on processor status output Arithmetic: Add, subtract, etc. Logical: Bit-wise AND, OR, complement, etc. Shift: Shift or rotate bits left or right in various ways Input & Output: Transfer data from or to reg. in I/O block EE3170/CC/Lecture#4 28 7
So, what exactly is a Processor? So, what exactly is a Computer? Hardware partitioning as previously described Control Unit responds to stored instructions Data Unit responds to control signals ALU + register Executes a list of instructions in sequence Instructions are stored in a memory Can execute branch instructions Especially data-dependent or Conditional Branches One or more processors If just one, called Central Processing Unit (CPU) e.g. 68HC11, 80286, Pentium, Athlon, SPARC, etc A memory system Stores both instructions and data e.g. RAM, ROM, Disks, etc An input/output (I/O) system provides interfaces to the outside world e.g. keyboards, mice, monitors, printers Bussing to link together all the above components EE3170/CC/Lecture#4 29 EE3170/CC/Lecture#4 30 General Purpose Computer: Princeton Architecture ALU + register Figure1-18 Stored Program Processor (Princeton/Von Neumann Architecture) EE3170/CC/Lecture#4 31 Building Blocks of General Purpose Computer Processor Arithmetic ALU Addition, subtraction, bit-wise AND/OR, shifts, etc Registers Memory register + addresses for data storing Instruction Codes & Data Input/Output a set of registers to hold/receive data for transfer Control Unit A synchronous sequential machine controls flow of data and operations among blocks Clock Used for the control unit synchronous sequential machine. EE3170/CC/Lecture#4 32 8
General Purpose Computer: Harvard Architecture Higher speed & increased complexity Separate instruction & data memories Allow fetch & execute cycles to proceed in parallel PIC family of microcomputers from Microchip Tech use Harvard architecture Harvard Architecture Source: PIC Reference Manual EE3170/CC/Lecture#4 33 EE3170/CC/Lecture#4 34 Definitions: Micro-what?? Microprocessor = a processor that fits on one chip e.g. 80386, 80486, Pentium, Athlon, SPARC Microcomputer = computer with a microproc. as CPU Includes CPU, memory, I/O, and bussing e.g. all PCs and Workstations Single-Chip Microcomputer = (the obvious) Microcontroller = A single-chip microcomputer optimized for embedded control applications I/O architecture is most obvious optimization e.g. 68HC11 EE3170/CC/Lecture#4 35 Instruction Set Architecture (ISA) Defines those features of the processor architecture visible to the programmer Instruction formats length of opcodes, number of operands (one of the inputs (arguments) of an operator), field meanings Opcodes: the portion of a machine language instruction that specifies the operation to be performed what the decoder is to do with each opcode number Memory addressing modes Data registers and their uses Number of registers, special purposes, register windows Data word size(s) EE3170/CC/Lecture#4 36 9
Microarchitecture Implementation details of the processor Special purpose registers Rename register files more physical registers than those in ISA e.g. PC, IR, internal buffers, temp registers, & drivers How instructions are sequenced How data dependencies between instr. are managed Number of concurrent pipelines Out-of-order execution implementations etc, etc, etc... These details are generally not visible to programmer Can not be directly controlled by instructions EE3170/CC/Lecture#4 37 EE3170/CC/Lecture#4 38 1-bit Full Adder Truth Table 1-bit Full Adder Implementation Boolean Equations: For each output variable on the truth table: Find all rows where that output = 1 AND the input polarities for each row (logical product) OR inputs for all such rows (logical sum of products) Logic Diagram: Minimize the logic equations (e.g. Karnaugh map) Implement the minimized logic equations using combinational logic EE3170/CC/Lecture#4 39 EE3170/CC/Lecture#4 40 10