JESD204B Xilinx/IDT DAC1658D-53D interoperability Report

[Interoperability Report] Rev 0.4 Page 1 of 14 JESD204B Xilinx/IDT DAC1658D-53D interoperability Report

[Interoperability Report] Rev 0.4 Page 2 of 14 CONTENTS INTRODUCTION... 3 SCOPE... 3 HARDWARE... 3 XILINX KC705 EVAL BOARD... 3 IDT DAC1658D/DAC1653D HW EVAL BOARD... 3 XILINX IP CONFIGURATION... 4 INTEROPERABILITY TEST RESULTS... 5 COMPLIANCE TO JESD204B SPECIFICATION... 10 DOCUMENT HISTORY... 14

[Interoperability Report] Rev 0.4 Page 3 of 14 Introduction This document describes the method and tests to be carried out to test interoperability between the Xilinx(R) LogiCORE(TM) JESD204 IP and the IDT DAC1658D and DAC1653D. Scope Interoperability testing used existing hardware supporting JESD204B subclasses 0, 1 and 2. Line rates of 3.125G, 6.375G, 10G, and 12.5Gbps were tested. Hardware Xilinx KC705 Eval Board The Kintex -7 FPGA KC705 Evaluation Kit includes all the basic components of hardware, design tools, IP, and a preverified reference design for system designs that demand high-performance, serial connectivity and advanced memory interfacing. The included pre-verified reference designs and industry-standard FPGA Mezzanine Connectors (FMC) allow scaling and customization with daughter cards. IDT DAC1658D/DAC1653D HW Eval Board The board used is referenced as DAC1653D1G5-DB or DAC1658D1G5-DB.Its main characteristics are: One dual high-speed serial JESD204B DAC with four lanes input. Populated device can be DAC1658D1G5 or DAC1653D1G5; One (SAMTEC FMC) high density connector to interface with compatible carrier board; One USB to SPI master device. It can be bypassed and the demo board can be controlled from the carrier through the FMC connector; On-board voltage regulators for all devices on the board; Clock divider (by 1, 2, 4, 8 or 16) to drive carrier board clock input. The DAC1653D and the DAC1658D are high-speed high-performance 16-bit dual channel Digital-to-Analog Converters (DACs). The devices provide sample rates up to 2 Gsps with selectable 2X, 4X and 8X interpolation filters optimized for multi-carrier and broadband wireless transmitters. The DAC165xD integrates a JEDEC JESD204B compatible high-speed serial input data interface running up to 10 Gbps allowing dual channel input sampling at up to 1 Gsps over four differential lanes. There are two versions of the DAC165xD: Low common-mode output voltage (part identification DAC1653D) High common-mode output voltage (part identification DAC1658D) An optional on-chip digital modulator converts the complex I/Q pattern from baseband to IF. The mixer frequency is set by writing to the Serial Peripheral Interface (SPI) control registers associated with the on-chip 40-bit Numerically

[Interoperability Report] Rev 0.4 Page 4 of 14 Controlled Oscillator (NCO). This accurately places the IF carrier in the frequency domain. The 16-bit phase adjustment feature, the 12-bit digital gain and the 16-bit digital offset enable full control of the analog output signals. The DAC165xD is fully compatible with device subclass 0 and 1 of the JEDEC JESD204B standard, guaranteeing deterministic and repeatable interface latency using the differential SYSREF signal. The device also supports harmonic clocking to reduce system-level clock synthesis and distribution challenges. Multiple Device Synchronization (MDS) enables multiple DAC channels to be sample synchronous MDS and phase coherent to within one DAC clock period. MDS is ideal for LTE and LTE-A MIMO transceiver applications. The DAC165xD includes a 2, 4 or 8 divider to achieve the best possible noise performance at the analog outputs, allowing harmonic clocking through the system. Hardware Setup The KC705 is configured in its default state and powered using the supplied PSU. The USB JTAG is required for connection to the controlling PC. The DAC165xD1G5-DB HW evaluation board connects directly to the KC705 (HPC) FMC connector. A separate power supply is required for the DAC165xD. The USB cable is required to connect to the controlling PC. The frequency generator is connected to DAC board DAC_CK SMA connector. Reference clock to FPGA is supplied from the DAC board via FMC connector. To supply the correct frequency, S0, S1 and S2 jumpers have to be properly set to divide down by 2. As, example, if the DAC clock frequency is 1,2GHz, the FPGA reference clock is 600MHz and the data rate on the lanes will be 6Gbps. DAC must be set to operate in by 2 interpolation and use all the 4 lanes. Chipscope(TM) is continuously polling KC705 through the USB and so is doing IDT control software with the DAC board. Some access conflicts might arise. To overcome this situation, one should disable chipscope polling. Xilinx IP Configuration The Xilinx LogiCORE JESD204 IP Core supports JESD204A and JESD204B on Virtex(R)-6 and Kintex-7 devices. See the IP User Guide for details. The IP shall be configured for Kintex-7 devices only for interoperability testing. The Example design RTL will require modification in order to generate the correct control and data signals to complete interoperability testing.

[Interoperability Report] Rev 0.4 Page 5 of 14 Interoperability Test Results The following table details teh tests carried out and the results. Test Number Test Description Interoperable Notes 1 Sync request Test correct operation when sync~ is requested by the receiver. Subclass 0 and 2. The receiver should request sync following reset. It also possible to force sync~ low when the FPGA is the receiver to re-request sync. Subclass 1. The receiver should request sync a number of frame clock cycles following the rising edge of SYSREF. It also possible to force sync~ low when the FPGA is the receiver to re-request sync. 1.1 Check K28.5 transmitted by transmitter in response to sync request. 1.2 Check ILA or Data follows K28.5 when sync~ goes high. 1.3 Check ILA or Data following K28.5 is aligned to frame clock. The receiver was seen to drive SYNC~ low after a reset. K28.5 characters were seen at the receiver in response to a sync request. The ILA was seen after SYNC~ goes high. 2 Initialization Test the link initializes correctly from reset and power on. 2.1 Check Alignment correct at receiver by inspecting sync~ de-assertion. The link was seen to initialize correctly. Alignment was seen to be correct 2.2 Check ILA transmitted and received following K28.5 when ILA supported. Duplicate of 1.2. 2.3 Check data frames transmitted and received following K28.5 when ILA disabled. When ILA is disabled at both side of the link, valid data are still available at the

[Interoperability Report] Rev 0.4 Page 6 of 14 output. 3 Deterministic Latency (Device Subclass 1) Test data is passed across the link with a deterministic latency in respect to SYSREF. 3.1 SYSREF Generation and sampling. The FPGA shall be programmed to output a one-shot and a periodic SYSREF. The converter devices should align their internal LMFC to the rising edge of SYSREF. 3.2 For each frame format supported by the IDT DAC, the IP will be reconfigured. The latency between the data entering the IP and the data output is measured using a scope. 3.3 Minimum Deterministic Latency. The latency will be set to the minimum as described in section 6.3 and measured using a scope. DAC was seen to align LMFC to the incoming periodic SYSREF pulses. Check that total latency is within one DAC clk. Tested with K = 32, LMF = 421, 422, 222, 124 and DAC interpolation ratio of x4, x2, x8 IDT DAC has an offset register to release data to yet another moment than the LMFC bondary. 4 Deterministic Latency (Device Subclass 2) Test data is passed across the link with a deterministic latency in respect to SYNC~ assertion. 4.1 For each frame format supported by the IDT DAC the IP will be reconfigured and the latency between SYNC~ going high and the data output measured via Chipscope on the FPGA. 4.2 Minimum Deterministic Latency. The latency will be set to the minimum as described in section 6.3 and measured via Chipscope. N.A. N.A. Suclass 2 devices not supported by DAC. Suclass 2 devices not supported by DAC. 5 Framing Test the data passes correctly for all framing formats supported by the hardware.

[Interoperability Report] Rev 0.4 Page 7 of 14 5.1 For each frame format supported by the IDT DAC the IP will be reconfigured and the link reestablished and the sample data verified by comparing the analogue data with the expected pattern. Framing format L=4, F=1, K=18 was tested. Framing format L=4, F=2, K=18 was tested. Framing format L=2, F=2, K=18 was tested. Framing format L=1, F= 4, K=18 was tested. Sine wave data checked on signal analyzer. 6 Initial Lane Sync Sequence Test the initial lane sequence is generated and received correctly including correct passing of the JESD204 configuration bytes. 6.1 Check the ILA is generated with the correct frame and multiframe numbers. 6.2 Check the Configuration data bytes are transferred correctly by inspecting register contents. The frame and multi-frame numbers were checked in DAC software. The configuration parameters were read from the DAC via SPI. 7 Data Samples and Control Bits Test the sample data is passed without error. 7.1 Check the analogue data from the DAC matches the pattern generated by the IP test pattern generator. A 1ksample lookup table based pattern generator shall be implemented to stimulate the IP. 7.2 Check the data received by the IP matches the analogue data stimulating the ADC. A repeating data pattern shall be injected into the ADC and captured by the IP using Xilinx Chipscope with a 2ksample window. N.A. Sine wave sent from FPGA with a step size of 1. Data checked on oscilloscope and signal analyzer at DAC. 8 Scrambling Test for correct link operation with scrambling enabled and disabled.

[Interoperability Report] Rev 0.4 Page 8 of 14 8.1 Check for correct data with scrambling disabled. 8.2 Check for correct data with scrambling enabled. 8.3 Check the first few octets following the ILA are correct by using logic analyzer to check early sync option if applicable. 9 Test Patterns Test generation and reception of all test patterns detailed in JESD204B. 9.1 Check PRBS7 9.2 Check PRBS15 9.3 Check PRBS23 9.4 Check PRBS31 9.5 Check Short Transport Layer Test Pattern defined in section 5.1.6.2. 9.6 Check Long Transport Layer Test Pattern defined in section 5.1.6.3 9.7 Check pattern two defined in section 5.3.3.8.2 is transmitted and verified correctly. 9.8 Check pattern three defined in section 5.3.3.8.2 is transmitted and verified correctly. 9.9 Check RPAT/JSPAT pattern defined in section 5.3.3.8.2 is transmitted and verified correctly. N/A N/A Check BER counter inside DAC. Check BER counter inside DAC. Check BER counter inside DAC. Check BER counter inside DAC. Tested for F=1 with scrambler on. Not supported by DAC. Continuous sequence of /K28.5/ is supported. Code group synchronization followed by repetitive alignment sequence is supported. Not applicable. The test patterns are optional and are not supported by the DAC or FPGA core.

[Interoperability Report] Rev 0.4 Page 9 of 14 9.10 Check JTSPAT pattern is transmitted and verified correctly. N/A Not applicable. The test patterns are optional and are not supported by the FPGA core. 10 Supported Line Rates Test correct operation at all rates supported by hardware. 10.1 Check operation at 3.125Gbps line rate. 10.2 Check operation at 6.375Gbps line rate. 10.3 Check operation at 10Gbps line rate. 10.3 Check operation at 12.5Gbps line rate using KC325T-3 device The DAC link was tested at 3.125Gbps. The DAC link was tested at 6.375Gbps. The DAC link was tested at 10Gbps. The DAC link was tested at 12.5Gbps on selected samples. 11 Alignment character replacement Test the correct insertion (Tx) and reinstatement (Rx) of alignment characters during normal data transmission as per 5.3.3.4.2 and 5.3.3.4.3. Check for alignment character insertion using logic analyzer in FPGA. 11.1 Check for alignment character insertion when scrambling disabled and ILA supported. 11.2 Check for alignment character insertion when scrambling disabled and ILA not supported. 11.3 Check for alignment character insertion when scrambling enabled. 11.4 Check when alignment character insertion is disabled and scrambling enabled. 11.5 Check when alignment character insertion is disabled and scrambling disabled. N.A. N.A.

[Interoperability Report] Rev 0.4 Page 10 of 14 Compliance to JESD204B Specification The interoperability tests in the previous section shall cover the items detailed in the table below. Spec section Contents Tested by Interop Notes 1 Scope N/A 2 References N/A 3 Terminology N/A 4 Electrical Partial Electrical interoperability is tested but compliance is not. 4.1 Overview Partial Electrical interoperability is tested but compliance is not. 4.2 Compliance Types Partial Electrical interoperability is tested but compliance is not. AC compliance only. 4.3 Interconnect Partial Electrical interoperability is tested but compliance is not. 4.3.1 Interconnect Insertion Loss Partial Electrical interoperability is tested but compliance is not. 4.4 LV-OIF-SxI5 Data Signals Partial Electrical interoperability is tested but compliance is not. 4.4.1 Compliance verification Partial Electrical interoperability is tested but compliance is not. 4.4.2 Transmitter Spec Partial Electrical interoperability is tested but compliance is not. 4.4.3 Receiver Spec Partial Electrical interoperability is tested but compliance is not. 4.5 LV-OIF-6G-SR Data Signals Partial Electrical interoperability is tested but compliance is not. 4.5.1 Compliance verification Partial Electrical interoperability is tested but compliance is not. 4.5.2 Transmitter Spec Partial Electrical interoperability is tested but compliance is not. 4.5.3 Receiver Spec Partial Electrical interoperability is tested but compliance is not. 4.6 LV-OIF-11G-SR Data Signals No 12.5G testing not carried out 4.6.1 Compliance verification No 12.5G testing not carried out 4.6.2 Transmitter Spec No 12.5G testing not carried out 4.6.3 Receiver Spec No 12.5G testing not carried out 4.7 Device Clock Partial Compliance not tested. 4.8 Frame Clock, and Local Multiframe Clock Partial Frame clock used by FPGA but compliance not tested. 4.9 SYNC Interface Partial SYNC~ signal is used in interop testing but compliance not tested. 4.10 Lane-to-lane Inter-device Sync Interface No Left to user for subclass 0 devices in JESD204B Spec. Not necessary in subclass 1 and 2 devices. Unable to test in interop. 4.11 SYSREF signal Partial SYSREF signal is used in interop testing but compliance not tested. 4.12 Skew Budget No Unable to test in interop. 4.13 Control Interfaces N/A Left to user in JESD204B Spec. Out with scope of interop 5 Data Stream Partial See subsections 5.1 Transport Layer Partial See subsections 5.1.1 Overview N/A 5.1.2 User Data Format for and Partial Multi-lane devices used in interop

[Interoperability Report] Rev 0.4 Page 11 of 14 Independent Lane 5.1.3 User Data Format for Multiple Lanes Partial Only formats supported by IDT DAC shall be tested 5.1.4 Tail Bits No Formats supported by interop hardware do require tail bits. 5.1.5 Idle Mode No Unable to test in interop. 5.1.5.1 General No Unable to test in interop. 5.1.5.2 Dummy Samples No Unable to test in interop. 5.1.6 Test Modes No Additional logic required in FPGA as this function is not included in the IP Core 5.1.6.1 General No Additional logic required in FPGA as this function is not included in the IP Core 5.1.6.2 Short Transport Layer Test Pattern No Additional logic required in FPGA as this function is not included in the IP Core 5.1.6.3 Long Transport Layer Test Pattern No Additional logic required in FPGA as this function is not included in the IP Core 5.2 Scrambling 5.2.1 Polynomial 5.2.2 Bit Order 5.2.3 Scrambler Type 5.2.4 Early Sync Option Only possible if there is a way of inspecting octets from the data stream individually. 5.2.5 Initial State N/A Early Sync implemented so Initial State is irrelevant 5.2.6 Scrambling Disable 5.3 Data Link Layer Partial See subsections 5.3.1 8B10B 5.3.2 Transmission Order 5.3.3 Link Operation Partial See subsections 5.3.3.1 Code Group Sync 5.3.3.2 SYNC~ Signal Combining 5.3.3.3 Initial Frame Sync 5.3.3.4 Frame Alignment monitoring and Correction No Not possible to inject alignment errors 5.3.3.4.1 Alignment Characters 5.3.3.4.2 Character Replacement without Scrambling 5.3.3.4.3 Character Replacement with Scrambling 5.3.3.4.4 Frame Alignment Correction in Rx Partial Not possible to inject alignment errors in FPGA 5.3.3.5 Initial Lane Synchronisation 5.3.3.6 Lane alignment monitoring and correction Partial Not possible to inject alignment errors in FPGA 5.3.3.7 Link re-initialization

[Interoperability Report] Rev 0.4 Page 12 of 14 5.3.3.8 Test Modes 5.3.3.8.1 General 5.3.3.8.2 Test Sequences Partial Only /K28.5/ and lane alignment sequence tests are supported by the IP Core 6 Deterministic Latency Partial See subsections 6.1 Introduction N/A 6.2 No Support for Deterministic Latency (Device subclass 0) Partial Not tested above 6.25Gbps 6.3 Deterministic Latency Using SYSREF (Device subclass 1) Partial Not tested above 6.25Gbps 6.4 Deterministic Latency Using SYNC~ Detection (Device subclass 2) Partial Not tested above 6.25Gbps. See subsections 6.4.1 Principles of SYNC~ Sampling N/A 6.4.1.1 SYNC~ Generation at the RX Device Partial SYNC~ is generated on the RX device clock in the FPGA 6.4.1.2 Adjustment Resolution and Adjustment Clock 6.4.1.3 Detection Resolution at the TX Device Partial SYNC~ is detected on the TX device clock in the FPGA 6.4.1.4 SYNC~ De-assertion and the Detection Interval No The IP Core transmitter aligns its LMFC to SYNC~ sampled on the device clock. 6.4.2 Master and Slave Configurations N/A 6.4.2.1 ADC Master and Slave Configuration N/A 6.4.2.2 DAC Master and Slave Configurations No Additional logic required in FPGA as phase adjustment is not included in the IP Core 6.4.3 Summary of Requirements for Subclass 2 Deterministic Latency N/A 6.5 Interoperability Between JESD204A and JESD204B Devices 7 Receiver Operation Partial See subsections 7.1 Code Group Synchronisation 7.2 Initial Frame Synchronization 7.3 Frame Alignment monitoring and correction Partial Not possible to inject alignment errors in FPGA 7.4 Initial Lane Synchronisation May not be possible to check time to align 7.5 Lane alignment monitoring and correction Partial Not possible to inject alignment errors in FPGA 7.6 Error Handling No Not possible to inject errors 7.6.1 Error Kinds No Not possible to inject errors

[Interoperability Report] Rev 0.4 Page 13 of 14 7.6.2 Data Output on Error No Not possible to inject errors 7.6.3 Errors Requiring reinitialization No Not possible to inject errors 7.6.4 Error Reporting via SYNC interface No Not possible to inject errors 7.6.5 Error Reporting via control interface No Not possible to inject errors 8 Transmitter Operation 8.1 Synchronisation 8.2 Initial Lane Alignment Sequence 8.3 Link Configuration Data and Encoding 8.4 SYNC Signal Decoding 8.5 SYNC~ Detection (Device Subclass 2) Partial Additional logic required in FPGA as phase adjustment is not included in the IP Core 9 Device Classification N/A

[Interoperability Report] Rev 0.4 Page 14 of 14 Document History Revision Date Name Change Details 0.1 3 Aug 2012 N. McKay Initial Draft for review by IDT 0.2 7 Aug 2012 D.Ramsay Minor edits after review. 0.3 30 May 2013 D. Ramsay Add IDT Logo 0.4 22 October 2013 P. Lieutaud Add some extra tests.