Trends in Digital Interfaces for High-Speed ADCs
|
|
- Dwight Whitehead
- 5 years ago
- Views:
Transcription
1 Trends in Digital Interfaces for High-Speed ADCs Robbie Shergill National Semiconductor Corp. INTRODUCTION The analog-to-digital converter is a critical component in many of the most demanding applications in the world today. From cost-sensitive consumer products such as scanners to many types of industrial imaging products to ultra-high speed defense communications, you will find an analog-to-digital converter lurking in there. In many of these applications the A-to-D can be the determining factor in the price-performance tradeoff. Thus, optimization of this component's functionality is very important. The speed-resolution progression of the ADC technology is a well-established trend that goes back decades - back to the early days of the integrated circuits industry. Ever greater sampling rates at all levels of resolution, and greater resolutions at a given sampling rate, are a reality of this technology. At this time, the mainstream, cost-effective ADCs from major manufacturers are achieving performance levels shown in Table 1. These are advertised products that are either in or about to go into full production. Of course, the next generation of these products is already working in our labs as we speak. Sampling Rate (Fs) 8-bit 10-bit 12-bit 14-bit 16-bit Fs >= 1 Gs/s 500Ms/s =< Fs < 1Gs/s 200Ms/s =< Fs <500Ms/s 100Ms/s =< Fs < 200Ms/s 50Ms/s =< Fs < 100Ms/s Table 1: State of commercially available ADCs in late-2004 Recently another trend has made an appearance in this field. Certain applications that run multiple signal paths in parallel have driven the ADC manufacturers to integrate multiple ADC channels in one IC. Medical imaging has been the driving application and
2 12-bit Quad ADCs in the 40Ms/s to 65Ms/s range have been the result (an octal integration in one vendor's case). As a result, the total throughput through a highresolution ADC IC has taken a sudden jump. With a conventional parallel CMOS interface it would mean 48 data signal pins on such a Quad ADC chip - with 4 additional clock signals on top of that. The problem is lot worse on the ASIC or the FPGA end of the interface where an imaging system may be using 64 or 128 such channels. TIME FOR SOME NEW THINKING Until now, the digital data interface has been the most overlooked aspect of an ADC or DAC chip design. The main challenges in converter design have always been in the analog side of the chip. In fact, when the conversion speed became too fast for the standard CMOS parallel interface, as has been the case for the ultra-high-speed 8-bit converters shown in Table 1, we just de-multiplexed the parallel data by a factor of 2 or more and just burned more pins. This approach simply won't work for higher resolutions and in the cases where multiple ADC cores are integrated into one chip. The immediate solution has been to serialize the digital data words in the simplest manner. This means that just the data words are serialized and a serial bit-rate clock and a Frame signal are provided to latch and deserialize the data stream at the receiver end. This is shown in Figure 1. Current spate of 12-bit Quad or Octal ADCs from various vendors follow this scheme - which is often referred to as CDF for Clock-Data-Frame. The benefit is obvious - National's Quad 12-bit 65 Ms/s chip implements the digital interface with just 12 signals instead of the 52 previously mentioned. Interface power consumption is also reduced by close to 2/3. Each serial data channel runs at up to 780 Mbps (65Ms/s x 12) using LVDS differential signaling. N-bit ADC Core N Parallel-to-Serial SDATA Data Word (N bits) SCLK PLL & Timing N x CKs FRAME CKs Figure 1: The Clock-Data-Frame (CDF) Serialization Scheme
3 The CDF scheme works quite well for the ADCs and DACs in the 40 Ms/s to 100 Ms/s range, depending upon the resolution of the converter. The limit of this technique comes from the clock-to-data skew. Current FPGA LVDS I/O technology limits the maximum serial rate of this scheme to about 850 Mbps. Future FPGA technologies may allow this interface to operate up to 1 Gbps. It should also be kept in mind that the width of the interface also limits the maximum speed since the clock-to-data skew is the limiting factor. OPTIONS FOR GOING FASTER Figure 2 shows the magnitude of ADC throughput we have to transfer across this interface and how the problem is getting worse as we go forward. Clearly the CDF scheme will not take us very far. What are the options? Thruput (Gbits/sec) Quad Dual Single 5 3 Progression of Technology 2 1 Approximate Limit of CDF 8-bit 10-bit 12-bit 14-bit 16-bit Resolution (also # parallel data signals) Figure 2: Per-converter throughput requirements of today's high-speed ADCs a) Extend CDF: This is the simplest next step. Just as with ultra-high speed 8-bit converters we demux the parallel data bus, we could employ 2, or even 3, serial data streams (lanes) in the CDF scheme. This has the obvious drawback of additional pins and
4 it will also have lower per-signal speed limit than the single-lane scheme due to the greater skew; but it retains the simplicity of implementation. Standard ASIC/FPGA I/Os could still be used - thus giving the system engineer the lowest cost alternative. b) Available SERDES I/Os: Advanced FPGA and ASIC families have SERDES (Serializer-Deserializer) cells available that can operate in the 2.5 to little over Gbps range. These cells were originally developed for communications applications - such as, Ethernet. Recently the basic PLLs and encoders/decoders of these cells have been pressed into other applications as well - such as PCI-Express and Serial-ATA. All of these SERDES cells support the IBM 8B10B code and some support the 64B66B code as well. Because of their wide availability, these SERDES cells are an obvious alternative that must be considered. c) Other SERDES methods: Other SERDES schemes are also possible that would give a simpler, more optimal solution than the Comm-type SERDES mentioned above. For example, National has had a serialization solution available for many years that is designed to simply embed the clock and frame in the transmitter and then recover the same with a relatively simpler PLL implementation in the receiver. Figure 3 shows one such implementation. In this case, each 16-bit data word is turned into an 18-bit code word that is serially transmitted on the medium. The 2 added bits cost 12.5% in overhead but they provide a simple, repetitive clock/frame signal for the receiver. N-bit ADC Core N Embed Clock/Frame N+2 Parallel-to-Serial Serial Data (N+2) x CKs PLL & Timing CKs N=16 example Serial Data D0 0 1 D15 D0 0 1 D15 Embedded Clock/Frame Embedded Clock/Frame Figure 3: National's Embedded-Clock/Frame Scheme
5 Another key issue to resolve is that of the electrical interface. Most current CDF implementations have used LVDS. This is because of its proven reliability and wide availability. At least one vendor has used the JEDEC SLVS electrical interface. This is a relatively new specification that is not yet widely adopted. Standard LVDS, as specified by ANSI/EIA/TIA , was originally intended for connection amongst equipment so its maximum transfer rate is determined by the cable length. In a board level application LVDS can approach speeds of 1.5 Gbps. Since the signal strength of the standard LVDS is not necessary for this chip-to-chip application, some of it can be traded for higher speed. However, this would require some level of standardization of such a low-swing, lower-common-mode implementation. The SERDES I/O cells offered by all the FPGA and ASIC vendors use the CML interface. CML is a generic term and not a standard per se. This, along with the fact that CML interface's voltage levels are referenced to the power supply, causes many system implementations to use ac-coupling with CML in order to deal with different common-mode requirements of the transmitter and the receiver. Table 2 compares some key characteristics of these electrical interfaces and Figure 4 shows the interconnect topology. Parameter LVDS SLVS CML* Transmit amplitude (diff. p-p) V 0.8 V nominal V Transmit common-mode voltage ** V 0.2 V nominal V Receive amplitude (diff. p-p) V 0.32 V min V Receive common-mode range ** V V V Medium Cable Not spec'd FR-4 Distance several meters Not spec'd ~ 8" * CML specification based on OIF SXI-5 spec. ** Common-mode voltage defined as ((V+) + (V-)) / 2; except the Receive Common-mode Range for SLVS which is the single-ended voltage range of each signal. Table 2: Key electrical specs of candidate interfaces
6 Vdd-t Vdd-r D+ Tx Zt = 2Zo Rx D- LVDS Vdd-t Vdd-r D+ Tx Rx D- SLVS Vdd-t Vtt Vdd-r D+ Tx Rx D- CML Figure 4: Comparison of interconnect topologies UNIQUE REQUIREMENTS OF THIS APPLICATION In defining a new serial interface for the ADCs and DACs, certain unique requirements of this application must be kept in mind. a) As evident from Figure 2, a wide range of data word widths (converter resolution) and sampling rates must be accommodated.
7 b) High-speed, high-resolution converter chips are highly sensitive to noise. The serial interface, operating at multi-gigabit/sec speeds, can easily add enough noise to materially reduce the converter's dynamic performance specifications. One thing that can reduce the added noise is if the serial interface rate is not allowed to be a fractional multiple of the converter's sampling rate. c) The data stream in many ADC/DAC applications is continuous. The interface must not require control constructs that interrupt the data stream under normal conditions. d) Any self-clocking serial interface will introduce a certain amount of latency variation to the datapath. This is because of the clock recovery and resynchronization that must take place in the receiver. The interface must make provisions for dealing with this latency. WHERE DO WE GO FROM HERE? At this writing, there is an active effort underway to define a standard serial interface for high-speed ADC and DAC interconnects. Almost all major data converter vendors are participating in this effort. A key determinant of success for this group would be to have broad support for its chosen solution from converter as well as ASIC/FPGA vendors. To this end, it is important to leverage the technologies that are already wellsupported. This means that the standard scheme should utilize the 8B10B type SERDES cells that are widely supported by the ASIC and FPGA vendors. Same argument also applies to CML electrical interface. However, it must be recognized that the typical 8B10B SERDES would produce a relatively inefficient solution for this problem. ASIC/FPGA SERDES cells were originally developed for communication applications where the data is packetized and carried over a constant frequency interconnect. Trying to fit the multitude of converter resolution and speed combinations into an 8B10B-coded stream would yield high overhead for many of those combinations. This, of course, would lead to higher power and noise - two things the converter designers want the least. The simpler embeddedcontrol/frame SERDES would yield a more efficient solution. But this option presents a greater standardization challenge. No matter how the SERDES-based standardization proceeds, the de-facto CDF and its multi-lane variant scheme will also live on because in many cases they will provide the system designer with the lowest-cost solution. In conclusion, system designers utilizing high-speed, high-resolution data converters should expect to start working with serial interfaces in the near future.
Technical Article MS-2442
Technical Article MS-2442. JESD204B vs. Serial LVDS Interface Considerations for Wideband Data Converter Applications by George Diniz, Product Line Manager, Analog Devices, Inc. Some key end-system applications
More informationECE 485/585 Microprocessor System Design
Microprocessor System Design Lecture 16: PCI Bus Serial Buses Zeshan Chishti Electrical and Computer Engineering Dept. Maseeh College of Engineering and Computer Science Source: Lecture based on materials
More informationDesignCon SerDes Architectures and Applications. Dave Lewis, National Semiconductor Corporation
DesignCon 2004 SerDes Architectures and Applications Dave Lewis, National Semiconductor Corporation Abstract When most system designers look at serializer/deserializer (SerDes) devices, they often compare
More informationWhite Paper. ORSPI4 Field-Programmable System-on-a-Chip Solves Design Challenges for 10 Gbps Line Cards
White Paper ORSPI4 Field-Programmable System-on-a-Chip Solves Design Challenges for 10 Gbps Line Cards Sidhartha Mohanty and Fred Koons Lattice Semiconductor Corporation October 2003 Bringing the Best
More informationTechnical Article MS-2503
Technical Article MS-2503. Slay Your System Dragons with JESD204B by Ian Beavers, Applications Engineer, Analog Devices, Inc. The JESD204B serial data link interface was developed to support the growing
More informationSolving Today s Interface Challenge With Ultra-Low-Density FPGA Bridging Solutions
Solving Today s Interface Challenges With Ultra-Low- Density FPGA Bridging Solutions August 2013 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 www.latticesemi.com
More informationASNT1011A-KMA DC-to-17Gbps Digital Multiplexer 16:1 / Serializer
ASNT1011A-KMA DC-to-17Gbps Digital Multiplexer 16:1 / Serializer Broadband digital serializer 16 to 1 operating seamlessly from DC to 17Gbps LVDS compliant input data buffers Full-rate clock output Clock
More informationScalable Low-Voltage Signaling with LatticeSC/M Devices
Scalable LowVoltage Signaling July 2011 Application Note AN8085 Introduction Differential signaling has become increasingly popular in network and telecommunications markets for a number of reasons. It
More informationLVDS applications, testing, and performance evaluation expand.
Stephen Kempainen, National Semiconductor Low Voltage Differential Signaling (LVDS), Part 2 LVDS applications, testing, and performance evaluation expand. Buses and Backplanes D Multi-drop D LVDS is a
More informationASNT1011-KMA DC-to-17Gbps Digital Multiplexer 16:1 / Serializer
ASNT1011-KMA DC-to-17Gbps Digital Multiplexer 16:1 / Serializer Broadband digital serializer 16 to 1 LVDS compliant input data buffers Full-rate clock output Clock-divided-by-16 LVDS output buffer with
More informationASNT Gbps 1:16 Digital Deserializer
12.5Gbps 1:16 Digital Deserializer Broadband up to 12.5Gbps (gigabits per second) 1:16 Deserializer High-speed Input Data Buffer with on-chip 100Ohm differential termination. Full-rate CML Input Clock
More informationASNT1016-PQA 16:1 MUX-CMU
16:1 MUX-CMU 16 to 1 multiplexer (MUX) with integrated CMU (clock multiplication unit). PLL-based architecture featuring both counter and forward clocking modes. Supports multiple data rates in the 9.8-12.5Gb/s
More informationMANAGING IMAGE DATA IN AUTOMOTIVE INFOTAINMENT APPLICATIONS USING LOW COST PLDS
MANAGING IMAGE DATA IN AUTOMOTIVE INFOTAINMENT APPLICATIONS USING LOW COST PLDS August 2011 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 www.latticesemi.com
More informationAdapter Modules for FlexRIO
Adapter Modules for FlexRIO Ravichandran Raghavan Technical Marketing Engineer National Instruments FlexRIO LabVIEW FPGA-Enabled Instrumentation 2 NI FlexRIO System Architecture PXI/PXIe NI FlexRIO Adapter
More informationASNT1011-KMA DC-to-17Gbps Digital Multiplexer / Serializer 16:1or 8:1
ASNT1011-KMA DC-to-17Gbps Digital Multiplexer / Serializer 16:1or 8:1 Broadband programmable digital serializer 16-to-1 or 8-to-1 LVDS compliant input data buffers Full-rate clock output Selectable LVDS-compliant
More informationHardware Design with VHDL PLDs IV ECE 443
Embedded Processor Cores (Hard and Soft) Electronic design can be realized in hardware (logic gates/registers) or software (instructions executed on a microprocessor). The trade-off is determined by how
More informationSerializer Deserializer POSSIBILITIES OF COMMUNICATION. MADE EASY. For extremely high communications reliability in radiation environments
Serializer Deserializer POSSIBILITIES OF COMMUNICATION. MADE EASY. For extremely high communications reliability in radiation environments Serializer Deserializer Industry challenges The industry continues
More informationAdvanced Computing, Memory and Networking Solutions for Space
Advanced Computing, Memory and Networking Solutions for Space 25 th Microelectronics Workshop November 2012 µp, Networking Solutions and Memories Microprocessor building on current LEON 3FT offerings UT699E:
More informationImplementing LVDS in Cyclone Devices
Implementing LVDS in Cyclone Devices March 2003, ver. 1.1 Application Note 254 Introduction Preliminary Information From high-speed backplane applications to high-end switch boxes, LVDS is the technology
More informationRHiNET-3/SW: an 80-Gbit/s high-speed network switch for distributed parallel computing
RHiNET-3/SW: an 0-Gbit/s high-speed network switch for distributed parallel computing S. Nishimura 1, T. Kudoh 2, H. Nishi 2, J. Yamamoto 2, R. Ueno 3, K. Harasawa 4, S. Fukuda 4, Y. Shikichi 4, S. Akutsu
More informationOIF CEI-56G Project Activity
OIF CEI-56G Project Activity Progress and Challenges for Next Generation 400G Electrical Links David R Stauffer Kandou Bus, SA OIF Physical & Link Layer Working Group Chair June 12, 2014 Electrical Implementation
More informationUsing Chiplets to Lower Package Loss. IEEE Gb/s Electrical Lane Study Group February 26, 2018 Brian Holden, VP of Standards Kandou Bus SA
1 Using Chiplets to Lower Package Loss IEEE 802.3 100 Gb/s Electrical Lane Study Group February 26, 2018 Brian Holden, VP of Standards Kandou Bus SA Chiplet Technology Big, 70mm packages are routine A
More informationASNT2011-KMA DC-to-17Gbps Digital Demultiplexer 1:16 / Deserializer
ASNT2011-KMA DC-to-17Gbps Digital Demultiplexer 1:16 / Deserializer Broadband digital deserializer 1:16 operating seamlessly from DC to 17Gbps. LVDS output data buffers that feature a low-power proprietary
More informationClock Tree Design Considerations
Tree Design Considerations Hardware design in high performance applications such as communications, wireless infrastructure, servers, broadcast video and test and measurement is becoming increasingly complex
More informationOptimal Management of System Clock Networks
Optimal Management of System Networks 2002 Introduction System Management Is More Challenging No Longer One Synchronous per System or Card Must Design Source-Synchronous or CDR Interfaces with Multiple
More informationIn-chip and Inter-chip Interconnections and data transportations for Future MPAR Digital Receiving System
In-chip and Inter-chip Interconnections and data transportations for Future MPAR Digital Receiving System A presentation for LMCO-MPAR project 2007 briefing Dr. Yan Zhang School of Electrical and Computer
More informationVIDEO BRIDGING SOLUTION PROMISES NEW LEVEL OF DESIGN FLEXIBILITY AND INNOVATION
VIDEO BRIDGING SOLUTION PROMISES NEW LEVEL OF DESIGN FLEXIBILITY AND INNOVATION May 2016 Lattice Semiconductor 111 5 th Ave., Suite 700 Portland, Oregon 97204 USA Telephone: (503) 268-8000 www.latticesemi.com
More information8. Selectable I/O Standards in Arria GX Devices
8. Selectable I/O Standards in Arria GX Devices AGX52008-1.2 Introduction This chapter provides guidelines for using industry I/O standards in Arria GX devices, including: I/O features I/O standards External
More informationDIGITAL SYSTEM. Technology Overview Nordco. All rights reserved. Rev C
DIGITAL SYSTEM Technology Overview Rev C 01-05-2016 Insert Full Frame Product Picture Here 2015 KEY FEATURES DIGITAL PROCESSING SYSTEM FOR INDUSTRIAL & TONNE UE SYSTEM DIGITAL PROCESSING SYSTEM FOR MICRO
More informationBuses. Disks PCI RDRAM RDRAM LAN. Some slides adapted from lecture by David Culler. Pentium 4 Processor. Memory Controller Hub.
es > 100 MB/sec Pentium 4 Processor L1 and L2 caches Some slides adapted from lecture by David Culler 3.2 GB/sec Display Memory Controller Hub RDRAM RDRAM Dual Ultra ATA/100 24 Mbit/sec Disks LAN I/O Controller
More informationJESD204B Xilinx/IDT DAC1658D-53D interoperability Report
[Interoperability Report] Rev 0.4 Page 1 of 14 JESD204B Xilinx/IDT DAC1658D-53D interoperability Report [Interoperability Report] Rev 0.4 Page 2 of 14 CONTENTS INTRODUCTION... 3 SCOPE... 3 HARDWARE...
More informationOne Technology Way P.O. Box 9106 Norwood, MA Tel: Fax:
One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 Tel: 781.329.4700 Fax: 781.461.3113 www.analog.com DPG3 The DPG3, or Data Pattern Generator 3, is a device designed to support the evaluation of
More informationIntel MAX 10 High-Speed LVDS I/O User Guide
Intel MAX 10 High-Speed LVDS I/O User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel MAX 10 High-Speed LVDS
More informationUnderstanding JESD204B High-speed inter-device data transfers for SDR
Understanding JESD204B High-speed inter-device data transfers for SDR Lars-Peter Clausen Introduction JESD204 Standard Designed as high-speed serial data link between converter (ADC, DAC) and logic device
More informationImplementing RapidIO. Travis Scheckel and Sandeep Kumar. Communications Infrastructure Group, Texas Instruments
White Paper Implementing RapidIO Travis Scheckel and Sandeep Kumar Communications Infrastructure Group, Texas Instruments In today s telecommunications market, slow and proprietary is not the direction
More informationUsing Flexible-LVDS Circuitry in Mercury Devices
Using Flexible-LVDS Circuitry in Mercury Devices November 2002, ver. 1.1 Application Note 186 Introduction With the ever increasing demand for high bandwidth and low power consumption in the telecommunications
More information4. Selectable I/O Standards in Stratix II and Stratix II GX Devices
4. Selectable I/O Standards in Stratix II and Stratix II GX Devices SII52004-4.6 Introduction This chapter provides guidelines for using industry I/O standards in Stratix II and Stratix II GX devices,
More informationASNT1011A. ASNT1011A-PQA DC-to-17Gbps Digital Multiplexer 16:1 / Serializer
Advaed Sciee And Novel Technology Company, I. 27 Via Porto Grande, Raho Palos Verdes, CA 90275 ASNT1011A-PQA DC-to-17Gbps Digital Multiplexer 16:1 / Serializer Broadband digital serializer 16-to-1. LVDS
More informationIDT for FPGAs CLOCKS AND TIMING INTERFACE AND CONNECTIVITY MEMORY AND LOGIC POWER MANAGEMENT RF PRODUCTS
IDT for FPGAs CLOCKS AND TIMING INTERFACE AND CONNECTIVITY MEMORY AND LOGIC POWER MANAGEMENT RF PRODUCTS IDT develops a broad range of low-power, high-performance mixed-signal semiconductor solutions that
More informationHOME :: FPGA ENCYCLOPEDIA :: ARCHIVES :: MEDIA KIT :: SUBSCRIBE
Page 1 of 8 HOME :: FPGA ENCYCLOPEDIA :: ARCHIVES :: MEDIA KIT :: SUBSCRIBE FPGA I/O When To Go Serial by Brock J. LaMeres, Agilent Technologies Ads by Google Physical Synthesis Tools Learn How to Solve
More informationWhite Paper Compromises of Using a 10-Gbps Transceiver at Other Data Rates
White Paper Compromises of Using a 10-Gbps Transceiver at Other Data Rates Introduction Many applications and designs are adopting clock data recovery-based (CDR) transceivers for interconnect data transfer.
More informationInnovative DSPLL and MultiSynth Clock Architecture Enables High-Density 10/40/100G Line Card Designs
Innovative and MultiSynth Clock Architecture Enables High-Density 10/40/100G Line Card Designs Introduction The insatiable demand for bandwidth to support applications such as video streaming and cloud
More informationBoard Design Guidelines for PCI Express Architecture
Board Design Guidelines for PCI Express Architecture Cliff Lee Staff Engineer Intel Corporation Member, PCI Express Electrical and Card WGs The facts, techniques and applications presented by the following
More informationUsing IBIS-AMI in the Modeling of Advanced SerDes Equalization for Serial Link Simulation
Using IBIS-AMI in the Modeling of Advanced SerDes Equalization for Serial Link Simulation CDNLive Boston August 2013 Mark Marlett and Mahesh Tirupattur, Analog Bits Ken Willis and Kumar Keshavan, Cadence
More informationRemote Keyless Entry In a Body Controller Unit Application
38 Petr Cholasta Remote Keyless Entry In a Body Controller Unit Application Many of us know this situation. When we leave the car, with a single click of a remote control we lock and secure it until we
More informationASNT2032-MBL Digital DMUX 12-to-24 with LVDS Interfaces
-MBL Digital DMUX 12-to-24 with LVDS Interfaces Digital demultiplexer (DMUX) 12-to-24 with LVDS output interface Programmable LVDS/CML/ECL input interface Supports data rates from 1.0Mbps to 3.6Gbps Preset
More informationASNT7120-KMA 10GS/s, 4-bit Flash Analog-to-Digital Converter
10GS/s, 4-bit Flash Analog-to-Digital Converter 18GHz analog input bandwidth. Selectable clocking mode: external high-speed clock or internal PLL with external lowspeed reference clock. Broadband operation
More informationSection 3 - Backplane Architecture Backplane Designer s Guide
Section 3 - Backplane Architecture Backplane Designer s Guide March 2002 Revised March 2002 The primary criteria for backplane design are low cost, high speed, and high reliability. To attain these often-conflicting
More informationHigh-speed Serial Interface
High-speed Serial Interface Lect. 8 SERES 1 High-Speed Circuits and Systems Lab., Yonsei University 2013-1 Block diagram Where are we today? Serializer Tx river Channel Rx Equalizer Sampler eserializer
More informationApplication Note: Optical data transmission with the Avocet Image Sensor
: Optical data transmission with the Avocet Image Sensor This application note presents a reference design for using optical data transmissions with the MLX75411 Avocet image sensor. The MLX75605 optical
More informationUT90nSDTC-EVB, Gbps Quad-lane SerDes Macro Evaluation Board Data Sheet February 2014
Semicustom Products UT90nSDTC-EVB, 3.125 Gbps Quad-lane SerDes Macro Evaluation Board Data Sheet February 2014 www.aeroflex.com/radhardasic FEATURES Aeroflex UT90nHBD 3.125 Gbps SerDes Macro transceiver,
More informationASNT1011. ASNT1011-PQA DC-to-16Gbps Digital Multiplexer 16:1 / Serializer
Advaed Sciee And Novel Technology Company, I. 27 Via Porto Grande, Raho Palos Verdes, CA 90275 ASNT1011-PQA DC-to-16Gbps Digital Multiplexer 16:1 / Serializer Broadband digital serializer 16-to-1. LVDS
More informationPSEC-4: Review of Architecture, etc. Eric Oberla 27-oct-2012
PSEC-4: Review of Architecture, etc. Eric Oberla 27-oct-2012 PSEC-4 ASIC: design specs LAPPD Collaboration Designed to sample & digitize fast pulses (MCPs): Sampling rate capability > 10GSa/s Analog bandwidth
More informationPART. *EP = Exposed pad. LVDS IN+ IN- PCB OR TWISTED PAIR. Maxim Integrated Products 1
19-0849; Rev 1; 12/07 10-Bit LVDS Serializer General Description The serializer transforms 10-bit-wide parallel LVCMOS/LVTTL data into a serial high-speed, low-voltage differential signaling (LVDS) data
More informationLatticeSCM SPI4.2 Interoperability with PMC-Sierra PM3388
August 2006 Technical Note TN1121 Introduction The System Packet Interface, Level 4, Phase 2 (SPI4.2) is a system level interface, published in 2001 by the Optical Internetworking Forum (OIF), for packet
More informationSERIAL MULTI-PROTOCOL TRANSMISSION WITH THE LatticeSC FPGA
SERIAL MULTI-PROTOCOL TRANSMISSION WITH THE LatticeSC FPGA February 2006 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 www.latticesemi.com 1 Serial
More informationQ Pairs QTE/QSE-DP Final Inch Designs In PCI Express Applications 16 mm Stack Height
Application Note Q Pairs QTE/QSE-DP Final Inch Designs In PCI Express Applications 16 mm Stack Height Copyrights and Trademarks Copyright 2004 Samtec, Inc. Developed in conjunction with Teraspeed Consulting
More informationIntroduction Electrical Considerations Data Transfer Synchronization Bus Arbitration VME Bus Local Buses PCI Bus PCI Bus Variants Serial Buses
Introduction Electrical Considerations Data Transfer Synchronization Bus Arbitration VME Bus Local Buses PCI Bus PCI Bus Variants Serial Buses 1 Most of the integrated I/O subsystems are connected to the
More informationTECHNOLOGY BRIEF. Double Data Rate SDRAM: Fast Performance at an Economical Price EXECUTIVE SUMMARY C ONTENTS
TECHNOLOGY BRIEF June 2002 Compaq Computer Corporation Prepared by ISS Technology Communications C ONTENTS Executive Summary 1 Notice 2 Introduction 3 SDRAM Operation 3 How CAS Latency Affects System Performance
More informationULTRA2 SCSI WHITE PAPER
1.0 The Advantages of Parallel SCSI 2.0 The Evolution of Parallel SCSI 3.0 Differential Signaling 4.0 Low-Voltage Differential (LVD) SCSI 5.0 Multi-Mode Devices 6.0 LVD Physical Configuation 7.0 Conclusion
More informationHigh Performance Embedded Applications. Raja Pillai Applications Engineering Specialist
High Performance Embedded Applications Raja Pillai Applications Engineering Specialist Agenda What is High Performance Embedded? NI s History in HPE FlexRIO Overview System architecture Adapter modules
More information4. Selectable I/O Standards in Stratix & Stratix GX Devices
4. Selectable I/O Standards in Stratix & Stratix GX Devices S52004-3.4 Introduction The proliferation of I/O standards and the need for higher I/O performance have made it critical that devices have flexible
More informationIGLOO2 Evaluation Kit Webinar
Power Matters. IGLOO2 Evaluation Kit Webinar Jamie Freed jamie.freed@microsemi.com August 29, 2013 Overview M2GL010T- FG484 $99* LPDDR 10/100/1G Ethernet SERDES SMAs USB UART Available Demos Small Form
More information802.3bj FEC Overview and Status. 1x400G vs 4x100G FEC Implications DRAFT. IEEE P802.3bs 400 Gb/s Ethernet Task Force. Bill Wilkie Xilinx
802.3bj FEC Overview and Status 1x400G vs 4x100G FEC Implications DRAFT IEEE P802.3bs 400 Gb/s Ethernet Task Force July 2015 Hawaii Bill Wilkie Xilinx Introduction This presentation takes a look at the
More informationLatticeSC/M Family flexipcs Data Sheet. DS1005 Version 02.0, June 2011
DS1005 Version 02.0, June 2011 Table of Contents June 2011 Introduction to flexipcs... 1-1 flexipcs Features... 1-1 flexipcs Introduction... 1-2 Architecture Overview... 1-2 flexipcs Quad... 1-2 flexipcs
More informationRiseUp RU8-DP-DV Series 19mm Stack Height Final Inch Designs in PCI Express Applications. Revision Date: March 18, 2005
RiseUp RU8-DP-DV Series 19mm Stack Height Final Inch Designs in PCI Express Applications Revision Date: March 18, 2005 Copyrights and Trademarks Copyright 2005 Samtec, Inc. Developed in conjunction with
More informationECE 485/585 Microprocessor System Design
Microprocessor System Design Lecture 17: Serial Buses USB Disks and other I/O Zeshan Chishti Electrical and Computer Engineering Dept. Maseeh College of Engineering and Computer Science Source: Lecture
More informationArria 10 Transceiver PHY User Guide
Arria 10 Transceiver PHY User Guide Subscribe UG-A10XCVR 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Arria 10 Transceiver PHY User Guide Contents Arria 10 Transceiver PHY Overview...1-1
More informationfor Image Applications
This article presents general information on the LVDS interface hard macro for image applications. * LVDS: Low Voltage Differential Signaling Necessity for High-speed Signal Transmission in Consumer Products
More informationTotal IP Solution for Mobile Storage UFS & NAND Controllers
Total IP Solution for Mobile Storage UFS & NAND Controllers Yuping Chung Arasan Chip Systems San Jose, CA Mobile Forum Taiwan & Korea 2012 Fast Growing NAND Storage Markets GB(M) 15 10 5 Mobile SSD Tablet
More informationPI6C GND REF_IN+ V TH V REF-AC REF_IN- Q0+ Q0- Q1+ Q1- VDD. 6 GHz / 12 Gbps Clock / Data Fanout Buffer with Internal Termination.
Features ÎÎInput Clock Frequency up to 6 GHz Typical ÎÎMaximum Input Data Rate up to 12 Gbps Typical ÎÎ2 pairs of differential CML outputs ÎÎLow additive jitter, < 0.05ps (max) ÎÎInput accepts: CML, LVDS,
More informationChallenges for Future Interconnection Networks Hot Interconnects Panel August 24, Dennis Abts Sr. Principal Engineer
Challenges for Future Interconnection Networks Hot Interconnects Panel August 24, 2006 Sr. Principal Engineer Panel Questions How do we build scalable networks that balance power, reliability and performance
More informationLatticeSC flexipcs/serdes Design Guide
October 2008 Introduction Technical Note TN1145 This document has been provided to assist the designer in using the flexipcs /SERDES block in the LatticeSC FPGA. The LatticeSC/M Family flexipcs Data Sheet
More informationAltera Product Overview. Altera Product Overview
Altera Product Overview Tim Colleran Vice President, Product Marketing Altera Product Overview High Density + High Bandwidth I/O Programmable ASSP with CDR High-Speed Product Term Embedded Processor High
More informationTF10CP02 / TF10CP Gbps 2x2 LVDS Crosspoint Switches. Features. Description. Applications. Function Diagram. Ordering Information.
Features DC to 1.5 Gbps low jitter, low skew, low power operation Pin configurable, fully differential, non-blocking architecture eases system design and PCB layout On-chip 100W input termination minimizes
More informationSupporting Advanced-Node FinFET SoCs with 16Gbps Multi-Protocol SerDes PHY IP
Supporting Advanced-Node FinFET SoCs with 16Gbps Multi-Protocol IP By William Chen and Osman Javed, Cadence Design Systems Applications such as the Internet of Things, cloud computing, and high-definition
More informationSAE AS5643 and IEEE1394 Deliver Flexible Deterministic Solution for Aerospace and Defense Applications
SAE AS5643 and IEEE1394 Deliver Flexible Deterministic Solution for Aerospace and Defense Applications Richard Mourn, Dap USA Inc. AS5643 coupled with IEEE-1394 Asynchronous Stream capability provides
More informationTermination Options for Any-Frequency Si51x XOs, VCXOs
Termination Options for Any-Frequency XOs, VCXOs 1. Introduction This application note provides termination recommendations for connecting output clock signals to the family of XO and VCXO ICs and is not
More informationLecture 5: Computing Platforms. Asbjørn Djupdal ARM Norway, IDI NTNU 2013 TDT
1 Lecture 5: Computing Platforms Asbjørn Djupdal ARM Norway, IDI NTNU 2013 2 Lecture overview Bus based systems Timing diagrams Bus protocols Various busses Basic I/O devices RAM Custom logic FPGA Debug
More informationMilitary Grade SmartFusion Customizable System-on-Chip (csoc)
Military Grade SmartFusion Customizable System-on-Chip (csoc) Product Benefits 100% Military Temperature Tested and Qualified from 55 C to 125 C Not Susceptible to Neutron-Induced Configuration Loss Microcontroller
More informationPCI EXPRESS TECHNOLOGY. Jim Brewer, Dell Business and Technology Development Joe Sekel, Dell Server Architecture and Technology
WHITE PAPER February 2004 PCI EXPRESS TECHNOLOGY Jim Brewer, Dell Business and Technology Development Joe Sekel, Dell Server Architecture and Technology Formerly known as 3GIO, PCI Express is the open
More informationSigmaRAM Echo Clocks
SigmaRAM Echo s AN002 Introduction High speed, high throughput cell processing applications require fast access to data. As clock rates increase, the amount of time available to access and register data
More informationWhite Paper The Need for a High-Bandwidth Memory Architecture in Programmable Logic Devices
Introduction White Paper The Need for a High-Bandwidth Memory Architecture in Programmable Logic Devices One of the challenges faced by engineers designing communications equipment is that memory devices
More informationReduce Your System Power Consumption with Altera FPGAs Altera Corporation Public
Reduce Your System Power Consumption with Altera FPGAs Agenda Benefits of lower power in systems Stratix III power technology Cyclone III power Quartus II power optimization and estimation tools Summary
More informationMULTIPLEXER / DEMULTIPLEXER IMPLEMENTATION USING A CCSDS FORMAT
MULTIPLEXER / DEMULTIPLEXER IMPLEMENTATION USING A CCSDS FORMAT Item Type text; Proceedings Authors Grebe, David L. Publisher International Foundation for Telemetering Journal International Telemetering
More informationZL40218 Precision 1:8 LVDS Fanout Buffer
Precision 1:8 LVDS Fanout Buffer Data Sheet Features Inputs/Outputs Accepts differential or single-ended input LVPECL, LVDS, CML, HCSL, LVCMOS Eight precision LVDS outputs Operating frequency up to 750
More information250 Mbps Transceiver in LC FB2M5LVR
250 Mbps Transceiver in LC FB2M5LVR DATA SHEET 650 nm 250 Mbps Fiber Optic Transceiver with LC Termination LVDS I/O IEC 61754-20 Compliant FEATURES LC click lock mechanism for confident connections Compatible
More informationSERIAL I/O PRODUCTS SEALEVEL I/O FAMILY NEW PRODUCT. RS-422/485 Serial I/O. RS-422/485 Specification
SEALEVEL I/O FAMILY RS-422/485 Serial I/O RS-422/485 Specification The RS-422 electrical specification allows very long distance (4000 ft. at 9600 bps) communications with virtually error free differential
More informationSFP-GIG-T-LEG. 1.25Gbps SFP Copper Transceiver
Part# 39665 SFP-GIG-T-LEG ALCATEL-LUCENT COMPATIBLE 1000BASE-TX SFP COPPER 100M REACH RJ-45 SFP-GIG-T-LEG 1.25Gbps SFP Copper Transceiver Features Up to 1.25Gb/s bi-directional data links Hot-pluggable
More informationSV3C DPRX MIPI D-PHY Analyzer. Data Sheet
SV3C DPRX MIPI D-PHY Analyzer Data Sheet Table of Contents Table of Contents Table of Contents... 1 List of Figures... 2 List of Tables... 2 Introduction... 3 Overview... 3 Key Benefits... 3 Applications...
More informationIntroduction to PCI Express Positioning Information
Introduction to PCI Express Positioning Information Main PCI Express is the latest development in PCI to support adapters and devices. The technology is aimed at multiple market segments, meaning that
More informationArria V GX Video Development System
Arria V GX Video Development System Like Sign Up to see what your friends like. The Arria V GX FPGA Video Development System is an ideal video processing platform for high-performance, cost-effective video
More informationWireless Infrastructure Solutions to Enhance the Digital Media Experience
WIRELESS INFRASTRUCTURE SOLUTIONS Wireless Infrastructure Solutions to Enhance the Digital Media Experience IDT ADDRESSES NEXT GENERATION WIRELESS BY ACCELERATING THE DATA PATH AND OFFLOADING FUNDAMENTAL
More informationAchieving UFS Host Throughput For System Performance
Achieving UFS Host Throughput For System Performance Yifei-Liu CAE Manager, Synopsys Mobile Forum 2013 Copyright 2013 Synopsys Agenda UFS Throughput Considerations to Meet Performance Objectives UFS Host
More information8. Migrating Stratix II Device Resources to HardCopy II Devices
8. Migrating Stratix II Device Resources to HardCopy II Devices H51024-1.3 Introduction Altera HardCopy II devices and Stratix II devices are both manufactured on a 1.2-V, 90-nm process technology and
More informationPrototyping NGC. First Light. PICNIC Array Image of ESO Messenger Front Page
Prototyping NGC First Light PICNIC Array Image of ESO Messenger Front Page Introduction and Key Points Constructed is a modular system with : A Back-End as 64 Bit PCI Master/Slave Interface A basic Front-end
More informationPXI Tsunami in Semiconductor ATE Michael Dewey Geotest Marvin Test Systems Silicon Valley Test Conference
PXI Tsunami in Semiconductor ATE Michael Dewey Geotest Marvin Test Systems miked@geotestinc.com Silicon Valley Test Conference 2012 1 Agenda Geotest background Semiconductor market and trends PXI for semiconductor
More informationfleximac A MICROSEQUENCER FOR FLEXIBLE PROTOCOL PROCESSING
fleximac A MICROSEQUENCER FOR FLEXIBLE PROTOCOL PROCESSING A Lattice Semiconductor White Paper February 2006 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503)
More informationQPairs QTE/QSE-DP Multi-connector Stack Designs In PCI Express Applications 16 mm Connector Stack Height REVISION DATE: OCTOBER 13, 2004
Application Note QPairs QTE/QSE-DP Multi-connector Stack Designs In PCI Express Applications 16 mm Connector Stack Height REVISION DATE: OCTOBER 13, 2004 Copyrights and Trademarks Copyright 2004 Samtec,
More information89HPES4T4[3T3]QFN Hardware Design Guide
89HPES4T4[3T3]QFN Hardware Design Guide Notes Introduction This document provides general guidelines to help design IDT s 89 PCI Express 4-port switch () and also applies to the PES3T3QFN. This document
More information