Introduction to Design Vision Instructor: Prof. Shantanu Dutt TA: Soumya Banerjee We use Synopsys Design Vision for synthesizing the VHDL descriptions. If you are aware in the show schematic option in VCS-MX (our GUI for simulation), it shows you different processes, architectures, and connection. If you want to see what they actually do, you will be redirected to the corresponding VHDL description of the architectures. You can t see any gates and hardware components, like AND, OR, NOT, MUX etc. To see those components, we need to use a much more powerful design synthesis tool, like Design Vision. 1. How to access Design Vision? In the command window, just type design_analyzer. You may get many errors. After that, Design Analyzer window will open. 2. How to work with Design Vision? You can see the at the bottom of the window, there is one statement design_vision>. You can enter different commands to the right. You have to insert different libraries now. Right beside design_vision>, type 1. set target_library [list lsi_10k.db], then press enter 2. set symbol_library [list lsi_10k.sdb], then press enter
3. set link_library [list * lsi_10k.db], press enter Everytime you start Design Vision, you need to enter these lines. Next, go to file and select Analyze. When the new window opens, click on Add Add all the vhdl files that you would like to compile, click ok. If work library menu is not work, rename it work. Then check on create new library if it doesn t exist. However, it is always recommended to create a work directory under the current directory where you stored your VHDL file and move your VHDL file to the work directory. You will see something like this. Click OK, the designs will be compiled. Then the design has to be elaborated. For this, go to File, then Elaborate. Inside the library WORK, select the top level in the hierarchy of your design. If your design is okay, you ll see the design opening on the left hand side of the screen. Right click on the top-level entity and select schematic view. You ll see the corresponding schematic.
Click on the rectangular blocks to see the contents of the block. If the block is actually a part of the library (such as a Multiplexer), you will not be able to see the contents. Design Example : 1. In the first lab, we had to test different design styles. One of them was an XOR gate given in behavioral description named ckt1.vhd. The code is given below, Library IEEE; use IEEE.STD_LOGIC_1164.all; entity ckt1 is port(s1,s2:in bit; Z:out bit); end entity ckt1; architecture behav of ckt1 is Z <= '1' when (s1='0' and s2='1') or
(s1='1' and s2='0') else '0' ; end architecture behav; After analyzing and compiling this code in the same way as described above, you should be able to see the following circuit. 2. You are to design a Parity Checker Moore FSM with two inputs: RST : Reset; X : Serial Input; The FSM checks the parity of the last bitstream since it received an RST. The circuit can be designed using this state diagram:
0 RST 1 Even [0] Odd [1] 0 1 The corresponding code: Library IEEE; use IEEE.STD_LOGIC_1164.all; Entity FSM is port(x: in std_logic; RST : in std_logic; clk : in std_logic; Y : out std_logic); end FSM; architecture behav of FSM is type state is (A, B); signal curr, nxt : state; process FF(clk, RST) if (RST = '1') then curr <= A; elsif(rising_edge(clk) then curr <= nxt; end if; end process FF; process ouput(curr) case curr is when A => y <= '0'; when B => y <= 1 ; end case; end process output; process state_transition(curr, X, RST) case curr is when A => if(x='1') then nxt <= B; else nxt <= A; end if;
when B => if(x='1') then nxt <= A; else nxt <= B; end if; end case; end process state_transition; end architecture behav; Follow the above steps to synthesize the attached code fsm.vhdl. You should be able to see the following circuit getting synthesized. You will see that the design contains 4 MUXes, 2 D Flip-Flops, 1 NOT gate, 2 buffers. The two states are encoded by 1 and 0. Recall that, in a behavioral description, for if.. then else statement, a cascade of MUXes is synthesized. The D Flip Flops are used for state storage. Try setting RST = 1, you will see that X is inputted to the first D flip flop as enable. If X = 1, the inverted value of the current state comes to the input of the first D Flip Flop and the output feeds the second D flip flop. The 1st D FF is unclocked and acts essentially as a transparent latch controlled by X. When X= 1, the first Flip Flop is enabled, and the inverted state A is input to the same. In the next clock cycle, the second Flip Flop updates the current state with the new one. When X = 0, the first Flip Flop is disabled, as a result, the second Flip Flop continues to store the previous state. The final MUX is used to compute the final output.
Note that you can t see the contents of the MUXes and the Flip Flops, because they are components taken from the library.