Luleå University of Technology Kurskod SMD098 Datum Skrivtid

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1 Luleå University of Technology Kurskod SMD098 Datum Skrivtid Tentamen i Beräkningstrukturer Antal uppgifter: 6 Max poäng: 35 Lärare: Jonas Thor Telefon: 2549 Tillåtna hjälpmedel: Enbart skrivmaterial. En syntax guide till VHDL hittas längst bak i tentamen Allowed material Only writing material. There is a VHDL syntax guide at the end of the exam Note: The exam is can give a total of 35 points. This means that if you completed Lab 3.1 part 2 you will get a 3.5 p bonus instead of 3 points. Questions may be answered in English or Swedish. Good luck and Merry Christmas!

2 1 Manual synthesis (7.5 p, 1.5 p each) Here you are given five different VHDL models. Your task is to draw the schematics of the VHDL models. Your schematics may only contain: AND gates with n inputs ( n 2) OR gates with n inputs XOR gates with n inputs Inverters Multiplexers Tri-state buffers Positive edge triggered D-type flip-flops, with or without synchronous or asynchronous clear or set. The flip-flops may also have a clock enable input (CE). Transparent data latches Clearly mark the names of the inputs/outputs as indicated in the VHDL source. a) library ieee; entity One_a is port ( Clk : in std_logic; A, B, C : in std_logic; Y1, Y2 : out std_logic); end One_a; architecture RTL of One_a is signal I1, I2 : std_logic; process(clk) if rising_edge(clk) then if C = '1' then Y1 <= I2; I2 <= I1; I1 <= not (A and B); Y2 <= I1 xor I2; end process; end RTL; 2

3 b) library ieee; entity One_b is port ( Clk : in std_logic; A, B, C : in std_logic; Y1, Y2 : out std_logic); end One_b; architecture RTL of One_b is process(clk) variable V1, V2 : std_logic; if rising_edge(clk) then V1 := A and B; if C = '1' then V2 := V1; Y1 <= V2; Y2 <= V1 xor V2; end process; end RTL; 3

4 c) library ieee; entity One_c is port ( Clk, Reset : in std_logic; Input : in std_logic; Output : out std_logic); end One_c; architecture RTL of One_c is type State is (S0, S1); signal PState, NState : State; process(clk, Reset) if Reset = '1' then PState <= S0; elsif rising_edge(clk) then PState <= NState; end process; process(pstate, Input) case PState is when S0 => Output <= '0'; if Input = '1' then NState <= S1; else NState <= S0; when S1 => Output <= '1'; if Input = '0' then NState <= S0; else NState <= S1; end case; end process; end RTL; 4

5 d) library ieee; entity One_d is port ( Clk : in std_logic; We, Re : in std_logic; D : inout std_logic); end One_d; architecture RTL of One_d is signal R : std_logic; process(clk) if rising_edge(clk) then if We = '1' then R <= D; end process; D <= R when Re = '1' else 'Z'; end RTL; 5

6 e) library ieee; entity One_e is port ( A, B : in std_logic; X, Y : out std_logic); end One_e; architecture Proc of One_e is signal Internal : std_logic; P1 : process (A, B) if A = '1' and B = '0' then X <= A; Internal <= '0'; else X <= B; Internal <= '1'; end process P1; P2 : process (A, B, Internal) if Internal = '1' then Y <= A; else Y <= B; end process P2; end Proc; 6

7 2 Finite state machine (5 p) Design a state machine that detects a sequence of logic 1 s occurring at the input and that asserts a logic 1 at the output during the last state of the sequence. An example input and output sequence is shown below. Each input/output bit corresponds to one clock cycle. Input sequence: Output sequence: The inputs are: D, serial input data Clk, clock signal Reset, asynchronous reset that initializes the state machine The output is: F, the single bit output a) Draw an ASM chart to describe the state machine. (If you are more comfortable with bubble charts you may draw such a chart instead.). Is the F output a Mealy or Moore output? (2.5 p) b) Write a VHDL description of the state machine. (2.5 p) 7

8 3 Testing, testing (5p, 1p each) a) What is the difference between testing and verification? b) What is fault coverage? c) What is BIST? (hint: it has something to do with testing) d) What is static timing analysis? Where in the design flow is this used? e) In order to speed up VHDL simulation variables should be used instead of signals wherever possible. Is this statement true? Explain. 8

9 4 SMD098 synchronous digital design rules (5 p) During the lectures you have learned a few rules for synchronous digital design. Some of these rules are listed below. For each rule, give a motivation why the rule should exist. For instance for rule 1) you may explain the problems related to having multiple clocks in a design. 1. Use one global clock (if possible) 2. Do not touch the clock! Use clock enable instead of clock gating 3. Combinational feedback loops are banned 4. Never source an asynchronous reset/set from combinational logic 5. Avoid using latches 6. Never synchronize an asynchronous input in more than one place 7. Be very careful when interfacing asynchronous signals 8. Do not throw beavers in wooden houses 9

10 5 Programmable Logic (5 p, 1 p each) a) What is a PAL? Explain by drawing a block diagram of a PAL. What type of logic can you implement with a PAL? b) What is a CPLD? Explain by drawing a block diagram of a CPLD. c) Draw a basic block diagram of a general FPGA architecture. Show the I/O blocks, routing resources and programmable function units (Xilinx calls their function units configurable logic blocks, CLBs). d) The Xilinx Virtex chips contain DLLs. What is a DLL and what can the Virtex DLLs be used for? e) Consider the two gate schematics below. They both implement the same functionality. The original gate level implementation requires three AND gates AND two OR gates. The replicated logic implementation requires one extra AND gate. So obviously if your target technology library is a gate library the original gate level implementation requires the least area. However, now assume that your target technology consist of 4-input LUTs instead. The replicated logic structure would require less LUTs to implement compared to the original gate level implementation. Explain why this is the case. Original gate level implementation Replicated logic 10

11 6 Behavioural synthesis (7.5 points) You have an algorithmic description of a computational structure given by the source code listed below. library ieee; entity Exam is port ( A, B, C, D, E : in integer; X, Y : out integer); end Exam; architecture Algorithm of Exam is X <= E*(A+B+C); Y <= (A+C)*(C+D); end Algorithm; Notice the description is purely combinational. Your task is to perform behavioral synthesis and transfer the algorithm to a synchronous sequential computational structure. a) Draw the data flow graph (DFG) for the algorithm. (0.5 p) b) Schedule the DFG with the ALAP (as late as possible) and the ASAP (as soon as possible) scheduling techniques. Draw both schedules and clearly indicate in which clock cycle each operation is performed. For each schedule, how many multipliers and adders are needed and what is the latency? (1 p) c) Reschedule the DFG with the constraint that only one multiplier and one adder is available. Minimize the latency. What is the latency of this schedule? (1 p) d) Allocate functional units and registers for the resource constrained schedule in c). Allocate one register for each input and output. Try to minimize the number of registers by exploiting register sharing. You should assume that you can use registers with clock enable input. (1 p) e) Draw the data path of the constrained schedule. Use registers, multiplexers, the adder and the multiplier. Clearly indicate the name of each register, input and output. These should correspond to the names you assigned in d). (2 p) f) Draw the ASM chart of the controller for the data path in e). The ASM chart should indicate what each register is assigned during the end of the current state. For instance in state S2 you might have the following assignment: (2 p) Reg3 A + B; 11