CS52 Computer Architecture and Engineering Lecture : Designing a Single Cycle February 7, 995 Dave Patterson (patterson@cs) and Shing Kong (shing.kong@eng.sun.com) Slides available on http://http.cs.berkeley.edu/~patterson cs 52 control. DAP & SIK 995 Recap: The MIPS Formats All MIPS instructions are bits long. The three instruction formats: 3 2 2 R-type op rs rt rd shamt t bits 5 bits 5 bits 5 bits 5 bits bits I-type 3 2 2 op rs rt immediate bits 5 bits 5 bits bits J-type 3 2 op target address bits 2 bits The different fields are: op: operation of the instruction rs, rt, rd: the source and destination registers specifier shamt: shift amount t: selects the variant of the operation in the op field address / immediate: address offset or immediate value target address: target address of the jump instruction cs 52 control.2 DAP & SIK 995
Recap: The MIPS Subset ADD and subtract add rd, rs, rt sub rd, rs, rt OR Imm: ori rt, rs, imm LOAD and STORE lw rt, rs, imm sw rt, rs, imm BRANCH: beq rs, rt, imm 3 3 2 2 op rs rt rd shamt t bits 5 bits 5 bits 5 bits 5 bits bits 2 2 op rs rt immediate bits 5 bits 5 bits bits JUMP: 3 2 j target op target address bits 2 bits cs 52 control.3 DAP & SIK 995 Recap: A Single Cycle Datapath We have everything ecept control signals (underline) Today s lecture will show you how to generate the control signals RegDst busw Mu Rs Rt RegWr 5 5 5 Rd imm Rt Rw Ra Rb -bit Registers busb Etender Branch busa EtOp Jump Mu Src Fetch Unit ctr Data In cs 52 control.4 DAP & SIK 995 Zero <3:> Rt <2:25> Rs <:2> MemWr WrEn Adr Data Rd <:5> <:5> Imm Mu MemtoReg
The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Input Datapath Output Today s Topic: Designing the for the Single Cycle Datapath cs 52 control.5 DAP & SIK 995 Outline of Today s Lecture Recap and Introduction ( minutes) for Register-Register & Or Immediate instructions ( minutes) Questions and Administrative Matters (5 minutes) signals for Load, Store, Branch, & Jump (5 minutes) Building a local controller: ( minutes) Break (5 minutes) The main controller (2 minutes) Summary (5 minutes) cs 52 control. DAP & SIK 995
RTL: The ADD 3 2 2 op rs rt rd shamt t bits 5 bits 5 bits 5 bits 5 bits bits add rd, rs, rt mem[pc] Fetch the instruction from memory R[rd] <- R[rs] + R[rt] The actual operation PC <- PC + 4 Calculate the net instruction s address cs 52 control.7 DAP & SIK 995 Fetch Unit at the Beginning of Add / Subtract Fetch the instruction from memory: <- mem[pc] This is the same for all instructions PC 3 imm <5:> 3 PC<3:28> Target 4 <25:> 2 Adder SignEt 3 Adder 3 3 3 Mu Mu Jump = previous Addr<3:2> Addr<:> <3:> Branch = previous Zero = previous cs 52 control.8 DAP & SIK 995
The Single Cycle Datapath during Add and Subtract 3 RegDst = Jump = Rd Rt Mu RegWr = busw Rs Rt 5 5 5 busa Rw Ra Rb -bit Registers imm 2 R[rd] <- R[rs] + / - R[rt] Branch = EtOp = busb Etender 2 ctr = Add or Subtract Mu op rs rt rd shamt t Src = Fetch Unit Data In cs 52 control.9 DAP & SIK 995 Zero <3:> Rt <2:25> Rs <:2> MemtoReg = MemWr = WrEn Adr Data Rd <:5> <:5> Imm Mu Fetch Unit at the End of Add and Subtract PC <- PC + 4 This is the same for all instructions ecept: Branch and Jump PC 3 imm <5:> 3 PC<3:28> Target 4 <25:> 2 Adder SignEt 3 Adder 3 3 3 Mu Mu Jump = Addr<3:2> Addr<:> <3:> Branch = Zero = cs 52 control. DAP & SIK 995
The Single Cycle Datapath during Or Immediate 3 RegDst = Jump = Rd Rt Mu RegWr = Rs Rt 5 5 5 ctr = Or busw busa Rw Ra Rb -bit Registers imm 2 EtOp = busb Etender 2 op rs rt immediate R[rt] <- R[rs] or ZeroEt[Imm] Branch = Mu Src = Fetch Unit Data In cs 52 control. DAP & SIK 995 Zero <3:> Rt <2:25> Rs <:2> MemWr = WrEn Adr Data Rd <:5> <:5> Imm MemtoReg = Mu Questions and Administrative Matters Midterm net Wednesday 2/22/95: 5:pm to 8:pm, Sibley Auditorium No class on that day Things to bring to midterm: Pencil, calculator, two 8.5 pages of handwritten notes Sit every other chair, every other row (odd row & odd seat) Meet at LaVal s pizza after the midterm ($5/person) - Need a headcount. How many are definitely coming? Net homework assignment due Tuesday, 2./2/95 Monday is a holiday cs 52 control.2 DAP & SIK 995
The Single Cycle Datapath during Load 3 2 2 op rs rt immediate R[rt] <- Data {R[rs] + SignEt[imm]} RegDst = Jump = Rd Rt Mu RegWr = busw Rs Rt 5 5 5 busa Rw Ra Rb -bit Registers busb imm EtOp = Branch = Etender Mu Src = Fetch Unit ctr = Add Data In cs 52 control.3 DAP & SIK 995 Zero <3:> Rt <2:25> Rs <:2> MemWr = WrEn Adr Data Rd <:5> Imm MemtoReg = <:5> Mu The Single Cycle Datapath during Store 3 2 2 op rs rt immediate Data {R[rs] + SignEt[imm]} <- R[rt] RegDst = Jump = Rd Rt Mu RegWr = busw Rs Rt 5 5 5 busa Rw Ra Rb -bit Registers busb imm EtOp = Branch = Etender Mu ctr = Add Data In Src = Fetch Unit cs 52 control.4 DAP & SIK 995 Zero <3:> Rt <2:25> Rs <:2> MemtoReg = MemWr = WrEn Adr Data Rd <:5> <:5> Imm Mu
The Single Cycle Datapath during Branch 3 2 2 op rs rt immediate if (R[rs] - R[rt] == ) then Zero <- ; else Zero <- <3:> Branch = Jump = Rd Rt RegDst = Mu RegWr = Rs Rt 5 5 5 busa Rw Ra Rb busw -bit Registers busb imm EtOp = Etender Mu ctr = Subtract Src = Fetch Unit Data In cs 52 control.5 DAP & SIK 995 Zero Rt <2:25> Rs <:2> MemWr = WrEn Adr Data Rd <:5> <:5> Imm MemtoReg = Mu Fetch Unit at the End of Branch 3 2 2 op rs rt immediate if (Zero == ) then PC = PC + 4 + SignEt[imm]*4 ; else PC = PC + 4 PC 3 imm <5:> PC<3:28> Target <25:> Adder SignEt 3 4 2 3 Adder 3 3 3 Mu Branch = Zero = Mu Jump = Assume Zero = to see the interesting case. Addr<3:2> Addr<:> <3:> cs 52 control. DAP & SIK 995
The Single Cycle Datapath during Jump 3 2 op target address Nothing to do! Make sure control signals are set correctly! Branch = <3:> Jump = Rd Rt Fetch Unit RegDst = Mu RegWr = 5 5 Rs Rt ctr = Rt Rs Rd Imm 5 MemtoReg = busa Zero MemWr = Rw Ra Rb busw -bit Registers busb WrEn Adr imm Data In Data Src = EtOp = Etender Mu cs 52 control.7 DAP & SIK 995 <2:25> <:2> <:5> <:5> Mu Fetch Unit at the End of Jump 3 2 op target address PC <- PC<3:29> concat target<25:> concat PC 3 imm <5:> PC<3:28> Target <25:> Adder SignEt 3 3 4 2 Adder 3 3 3 Mu Mu Jump = Addr<3:2> Addr<:> <3:> Branch = Zero = cs 52 control.8 DAP & SIK 995
A Summary of the Signals See We Don t Care :-) Appendi A op add sub ori lw sw beq jump RegDst Src MemtoReg RegWrite MemWrite Branch Jump EtOp ctr<2:> Add Subtract Or Add Add Subtract R-type 3 2 2 op rs rt rd shamt t add, sub I-type op rs rt immediate ori, lw, sw, beq J-type op target address jump cs 52 control.9 DAP & SIK 995 The Concept of Local Decoding op R-type ori lw sw beq jump RegDst Src MemtoReg RegWrite MemWrite Branch Jump EtOp op<n:> R-type Or Add Add Subtract op Main op N (Local) ctr 3 cs 52 control.2 DAP & SIK 995
The Encoding of op op Main op N (Local) ctr 3 In this eercise, op has to be 2 bits wide to represent: () R-type instructions I-type instructions that require the to perform: - (2) Or, (3) Add, and (4) Subtract To implement the full MIPS ISA, op hat to be 3 bits to represent: () R-type instructions I-type instructions that require the to perform: - (2) Or, (3) Add, (4) Subtract, and (5) And (Eample: andi) R-type ori lw sw beq jump op (Symbolic) R-type Or Add Add Subtract op<2:> cs 52 control.2 DAP & SIK 995 The Decoding of the Field op Main op N (Local) ctr 3 R-type ori lw sw beq jump op (Symbolic) R-type Or Add Add Subtract op<2:> R-type 3 2 2 op rs rt rd shamt t t<5:> Operation add subtract and or set-on-less-than Recall Homework (also P. 28 tet): ctr<2:> Operation Add Subtract And Or Set-on-less-than cs 52 control.22 DAP & SIK 995
The Truth Table for ctr op R-type ori lw sw beq (Symbolic) R-type Or Add Add Subtract op<2:> t<3:> Op. add subtract and or set-on-less-than op bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> ctr Operation bit<2> bit<> bit<> Add Subtract Or Add Subtract And Or Set on < cs 52 control.23 DAP & SIK 995 Break (5 Minutes) cs 52 control.24 DAP & SIK 995
The Logic Equation for ctr<2> op bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> ctr<2> This makes <3> a don t care ctr<2> =!op<2> & op<> + op<2> &!<2> & <> &!<> cs 52 control.25 DAP & SIK 995 The Logic Equation for ctr<> op bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> ctr<> ctr<> =!op<2> &!op<> + op<2> &!<2> &!<> cs 52 control.2 DAP & SIK 995
The Logic Equation for ctr<> op bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> ctr<> ctr<> =!op<2> & op<> + op<2> &!<3> & <2> &!<> & <> + op<2> & <3> &!<2> & <> &!<> cs 52 control.27 DAP & SIK 995 The Block op 3 (Local) ctr 3 ctr<2> =!op<2> & op<> + op<2> &!<2> & <> &!<> ctr<> =!op<2> &!op<> + op<2> &!<2> &!<> ctr<> =!op<2> & op<> + op<2> &!<3> & <2> &!<> & <> + op<2> & <3> &!<2> & <> &!<> cs 52 control.28 DAP & SIK 995
The Truth Table for the Main op Main RegDst Src : op 3 (Local) op R-type ori lw sw beq jump RegDst Src MemtoReg RegWrite MemWrite Branch Jump EtOp op (Symbolic) R-type Or Add Add Subtract op <2> op <> op <> cs 52 control.29 DAP & SIK 995 ctr 3 The Truth Table for RegWrite op R-type ori lw sw beq jump RegWrite RegWrite = R-type + ori + lw =!op<5> &!op<4> &!op<3> &!op<2> &!op<> &!op<> (R-type) +!op<5> &!op<4> & op<3> & op<2> &!op<> & op<> (ori) + op<5> &!op<4> &!op<3> &!op<2> & op<> & op<> (lw). <> <> <> <>op<5>. <> op<> R-type ori lw sw beq jump RegWrite cs 52 control.3 DAP & SIK 995
PLA Implementation of the Main <> <> <> <> <> op<> R-type ori lw sw beq jump RegWrite Src RegDst MemtoReg MemWrite Branch Jump EtOp op<2> op<> op<> cs 52 control.3 DAP & SIK 995 op Instr<3:2> RegDst Putting it All Together: A Single Cycle Processor busw Mu Rs Rt RegWr 5 5 5 Main Rd imm Instr<5:> Rt Rw Ra Rb -bit Registers op RegDst Src : busb Etender Branch busa EtOp Jump 3 Mu Src Fetch Unit ctr Data In cs 52 control. DAP & SIK 995 Instr<5:> Zero <3:> Rt <2:25> Rs <:2> MemWr WrEn Adr Data ctr Rd <:5> 3 <:5> Imm Mu MemtoReg
How is this Different from a Real MIPS Processor? The effect of load in a real MIPS Processor is delayed: - lw $, ($2) // Load Register R - add $3, $, $ // Move old R into R3 - add $4, $, $ // Move new R into R4 The effect of load in our single cycle proccess is NOT delayed - lw $, ($2) // Load Register R - add $3, $, $ // Move new R into R3 The effect of branch and jump in a real MIPS Processor is delayed: - Address: j - Address: 4 add $, $2, $3 - Address: sub $, $2, $3 Branch and jump in our single cycle proccess is NOT delayed - Address: j - Address: sub $, $2, $3 cs 52 control.33 DAP & SIK 995 Worst Case Timing PC Rs, Rt, Rd, Op, Func ctr Old Value -to-q New Value Old Value Old Value Memoey Access Time New Value Delay through Logic New Value EtOp Old Value New Value Src Old Value New Value MemtoReg Old Value New Value Register Write Occurs RegWr Old Value New Value Register File Access Time busa Old Value New Value Delay through Etender & Mu busb Old Value New Value Delay Address Old Value New Value Data Access Time busw Old Value New cs 52 control.34 DAP & SIK 995
Drawback of this Single Cycle Processor Long cycle time: Cycle time must be long enough for the load instruction: PC s Clock -to-q + Access Time + Register File Access Time + Delay (address calculation) + Data Access Time + Register File Setup Time + Clock Skew Cycle time is much longer than needed for all other instructions cs 52 control.35 DAP & SIK 995 Where to get more information? Chapter 5. to 5.3 of your tet book: Daid Patterson and John Hennessy, Computer Organization & Design: The Hardware / Software Interface, Morgan Kaufman Publishers, San Mateo, California, 994. One of the best PhD thesis on processor design: Manolis Katevenis, Reduced Set Computer Architecture for VLSI, PhD Dissertation, EECS, U C Berkeley, 982. For a reference on the MIPS architecture: Gerry Kane, MIPS RISC Architecture, Prentice Hall. cs 52 control.3 DAP & SIK 995