Anode LCT 2001 Design

Anode LCT 2001 Design UCLA and U. Florida High Energy Physics Version 2.4 NOTE: this version adapted from v2.2 by AM, some discrep s with v2.3 by JH may exist and need to be reconciled. April 14, 2003 Abstract This document describes the UCLA Anode Local Charged Track board, version 2001. Signals to and from the other modules that comprise the system are specified in detail, including all data bits and connector pins that involve the ALCT2001 board. ALCT2001 Functionality The ALCT2001 board is a 4 th generation design that finds Anode Local Charged Tracks in a Cathode Strip Chamber. Only slight modifications are planned for the production version. There are three variants: 384, 672, and 288 channel versions, in order of expected production date. The numbers of chambers and ALCT boards of various types are shown below in Table 1. Table 1. Numbers of chambers and ALCTs of various types. CSC Type Chambers Wire Groups ALCT384s ALCT672s ALCT288s ME1/1 72 288 72 ME1/2 72 384 72 ME1/3 72 192 72 ME2/1 36 672 36 ME2/2 72 384 72 ME3/1 36 576 36 ME3/2 72 384 72 ME4/1 36 576 36 ME4/2 72 384 72 Total US base 360 216 72 72 Total US+ME4/1 396 216 108 72 Total US+ME1/1 432 216 72 144 Total US+ME1/1+ME4/1+ME4/2 540 288 108 144 The ALCT2001 boards are constructed of a relatively large motherboard (384-channel variant shown in Figure 1 on which is placed a small mezzanine card containing a Virtex FPGA with many ball-grid array (BGA) connections (shown in Figure 2). The motherboard comes in different varieties to accommodate the different number of input wire groups, while only one mezzanine card accommodates all varieties of ALCT motherboards. Page 1 of 62

Figure 1 Picture of the ALCT2001-384 motherboard. Figure 2. Picture of the ALCT mezzanine card. Page 2 of 62

Page 3 of 62 Table of Contents ABSTRACT... 1 ALCT2001 FUNCTIONALITY... 1 TABLE OF CONTENTS... 3 LIST OF FIGURES... 6 LIST OF TABLES... 7 SYSTEM OVERVIEW... 8 AFEB... 9 CFEB... 9 ALCT 2001... 9 TMB 2001... 9 CCB... 9 DAQMB... 9 ALCT2001 OVERVIEW... 10 ALCT2001 COMPONENTS... 10 AFEB I/O connector... 11 Delay ASIC... 11 Bus Multiplexer... 11 LCT FPGA... 11 Xilinx EEPROMs... 11 JTAG Chain Multiplexer... 11 Slow Control FPGA... 11 DACs... 11 ADCs... 11 Test Pulse Generator... 11 Power Supply... 12 DATA FORMATS... 13 ANODE DISCRIMINATOR BOARD... 13 AFEB OVERVIEW... 13 AFEB-ALCT2001 Signals... 13 AFEB CHANNEL MAPPING... 13 Mapping CSC Wire Groups and Layers to AFEB Card and Channel... 14 Mapping Wire Groups/Layers to multiplexed ALCT and Mezzanine card signal names, Virtex pins, and Virtex firmware... 15 TEST POINTS AND LEDS... 19 DELAY ASIC... 20 Programming... 20 Delay ASIC Signals... 21 Binning by Maximum Delay... 21 GENERAL REMARKS ON JTAG PROGRAMMING... 23 GENERAL REMARKS ON JTAG PROGRAMMING... 23 XILINX FPGAS... 24 XILINX FLASH MEMORY... 24 TAP Controller... 24 JTAG TAP States... 25 JTAG TAP States... 26 VIRTEX JTAG REGISTERS... 27 Virtex FPGA Instruction Register... 27 Virtex ID Register... 29 Virtex Configuration Register... 30 Virtex Trigger Register... 32

Virtex Bypass Register... 33 HOT CHANNEL MASK REGISTER... 33 DELAY LINE REGISTER... 33 DELAY LINE CONTROL REGISTER... 33 COLLISION MASK REGISTER... 33 OUTPUT REGISTER... 34 OUTPUT FIFO... 34 DAQ DATA FORMAT FOR ALCT2001... 36 ALCT-2001 ALGORITHM DESCRIPTION... 37 SLOW CONTROL JTAG PROGRAMMING... 40 Slow Control Instruction Register... 40 Slow Control ID Register... 41 Reset Threshold DAC... 41 Reset Delay ASIC... 41 Write Test Pulse DAC... 41 Write Threshold DAC(i, i=0..3)... 41 Read Threshold ADC(i, i=0..4)... 42 Write Test Pulse Group... 44 Read Test Pulse Group... 44 Write Test Pulse Strip... 44 Read Test Pulse Strip... 45 Write Standby Register... 45 Read Standby Register... 45 Write TP Power Down... 45 Read TP Power Down... 45 Bypass Scan... 45 CONFIGURATION JUMPERS... 46 ALCT2001 CONNECTORS... 47 J1 XILINX LVDS X-BLASTER CONNECTOR... 48 J2 POWER CONNECTOR... 48 Power Requirements... 48 Power Protection... 50 EACH AFEB IS PROTECTED INDIVIDUALLY AGAINST SHORTS OR HIGH CURRENT CONDITIONS (E.G. LATCHUP) WITH 1.0A RESETTABLE FUSES.J3 EXTERNAL TEST PULSE INPUT... 50 J3 EXTERNAL TEST PULSE INPUT... 51 J4 AND J5: SCSI CONNECTORS FOR TMB I/O... 51 LOGICAL DESCRIPTION OF ALCT-TMB SIGNALS... 51 J5 TMB CABLE 1... 52 J4 TMB CABLE 2... 53 J4/J5 TMB Connectors... 54 J6-J11 STRIP TEST PULSE OUTPUTS... 55 J12-J29 OR J12-35 OR J12-53 AFEB BOARD I/O... 55 MECHANICAL SPECS... 56 MECHANICS FOR 384-CHANNEL VERSION... 56 PCB Footprint... 56 Stiffener Plate Dimensions... 57 MECHANICS FOR 672-CHANNEL VERSION... 58 PCB Footprint... 58 Stiffener Plate Dimensions... 59 MECHANICS FOR 288-CHANNEL VERSION... 60 PCB Footprint... 60 Stiffener plate dimensions... 61 REVISION HISTORY... 62 Page 4 of 62

Page 5 of 62

List of Figures Figure 1 Picture of the ALCT2001-384 motherboard....2 Figure 2. Picture of the ALCT mezzanine card...2 Figure 3: System Diagram from ALCT2001 point of view....8 Figure 4: ALCT2001 Components, 384-channel board type....10 Figure 5: TAP State Machine (4-bit TAP controller states indicated)....25 Figure 6: ALCT2001 Power Connector...48 Figure 7: 50-Pin PCB Connector (Female)...54 Figure 8: 50 Pin Cable Connector (Male)...54 Figure 9: ALCT2001-384 PCB footprint....56 Figure 10: ALCT2001-384 Stiffener Plate footprint...57 Figure 11: ALCT2001-672 PCB footprint....58 Figure 12: ALCT2001-672 Stiffener Plate footprint...59 Figure 13: ALCT2001-288 PCB footprint....60 Figure 14: ALCT2001-288 Stiffener Plate footprint...61 Page 6 of 62

List of Tables Table 1. Numbers of chambers and ALCTs of various types...1 Table 2: AFEB-ALCT2001 Signals...13 Table 3: Mapping CSC Wire Groups to AFEB Card/Channel...14 Table 4: Mapping Wire Groups/Layers to multiplexed ALCT and Mezzanine card signal names, Virtex pins. Virtex firmware names (AM design) are approximately the same as the ALCT signal names, e.g. LCT0_0, LCT0_1, etc. ALCT384 variant shown...15 Table 5. Map from Delay ASIC channels to Layers and Wire Groups...20 Table 6: Delay ASIC Signals...21 Table 7: TAP Controller States...26 Table 8: Virtex JTAG instructions for ALCT2001....27 Table 9: Virtex ID Register...29 Table 10: Virtex Configuration Register...30 Table 11: Virtex Trigger Register...32 Table 12 ALCT DAQ data format...36 Table 13: Slow Control JTAG Instruction Op Codes...40 Table 14: Slow Control ID Register...41 Table 15: Threshold DAC Channel Assignments...42 Table 16: ADC Channel Assignments...43 Table 17: Delay ASIC Group Assignments...44 Table 18: Analog Test Pulse AFEB Group Assignments...44 Table 19: ALCT2001 PCB Jumpers...46 Table 20: ALCT2001 Input/Output Signals....47 Table 21: ALCT2001 Connectors...47 Table 22: Xilinx LVDS X-Blaster Connector...48 Table 23: Measured Power Supply Currents [ALCT2001-384]...49 Table 24: Power Estimate for ALCT2001 Variants (simple scaling)...50 Table 25: ALCT2001 Power Requirements....50 Table 26: TMB Cable 1 Signal and Pin Assignments...52 Table 27: TMB Cable2 Connector...53 Table 28: AMP 50-Pin SCSI PCB Connector...54 Table 29: J13-J36 AFEB I/O Connector...55 Page 7 of 62

System Overview A block diagram of the system from the ALCT point of view is shown in Figure 3. The TMB has other system connections which are described in a separate TMB specification document. Figure 3: System Diagram from ALCT2001 point of view. ADB0 16-Wire Groups ADB23 (17,23,41 variants) LVDB +5.5v power Vthreshold Test Pulse /Standby Out[15..0] +1.8v power +3.3v power +5.5v_1 power +5.5v_2 power ALCT2001 ------------------ J11 ------------------- ------------- J10 ------------ 1 st LCT 2 nd LCT DAQ data BXN SEU Status 40 MHz Clock JTAG Config Done L1Accept BX0 BXReset TTC Command Ext_Inject Ext_Trig Test Pulse --------------- Front Panel I/O ----------------- TMB CFEB0 96 Strips = 48 ½-Strip Triads CFEB4 (3,4 variants) 40 MHz Clock Reset Triad[23..0] Triad[47..24] ------ Front Panel I/O ------ Rear Panel I/O 1st LCT 2nd LCT Active FEB Data VME Backplane TTCrx CCB 40MHz Clock L1Accept BxReset Bx0 TTC Cmd MPC DAQMB VME Backplane Page 8 of 62

System Overview (Continued) AFEB Anode Discriminator Boards indicate which CSC anode wire-groups have signals over threshold. Each board outputs 16 asynchronous, uncompressed bits. Depending on the size of the CSC there are between 18 and 42 AFEB boards mounted along the chamber edge. CFEB Cathode Front End Boards indicate which CSC cathode strips have signals over threshold. Chargecluster center-finding and data compression are performed by an on-board ASIC. Each board outputs 48 synchronous bits compressed into triad serial-data streams. ALCT 2001 The Anode LCT board receives AFEB discriminator signals from a Cathode Strip Chamber and attempts to identify the location (eta coordinate) and quality of the best-two muon track stubs transiting the chamber. A single ALCT2001 board can accept all of the signals from an entire CSC. There are 3 versions of the ALCT2001, having either 288, 384 or 672 channels that correspond to different CSC sizes. Results from the muon pattern-finder logic are sent to the Trigger Motherboard, which requires a coincidence between anode and cathode trigger information. In the case of a Level-1 Accept signal, LCT frames are transmitted to the Trigger Mother Board and hence to the DAQ Motherboard. The ALCT also sends FIFO data consisting of raw CSC wire-group hits that have been stored and serialized by the ALCT2001. FIFO data can also be read out via a JTAG interface. TMB 2001 The Trigger Mother Board TMB 2001 contains Cathode LCT logic and anode/cathode coincidence logic. Cathode LCT logic receives Comparator signals from the Cathode Front End Boards and finds the location (phi coordinate), bend angle, and quality of the two best track stubs transiting the chamber. Results from the muon pattern-finder logic are formatted into LCT data frames for each muon found. The anode/cathode logic receives ALCT and CLCT data for the 2 best muons found in the CSC on every clock cycle. It performs a time correlation between anode and cathode views of the muon track-stub. Successful matches are forwarded to the Muon Port Card for input to the muon trigger system. CCB The Clock and Control Board (CCB) distributes the 40MHz system clock, Level 1 Accept signal, and Bunch Crossing signals to all the VME modules in the system. It also sends synchronous commands from the TTC system. DAQMB The Data Acquisition Motherboard receives trigger and raw-hits FIFO data from the TMB for inclusion in the data output stream. It also receives Active FEB bits that indicate which of the Anode and Cathode Front End Boards have trigger. The DAQMB sends output data via optical links for readout. Page 9 of 62

ALCT2001 Overview ALCT boards contain 288, 384, or 672 channels, from 3, 4 or 7 sets of 96 channels, depending on the type of CSC. The 96 channel units correspond to discriminator bits from 16 wire groups times 6 chamber layers. The ALCT logic finds anode hit-patterns consistent with passage from the collision point and quantify the two best muon track-stub (a Local Charged Track) that transit the CSC. ALCT2001 Components Figure 4: ALCT2001 Components, 384-channel board type. AFEB I/O AFEB I/O AFEB I/O AFEB I/O AFEB I/O AFEB I/O Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Bus Mux Bus Mux Bus Mux Bus Mux Delay Bus Mux ASIC Bus Mux Power +5.5v_1,+5.5v_2, +3.3v, +1.8v Low Voltage Distribution Board AFEB I/O AFEB I/O AFEB I/O AFEB I/O AFEB I/O AFEB I/O AFEB I/O AFEB I/O AFEB I/O AFEB I/O Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Bus Mux Bus Mux Bus Mux Bus Mux Bus Mux Bus Mux Bus Mux Bus Mux Bus Mux Bus Mux LCT FPGA on Mezzanine Card Clock, BX0, BxReset, L1Accept, Test Pulse, from TMB LCT #1, LCT #2 to TMB LCT, Input Bits Dump to TMB AFEB I/O AFEB I/O Delay ASIC Delay ASIC Bus Mux Bus Mux Test Strips AFEB I/O AFEB I/O AFEB I/O AFEB I/O AFEB I/O AFEB I/O Analog Test Pulse Generator Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Delay ASIC Threshold DACs Serial Bus Bus Mux Bus Mux Bus Mux Bus Mux Bus Mux Bus Mux ADCs CLK 40, 80 MHz Currents, Voltages Temp Sensor Test Pulse Strobe Slow Control FPGA Xilinx EEPROMs Control JTAG Control JTAG Config JTAG JTAG Chain Mux - TMB priority over XBlaster Config JTAG Xilinx EEPROM JTAG from XBlaster JTAG from TMB Serial Busses Page 10 of 62

AFEB I/O connector receives 16 discriminator output signals, and supplies power (+5.5V) and control signals (/stand_by, V thr, test_pulse) to the AFEB cards. Delay ASIC is a full-custom Application-Specific Integrated Circuit that receives 16 differential LVDS inputs from an AFEB and outputs 16 single-ended TTL outputs to the LCT chip. It has a programmable propagation delay, and provides fixed-width output pulses. Bus Multiplexer latches data from AFEBs synchronously at 40 MHz and transmits it at 80 MHz to the LCT FPGA in order to save a factor of 2 in number of input and output signals at the FPGA. LCT FPGA is mounted on a mezzanine card. It receives input anode hits at 80 MHz from the bus multiplexers. When a valid track-stub pattern is found, the Concentrator formats and forwards the data for the best 2 muons to the Trigger Mother Board (TMB). When a Level 1 Accept arrives, the LCT FPGA transfers trigger and raw-hits data to the DAQ Mother Board (DAQMB). The LCT FPGA also writes to the serial configuration chains (delay settings and test pattern register) for the Delay ASICs. Xilinx EEPROMs store configuration data for FPGAs. There is one of these for the Slow Control FPGA and up to 3 of these on the mezzanine card. In CMS operation, these are normally downloaded with JTAG protocol on rare occasions via the Trigger Motherboard. The FPGAs are normally loaded from the EEPROMs when power is cycled or when a hard reset signal is received from the TMB. This loading takes 24.7 ms in the case of XCV600E and 41 ms in the case of XCV1000E Virtex chip. In debugging mode, an external JTAG cable can be connected via a small LVDS Xblaster that is connected directly to the parallel port of a PC. JTAG Chain Multiplexer multiplexes JTAG signals among 4 chains according to two control bits. The chains are: LCT FPGA configuration (programming), LCT FPGA control registers, Slow Control FPGA configuration (programming), Slow Control FPGA control registers. Slow Control FPGA writes the DACs (AFEB threshold, Test Pulse amplitude), reads the ADCs (DAC read-back, power supply voltages and currents, and on-board temperature), and controls Test Pulse distribution. DACs provide discriminator threshold voltages for the AFEBs. These 12-channel, 8-bit serial DACs can not be read-back directly, so their outputs are connected to ADCs that can be read via JTAG. The DAC voltages are set via JTAG commands to the Slow Control FPGA. ADCs digitize the threshold DACs for read-back. The 12-channel, 8-bit ADCs also digitize power supply voltages and currents as well as the on-board temperature sensor. They are read via JTAG commands to the Slow Control FPGA. Test Pulse Generator produces test pulses for the AFEB cards and for the CSC test pulse strips. The pulse amplitude is determined by an 8-bit DAC that is set by JTAG commands to the Slow Control FPGA. A JTAG register selects the AFEBs and strips to be pulsed. The test pulse is initiated by either JTAG command to the Concentrator chip or by a TTL pulse to the LEMO input (selected by a jumper). Page 11 of 62

Power Supply comes from the Low Voltage Distribution Board. There are two +5.5v inputs, one +3.3v input, and a +1.8v inputvoltages and currents are buffered and scaled for read-back by the ADCs. Fuses and Zener diodes protect ALCT circuitry. In addition, the ALCT2001 board supplies power to the AFEB cards through resettable fuses.. There is one on-board voltage regulators to make precision 5.0v for analog circuits from the first 5.5v channel. Page 12 of 62

Data Formats Anode Discriminator Board AFEB Overview For 288/384/672 channel versions, the ALCT2001 board receives 16 bits of data from each of 18/24/42 Anode Front-End Boards (AFEBs), respectively. Logic levels are compatible with standard LVDS (Low Voltage Differential Signaling), and represent the anode-wires having signal amplitudes above threshold. DACs on the ALCT2001 supply the AFEB threshold voltage via the AFEB-ALCT cables. Maximum threshold voltage is around +1.0 volts. Higher threshold voltages correspond to lower actual AFEB thresholds. AFEB output pulse widths are proportional to time-over-threshold. AFEB-ALCT2001 Signals The following shows the signals carried between AFEB and ALCT2001. A later portion of this document contains the exact specification of connector pins. +Outsn, -Outsn +Out_n, -Out_n /Stand_By Vthr Test_Pulse +5.5VA GND Table 2: AFEB-ALCT2001 Signals Discriminator Outputs, LVDS, for strip-side Anode wires Discriminator Outputs, LVDS AFEB voltage regulator shut-down Discriminator threshold voltage AFEB Test Pulse. Falling edge triggers all 16 channels +5.5V Analog Power Power Return AFEB Channel Mapping There are several relevant mappings: Chamber wire group and layer order is defined by CMS note 2000/004. Correspondance between wire group/layer and AFEB card and channel numbers. This is shown below in Table 3. Correspondance between wire group/layer and ALCT schematic name, Mezzanine card name, and Virtex pin number, and Virtex firmware name. This is shown below in Table 4. Page 13 of 62

Mapping CSC Wire Groups and Layers to AFEB Card and Channel Table 3: Mapping CSC Wire Groups to AFEB Card/Channel Wire Group Wire Group Layer AFEB 0 1 2 3 4 5 6 7 AFEB 8 9 10 11 12 13 14 15 0 0 4 5 6 7 12 13 14 15 3 4 5 6 7 12 13 14 15 1 0 0 1 2 3 8 9 10 11 3 0 1 2 3 8 9 10 11 2 1 4 5 6 7 12 13 14 15 4 4 5 6 7 12 13 14 15 3 1 0 1 2 3 8 9 10 11 4 0 1 2 3 8 9 10 11 4 2 4 5 6 7 12 13 14 15 5 4 5 6 7 12 13 14 15 5 2 0 1 2 3 8 9 10 11 5 0 1 2 3 8 9 10 11 Wire Group Wire Group Layer AFEB 16 17 18 19 20 21 22 23 AFEB 24 25 26 27 28 29 30 31 0 6 4 5 6 7 12 13 14 15 9 4 5 6 7 12 13 14 15 1 6 0 1 2 3 8 9 10 11 9 0 1 2 3 8 9 10 11 2 7 4 5 6 7 12 13 14 15 10 4 5 6 7 12 13 14 15 3 7 0 1 2 3 8 9 10 11 10 0 1 2 3 8 9 10 11 4 8 4 5 6 7 12 13 14 15 11 4 5 6 7 12 13 14 15 5 8 0 1 2 3 8 9 10 11 11 0 1 2 3 8 9 10 11 Wire Group Wire Group Layer AFEB 32 33 34 35 36 37 38 39 AFEB 40 41 42 43 44 45 46 47 0 12 4 5 6 7 12 13 14 15 15 4 5 6 7 12 13 14 15 1 12 0 1 2 3 8 9 10 11 15 0 1 2 3 8 9 10 11 2 13 4 5 6 7 12 13 14 15 16 4 5 6 7 12 13 14 15 3 13 0 1 2 3 8 9 10 11 16 0 1 2 3 8 9 10 11 4 14 4 5 6 7 12 13 14 15 17 4 5 6 7 12 13 14 15 5 14 0 1 2 3 8 9 10 11 17 0 1 2 3 8 9 10 11 Wire Group Wire Group Layer AFEB 48 49 50 51 52 53 54 55 AFEB 56 57 58 59 60 61 62 63 0 18 4 5 6 7 12 13 14 15 21 4 5 6 7 12 13 14 15 1 18 0 1 2 3 8 9 10 11 21 0 1 2 3 8 9 10 11 2 19 4 5 6 7 12 13 14 15 22 4 5 6 7 12 13 14 15 3 19 0 1 2 3 8 9 10 11 22 0 1 2 3 8 9 10 11 4 20 4 5 6 7 12 13 14 15 23 4 5 6 7 12 13 14 15 5 20 0 1 2 3 8 9 10 11 23 0 1 2 3 8 9 10 11 Wire Group Wire Group Layer AFEB 64 65 66 67 68 69 70 71 AFEB 72 73 74 75 76 77 78 79 0 24 4 5 6 7 12 13 14 15 27 4 5 6 7 12 13 14 15 1 24 0 1 2 3 8 9 10 11 27 0 1 2 3 8 9 10 11 2 25 4 5 6 7 12 13 14 15 28 4 5 6 7 12 13 14 15 3 25 0 1 2 3 8 9 10 11 28 0 1 2 3 8 9 10 11 4 26 4 5 6 7 12 13 14 15 29 4 5 6 7 12 13 14 15 5 26 0 1 2 3 8 9 10 11 29 0 1 2 3 8 9 10 11 Wire Group Wire Group Layer AFEB 80 81 82 83 84 85 86 87 AFEB 88 89 90 91 92 93 94 95 0 30 4 5 6 7 12 13 14 15 33 4 5 6 7 12 13 14 15 1 30 0 1 2 3 8 9 10 11 33 0 1 2 3 8 9 10 11 2 31 4 5 6 7 12 13 14 15 34 4 5 6 7 12 13 14 15 3 31 0 1 2 3 8 9 10 11 34 0 1 2 3 8 9 10 11 4 32 4 5 6 7 12 13 14 15 35 4 5 6 7 12 13 14 15 5 32 0 1 2 3 8 9 10 11 35 0 1 2 3 8 9 10 11 Wire Group Wire Group Layer AFEB 96 97 98 99 100 101 102 103 AFEB 104 105 106 107 108 109 110 111 0 36 4 5 6 7 12 13 14 15 39 4 5 6 7 12 13 14 15 1 36 0 1 2 3 8 9 10 11 39 0 1 2 3 8 9 10 11 2 37 4 5 6 7 12 13 14 15 40 4 5 6 7 12 13 14 15 3 37 0 1 2 3 8 9 10 11 40 0 1 2 3 8 9 10 11 4 38 4 5 6 7 12 13 14 15 41 4 5 6 7 12 13 14 15 5 38 0 1 2 3 8 9 10 11 41 0 1 2 3 8 9 10 11 Page 14 of 62

Mapping Wire Groups/Layers to multiplexed ALCT and Mezzanine card signal names, Virtex pins, and Virtex firmware. Table 4: Mapping Wire Groups/Layers to multiplexed ALCT and Mezzanine card signal names, Virtex pins. Virtex firmware names (AM design) are approximately the same as the ALCT signal names, e.g. LCT0_0, LCT0_1, etc. ALCT384 variant shown. MUX 1st Layer Page 15 of 62 1st WG 2nd Layer 2nd WG ALCT384 Connector Mezz Card FPGA pin for ALCT384 1 L1 W07 L3 W00 LCT0_0 XP1.A29 I/O_81 B25 1 L1 W06 L3 W01 LCT0_01 XP1.B29 I/O_82 C25 1 L1 W05 L3 W02 LCT0_02 XP1.C29 I/O_83 D25 1 L1 W04 L3 W03 LCT0_03 XP1.D29 I/O_84 A26 1 L1 W03 L3 W04 LCT0_04 XP1.A30 I/O_85 B26 1 L1 W02 L3 W05 LCT0_05 XP1.B30 I/O_86 C26 1 L1 W01 L3 W06 LCT0_06 XP1.C30 I/O_87 D26 1 L1 W00 L3 W07 LCT0_07 XP1.D30 I/O_88 A27 1 L0 W07 L2 W00 LCT0_08 XP1.A31 I/O_89 B27 1 L0 W06 L2 W01 LCT0_09 XP1.B31 I/O_90 C27 1 L0 W05 L2 W02 LCT0_10 XP1.C31 I/O_91 D27 1 L0 W04 L2 W03 LCT0_11 XP1.D31 I/O_92 A28 1 L0 W03 L2 W04 LCT0_12 XP1.A32 I/O_93 B28 1 L0 W02 L2 W05 LCT0_13 XP1.B32 I/O_94 C28 1 L0 W01 L2 W06 LCT0_14 XP1.C32 I/O_95 A29 1 L0 W00 L2 W07 LCT0_15 XP1.D32 I/O_96 B29 2 L5 W07 L1 W08 LCT0_16 XP1.A33 I/O_97 C29 2 L5 W06 L1 W09 LCT0_17 XP1.B33 I/O_98 D29 2 L5 W05 L1 W10 LCT0_18 XP1.C33 I/O_99 A30 2 L5 W04 L1 W11 LCT0_19 XP1.D33 I/O_100 B30 2 L5 W03 L1 W12 LCT0_20 XP1.A34 I/O_101 C30 2 L5 W02 L1 W13 LCT0_21 XP1.B34 I/O_102 D30 2 L5 W01 L1 W14 LCT0_22 XP1.C34 I/O_103 A31 2 L5 W00 L1 W15 LCT0_23 XP1.D34 I/O_104 B31 2 L4 W07 L0 W08 LCT0_24 XP1.A35 I/O_105 C31 2 L4 W06 L0 W09 LCT0_25 XP1.B35 I/O_106 D31 2 L4 W05 L0 W10 LCT0_26 XP1.C35 I/O_107 A32 2 L4 W04 L0 W11 LCT0_27 XP1.D35 I/O_108 B32 2 L4 W03 L0 W12 LCT0_28 XP1.A36 I/O_109 C32 2 L4 W02 L0 W13 LCT0_29 XP1.B36 I/O_110 D32 2 L4 W01 L0 W14 LCT0_30 XP1.C36 I/O_111 A33 2 L4 W00 L0 W15 LCT0_31 XP1.D36 I/O_112 B33 3 L3 W15 L5 W08 LCT0_32 XP1.A37 I/O_113 C33 3 L3 W14 L5 W09 LCT0_33 XP1.B37 I/O_114 D33 3 L3 W13 L5 W10 LCT0_34 XP1.C37 I/O_115 A34 3 L3 W12 L5 W11 LCT0_35 XP1.D37 I/O_116 B34 3 L3 W11 L5 W12 LCT0_36 XP1.A38 I/O_117 C34

MUX 1st Layer 1st WG 2nd Layer 2nd WG ALCT384 Connector Mezz Card FPGA pin for ALCT384 3 L3 W10 L5 W13 LCT0_37 XP1.B38 I/O_118 D34 3 L3 W09 L5 W14 LCT0_38 XP1.C38 I/O_119 A35 3 L3 W08 L5 W15 LCT0_39 XP1.D38 I/O_120 B35 3 L2 W15 L4 W08 LCT0_40 XP3.A03 I/O_121 C35 3 L2 W14 L4 W09 LCT0_41 XP3.B03 I/O_122 D35 3 L2 W13 L4 W10 LCT0_42 XP3.C03 I/O_123 A36 3 L2 W12 L4 W11 LCT0_43 XP3.D03 I/O_124 B36 3 L2 W11 L4 W12 LCT0_44 XP3.A04 I/O_125 B37 3 L2 W10 L4 W13 LCT0_45 XP3.B04 I/O_126 C38 3 L2 W09 L4 W14 LCT0_46 XP3.C04 I/O_127 D39 3 L2 W08 L4 W15 LCT0_47 XP3.D04 I/O_128 D38 4 L1 W23 L3 W16 LCT1_0 XP3.A05 I/O_129 D37 4 L1 W22 L3 W17 LCT1_01 XP3.B05 I/O_130 E39 4 L1 W21 L3 W18 LCT1_02 XP3.C05 I/O_131 E38 4 L1 W20 L3 W19 LCT1_03 XP3.D05 I/O_132 E37 4 L1 W19 L3 W20 LCT1_04 XP3.A06 I/O_133 F39 4 L1 W18 L3 W21 LCT1_05 XP3.B06 I/O_134 F38 4 L1 W17 L3 W22 LCT1_06 XP3.C06 I/O_135 F37 4 L1 W16 L3 W23 LCT1_07 XP3.D06 I/O_136 F36 4 L0 W23 L2 W16 LCT1_08 XP3.A07 I/O_137 G39 4 L0 W22 L2 W17 LCT1_09 XP3.B07 I/O_138 G38 4 L0 W21 L2 W18 LCT1_10 XP3.C07 I/O_139 G37 4 L0 W20 L2 W19 LCT1_11 XP3.D07 I/O_140 G36 4 L0 W19 L2 W20 LCT1_12 XP3.A08 I/O_141 H39 4 L0 W18 L2 W21 LCT1_13 XP3.B08 I/O_142 H38 4 L0 W17 L2 W22 LCT1_14 XP3.C08 I/O_143 H37 4 L0 W16 L2 W23 LCT1_15 XP3.D08 I/O_144 H36 5 L5 W23 L1 W24 LCT1_16 XP3.A09 I/O_145 J39 5 L5 W22 L1 W25 LCT1_17 XP3.B09 I/O_146 J38 5 L5 W21 L1 W26 LCT1_18 XP3.C09 I/O_147 J37 5 L5 W20 L1 W27 LCT1_19 XP3.D09 I/O_148 J36 5 L5 W19 L1 W28 LCT1_20 XP3.A10 I/O_149 K39 5 L5 W18 L1 W29 LCT1_21 XP3.B10 I/O_150 K38 5 L5 W17 L1 W30 LCT1_22 XP3.C10 I/O_151 K37 5 L5 W16 L1 W31 LCT1_23 XP3.D10 I/O_152 K36 5 L4 W23 L0 W24 LCT1_24 XP3.A11 I/O_153 L39 5 L4 W22 L0 W25 LCT1_25 XP3.B11 I/O_154 L38 5 L4 W21 L0 W26 LCT1_26 XP3.C11 I/O_155 L37 5 L4 W20 L0 W27 LCT1_27 XP3.D11 I/O_156 L36 5 L4 W19 L0 W28 LCT1_28 XP3.A12 I/O_157 M39 5 L4 W18 L0 W29 LCT1_29 XP3.B12 I/O_158 M38 5 L4 W17 L0 W30 LCT1_30 XP3.C12 I/O_159 M37 5 L4 W16 L0 W31 LCT1_31 XP3.D12 I/O_160 N39 6 L3 W31 L5 W24 LCT1_32 XP3.A13 I/O_161 N38 6 L3 W30 L5 W25 LCT1_33 XP3.B13 I/O_162 N37 6 L3 W29 L5 W26 LCT1_34 XP3.C13 I/O_163 N36 Page 16 of 62

MUX 1st Layer 1st WG 2nd Layer 2nd WG ALCT384 Connector Mezz Card FPGA pin for ALCT384 6 L3 W28 L5 W27 LCT1_35 XP3.D13 I/O_164 P39 6 L3 W27 L5 W28 LCT1_36 XP3.A14 I/O_165 P38 6 L3 W26 L5 W29 LCT1_37 XP3.B14 I/O_166 P37 6 L3 W25 L5 W30 LCT1_38 XP3.C14 I/O_167 P36 6 L3 W24 L5 W31 LCT1_39 XP3.D14 I/O_168 R39 6 L2 W31 L4 W24 LCT1_40 XP3.A15 I/O_169 R38 6 L2 W30 L4 W25 LCT1_41 XP3.B15 I/O_170 R37 6 L2 W29 L4 W26 LCT1_42 XP3.C15 I/O_171 R36 6 L2 W28 L4 W27 LCT1_43 XP3.D15 I/O_172 T39 6 L2 W27 L4 W28 LCT1_44 XP3.A16 I/O_173 T38 6 L2 W26 L4 W29 LCT1_45 XP3.B16 I/O_174 T37 6 L2 W25 L4 W30 LCT1_46 XP3.C16 I/O_175 T36 6 L2 W24 L4 W31 LCT1_47 XP3.D16 I/O_176 U39 7 L1 W39 L3 W32 LCT2_0 XP3.A25 I/O_203 AC37 7 L1 W38 L3 W33 LCT2_01 XP3.B25 I/O_204 AC36 7 L1 W37 L3 W34 LCT2_02 XP3.C25 I/O_205 AC35 7 L1 W36 L3 W35 LCT2_03 XP3.D25 I/O_206 AD39 7 L1 W35 L3 W36 LCT2_04 XP3.A26 I/O_207 AD38 7 L1 W34 L3 W37 LCT2_05 XP3.B26 I/O_208 AD37 7 L1 W33 L3 W38 LCT2_06 XP3.C26 I/O_209 AD36 7 L1 W32 L3 W39 LCT2_07 XP3.D26 I/O_210 AE39 7 L0 W39 L2 W32 LCT2_08 XP3.A27 I/O_211 AE38 7 L0 W38 L2 W33 LCT2_09 XP3.B27 I/O_212 AE37 7 L0 W37 L2 W34 LCT2_10 XP3.C27 I/O_213 AE36 7 L0 W36 L2 W35 LCT2_11 XP3.D27 I/O_214 AF39 7 L0 W35 L2 W36 LCT2_12 XP3.A28 I/O_215 AF38 7 L0 W34 L2 W37 LCT2_13 XP3.B28 I/O_216 AF37 7 L0 W33 L2 W38 LCT2_14 XP3.C28 I/O_217 AF36 7 L0 W32 L2 W39 LCT2_15 XP3.D28 I/O_218 AG39 8 L5 W39 L1 W40 LCT2_16 XP3.A29 I/O_219 AG38 8 L5 W38 L1 W41 LCT2_17 XP3.B29 I/O_220 AG37 8 L5 W37 L1 W42 LCT2_18 XP3.C29 I/O_221 AG36 8 L5 W36 L1 W43 LCT2_19 XP3.D29 I/O_222 AH39 8 L5 W35 L1 W44 LCT2_20 XP3.A30 I/O_223 AH38 8 L5 W34 L1 W45 LCT2_21 XP3.B30 I/O_224 AH37 8 L5 W33 L1 W46 LCT2_22 XP3.C30 I/O_225 AJ39 8 L5 W32 L1 W47 LCT2_23 XP3.D30 I/O_226 AJ38 8 L4 W39 L0 W40 LCT2_24 XP3.A31 I/O_227 AJ37 8 L4 W38 L0 W41 LCT2_25 XP3.B31 I/O_228 AJ36 8 L4 W37 L0 W42 LCT2_26 XP3.C31 I/O_229 AK39 8 L4 W36 L0 W43 LCT2_27 XP3.D31 I/O_230 AK38 8 L4 W35 L0 W44 LCT2_28 XP3.A32 I/O_231 AK37 8 L4 W34 L0 W45 LCT2_29 XP3.B32 I/O_232 AK36 8 L4 W33 L0 W46 LCT2_30 XP3.C32 I/O_233 AL39 8 L4 W32 L0 W47 LCT2_31 XP3.D32 I/O_234 AL38 9 L3 W47 L5 W40 LCT2_32 XP3.A33 I/O_235 AL37 Page 17 of 62

MUX 1st Layer 1st WG 2nd Layer 2nd WG ALCT384 Connector Mezz Card FPGA pin for ALCT384 9 L3 W46 L5 W41 LCT2_33 XP3.B33 I/O_236 AL36 9 L3 W45 L5 W42 LCT2_34 XP3.C33 I/O_237 AM39 9 L3 W44 L5 W43 LCT2_35 XP3.D33 I/O_238 AM38 9 L3 W43 L5 W44 LCT2_36 XP3.A34 I/O_239 AM37 9 L3 W42 L5 W45 LCT2_37 XP3.B34 I/O_240 AM36 9 L3 W41 L5 W46 LCT2_38 XP3.C34 I/O_241 AN39 9 L3 W40 L5 W47 LCT2_39 XP3.D34 I/O_242 AN38 9 L2 W47 L4 W40 LCT2_40 XP3.A35 I/O_243 AN37 9 L2 W46 L4 W41 LCT2_41 XP3.B35 I/O_244 AN36 9 L2 W45 L4 W42 LCT2_42 XP3.C35 I/O_245 AP39 9 L2 W44 L4 W43 LCT2_43 XP3.D35 I/O_246 AP38 9 L2 W43 L4 W44 LCT2_44 XP3.A36 I/O_247 AP37 9 L2 W42 L4 W45 LCT2_45 XP3.B36 I/O_248 AP36 9 L2 W41 L4 W46 LCT2_46 XP3.C36 I/O_249 AR39 9 L2 W40 L4 W47 LCT2_47 XP3.D36 I/O_250 AR38 10 L1 W55 L3 W48 LCT3_0 XP3.A37 I/O_251 AR37 10 L1 W54 L3 W49 LCT3_01 XP3.B37 I/O_252 AR36 10 L1 W53 L3 W50 LCT3_02 XP3.C37 I/O_253 AT39 10 L1 W52 L3 W51 LCT3_03 XP3.D37 I/O_254 AT38 10 L1 W51 L3 W52 LCT3_04 XP3.A38 I/O_255 AV36 10 L1 W50 L3 W53 LCT3_05 XP3.B38 I/O_256 AU36 10 L1 W49 L3 W54 LCT3_06 XP3.C38 I/O_257 AW36 10 L1 W48 L3 W55 LCT3_07 XP3.D38 I/O_258 AV35 10 L0 W55 L2 W48 LCT3_08 XP4.D38 I/O_259 AW35 10 L0 W54 L2 W49 LCT3_09 XP4.C38 I/O_260 AT34 10 L0 W53 L2 W50 LCT3_10 XP4.B38 I/O_261 AU34 10 L0 W52 L2 W51 LCT3_11 XP4.A38 I/O_262 AV34 10 L0 W51 L2 W52 LCT3_12 XP4.D37 I/O_263 AW34 10 L0 W50 L2 W53 LCT3_13 XP4.C37 I/O_264 AT33 10 L0 W49 L2 W54 LCT3_14 XP4.B37 I/O_265 AU33 10 L0 W48 L2 W55 LCT3_15 XP4.A37 I/O_266 AV33 11 L5 W55 L1 W56 LCT3_16 XP4.D36 I/O_267 AW33 11 L5 W54 L1 W57 LCT3_17 XP4.C36 I/O_268 AT32 11 L5 W53 L1 W58 LCT3_18 XP4.B36 I/O_269 AU32 11 L5 W52 L1 W59 LCT3_19 XP4.A36 I/O_270 AV32 11 L5 W51 L1 W60 LCT3_20 XP4.D35 I/O_271 AW32 11 L5 W50 L1 W61 LCT3_21 XP4.C35 I/O_272 AT31 11 L5 W49 L1 W62 LCT3_22 XP4.B35 I/O_273 AU31 11 L5 W48 L1 W63 LCT3_23 XP4.A35 I/O_274 AV31 11 L4 W55 L0 W56 LCT3_24 XP4.D34 I/O_275 AW31 11 L4 W54 L0 W57 LCT3_25 XP4.C34 I/O_276 AT30 11 L4 W53 L0 W58 LCT3_26 XP4.B34 I/O_277 AU30 11 L4 W52 L0 W59 LCT3_27 XP4.A34 I/O_278 AV30 11 L4 W51 L0 W60 LCT3_28 XP4.D33 I/O_279 AW30 11 L4 W50 L0 W61 LCT3_29 XP4.C33 I/O_280 AU29 11 L4 W49 L0 W62 LCT3_30 XP4.B33 I/O_281 AV29 Page 18 of 62

MUX 1st Layer 1st WG 2nd Layer 2nd WG ALCT384 Connector Mezz Card FPGA pin for ALCT384 11 L4 W48 L0 W63 LCT3_31 XP4.A33 I/O_282 AW29 12 L3 W63 L5 W56 LCT3_32 XP4.D32 I/O_283 AT29 12 L3 W62 L5 W57 LCT3_33 XP4.C32 I/O_284 AU28 12 L3 W61 L5 W58 LCT3_34 XP4.B32 I/O_285 AV28 12 L3 W60 L5 W59 LCT3_35 XP4.A32 I/O_286 AW28 12 L3 W59 L5 W60 LCT3_36 XP4.D31 I/O_287 AT27 12 L3 W58 L5 W61 LCT3_37 XP4.C31 I/O_288 AU27 12 L3 W57 L5 W62 LCT3_38 XP4.B31 I/O_289 AV27 12 L3 W56 L5 W63 LCT3_39 XP4.A31 I/O_290 AW27 12 L2 W63 L4 W56 LCT3_40 XP4.D30 I/O_291 AT26 12 L2 W62 L4 W57 LCT3_41 XP4.C30 I/O_292 AU26 12 L2 W61 L4 W58 LCT3_42 XP4.B30 I/O_293 AV26 12 L2 W60 L4 W59 LCT3_43 XP4.A30 I/O_294 AW26 12 L2 W59 L4 W60 LCT3_44 XP4.D29 I/O_295 AT25 12 L2 W58 L4 W61 LCT3_45 XP4.C29 I/O_296 AU25 12 L2 W57 L4 W62 LCT3_46 XP4.B29 I/O_297 AV25 12 L2 W56 L4 W63 LCT3_47 XP4.A29 I/O_298 AW25 The test point assignment is shown below: Test points and LEDs. Pin Name Description TH1-1 Input Enable see InputEnable command in Table 8 for explanation TH1-2 L1A This signal is set to 1 when there was external L1A or internal L1A (if enabled). TH1-3 L1Awindow This signal shows a time window when the trigger data are being saved into the internal memory. It should begin right after L1A and be l1a_window clocks in length. TH1 is the header on the ALCT (near mezzanine board), the name TH1 is written on the board. -1, -2 and -3 are pin numbers in this header. Pins 1 and 2 are marked on the board. The LEDs assignment is shown below: LED Name Description D26 Jstate0 JTAG state machine state bit 0 (please see Table 7 for details) D27 Jstate1 JTAG state machine state bit 1 (please see Table 7 for details) D28 Jstate2 JTAG state machine state bit 2 (please see Table 7 for details) D29 Jstate3 JTAG state machine state bit 3 (please see Table 7 for details) Page 19 of 62

Delay ASIC The Delay ASIC is a full-custom Application-Specific Integrated Circuit that receives 16 differential LVDS inputs from an AFEB and outputs16 single-ended TTL to an LCT FPGA. It has a programmable propagation delay for the outputs, and provides fixed-width output pulses. A special mode can be used to send a pre-loaded set of pattern bits out instead of the normal function. This mode is used for testing connections between the Delay ASICs and other chips. Programming The 4-bit delay shift-register is written by an SPI-like Serial Bus and is common to all 16 channels. One delay step is approximately 2ns, which is determined by the external I delay resistor. The output-pulse width is determined by the Iwidth resistor, and is the same for all 16 channels. I width resistors are chosen to give output pulses in the range of 35ns to 40ns. The order of data bits to send into the chip is: [T1 T4, C1 C16] meaning that T1 is the first and C16 is the last bit to be sent into the chip. T1 T4 are the bits of the code for the delay (Time) setting and C1 C16 are the pattern bits. There are 3/4/7 serial chains from the Slow Control FPGA, each containing six chips that are connected in sequence in the serial chain (Dout from one chip goes to Din of the next). (N.B. on ALCT schematics Outs7 corresponds to Delay ASIC channel 1 Outs0 to ASIC channel 8, Out_0 to ASIC channel 9 Out_7 to ASIC channel 16. Therefore the data for the Pattern mask goes into the chip as [Out_7 Out_0, Outs0 Outs7] ). An example 96-channel group of six Delay ASICs has order [Layers 0-1 W0-7, Layers 2-3 W0-7, Layers 4-5 W0-7, Layers 0-1 W8-15, Layers 2-3 W8-15, Layers 4-5 W8-15], where the first bits end up shifted into 16-channel chip containing Layers 0-1 W0-7 after the total 120 bits have been sent. Within the 16-channel ASIC, the order of channels and their Layer/Wire Group meaning is listed below. The other 96-channel groups are the same but shifted by 16 wires per 96-channel group. Table 5. Map from Delay ASIC channels to Layers and Wire Groups. Delay ASIC Channel ALCT Schematic Example Layer Example Wire Group C16 Out_7 0 7 C15 Out_6 0 6 C14 Out_5 0 5 C13 Out_4 0 4 C12 Out_3 0 3 C11 Out_2 0 2 C10 Out_1 0 1 C09 Out_0 0 0 C08 Outs0 1 0 C07 Outs1 1 1 C06 Outs2 1 2 C05 Outs3 1 3 C04 Outs4 1 4 C03 Outs5 1 5 C02 Outs6 1 6 C01 Outs7 1 7 Page 20 of 62

Delay ASIC Signals Seems that CLRB (CLeaR-Bar signal) normally should be set high when not in use. A negative pulse will clear all internal pattern and delay registers. CHSB (CHip Select Bar signal) should normally be set high when not in use. The front (falling) edge of a negative pulse then allows the rising edge of CLK to clock input data on Din into the serial register. This data is subsequently clocked into the actual working registers on the back (rising) edge of the CHSB pulse. Inn_P, Inn_N Outn Iw Id CHSB CLK Din Dout CLRB SEL Vdd GND Table 6: Delay ASIC Signals Positive/Negative LVDS inputs from AFEB card TTL Outputs to LCT chip, fixed width, programmable delay Output width program current (selected by a resistor to Gnd) Full-scale (maximum) In-to-Out delay program current (selected by a resistor to Gnd) Chip Select input for programming (negative logic) Serial data clock input Serial data input Serial data output Clear-bar, negative logic reset input, sets delay register and pattern mask to 0 Low for normal operation, High for enable output of Pattern register and disable output of data from LVDS inputs. +3.3V Power input Power Return Binning by Maximum Delay The delay ASICs have been found to have large chip-to-chip variation in the maximum time (at code=15). Therefore, the chips are shipped according to various bins corresponding to 2 ns increments in the maximum delay time. These bins and the number of chips found in each bin in the first large batch tested are: 1. 42-44 ns - 25 chips 1.6 ns/div "road" = 3.3 ns 2. 44-46 ns - 85 chips 1.7 ns/div "road" = 4.8 ns 3. 46-48 ns - 150 chips 1.8 ns/div "road" = 4.3 ns 4. 48-50 ns - 185 chips 1.9 ns/div "road" = 4.5 ns 5. 50-52 ns - 290 chips 2.0 ns/div "road" = 4.8 ns 6. 52-54 ns - 330 chips 2.1 ns/div "road" = 4.7 ns 7. 54-56 ns - 586 chips 2.2 ns/div "road" = 4.7 ns 8. 56-58 ns - 373 chips 2.3 ns/div "road" = 4.5 ns 9. 58-60 ns - 99 chips 2.4 ns/div "road" = 4.3 ns Only bins 3-8 will be used (46-58 ns) for ALCT cards, the others will be discarded. Bin 7 chips were the first sent to UCLA. Bin 7&8 chips are used for ALCT-384, Bin 5&6 for ALCT-672, and Bin 3&4 for ALCT-288, adjusting the resistor value to equalize the maximum delay between types of boards. Numbers and percentages of chips required of each type (including spares) versus measurement: Page 21 of 62

Type Number Required Percent Required Bins Used Number Chips in These Bins Percentage of Good Chips ALCT-384 6739 42% 7&8 959 50% ALCT-672 5896 37% 5&6 620 32% ALCT-288 3370 21% 3&4 335 18% Page 22 of 62

General remarks on JTAG Programming The Xilinx FPGAs and FlashRAMs (Eproms) can be programmed via JTAG. They use a separate connector on the PCB for this purpose. An LVDS Xblaster 1 is required to connect the ALCT2001 to a PC parallel port. Xilinx Foundation (Windows-based) software is used to create the programs for the FPGAs and FlashRAMs. Foundation software can be used to download the FPGAs and FlashRAMs as well. Linux-based software has been developed for accessing the control registers as well as downloading (the latter not implemented yet as of 17-Sep-01). There are two general modes of operation: 1. Download the Eproms from a PC. Then FPGAs are loaded automatically from the Eproms every time power is cycled or when a hard reset signal is sent from the TMB. Settings can be specified by directly writing to various configuration registers. This is the normal sequence of operations. 2. Download the FPGA directly. This can be useful during debugging phase when a new program is ready but one does not want to store the potentially faulty information in the Eprom. There are 4 JTAG chains on ALCT2001: Chain 0 is for control registers in the Slow Control FPGA. The chain goes only to this FPGA. Chain 1 is for programming the Slow Control FPGA. Data goes through the FPGA, then the configuration Eprom. The FPGA is put into bypass mode during Eprom programming. Chain 2 is for control registers in the Mezzanine card FPGA. The chain goes only to this FPGA. Chain 3 is for programming the Mezzanine card FPGA. Data goes through the FPGA, then two (or maximum of 3) configuration Eproms. The FPGA is put into bypass mode during Eprom programming. All of the JTAG readable registers are implemented as two sets of identical shift-registers to allow nondestructive readout. The actual shift-register is used to store JTAG-write data, and is used to carry out the selected function. A "shadow" shift-register copies the output bits from its matching actual register. The "shadow" register is shifted-out to TDO during a JTAG read operation, and is over-written by TDI. The actual register remains unaffected. Hot mask register and collision pattern register do not have shadows in the current version of the ALCT Virtex firmware. 1 A custom designed version of Xilinx parallel cable interface that instead of I/O levels that are TTL (requiring a very short cable) uses I/O levels that are translated to LVDS. Page 23 of 62

Xilinx FPGAs The Xilinx FPGA devices detect power-up, and automatically load their programming data from the FlashRAMs in about 40 milliseconds. It is possible to write new programming data to Xilinx FPGAs via JTAG. Jumpers on the ALCT circuit board select whether the FPGAs are included in the programming JTAG chain. Xilinx Flash Memory The Flash Memory devices contain non-volatile programming data for the FPGAs. These devices are written using the LVDS X-blaster. The current ALCT2001-384 boards have only these devices enabled in the Programming JTAG chain. TAP Controller is a custom state machine with 16 states that correspond to the JTAG standard Test Access Port states. Page 24 of 62

Figure 5: TAP State Machine (4-bit TAP controller states indicated). 0000 0001 0010 1001 0011 1010 0100 1011 0101 1100 0110 1101 0111 1110 1000 1111 Page 25 of 62

JTAG TAP States The JTAG TAP state machines used in the LCT and Slow Control FPGAs have 4-bit binary codes assigned to each state. The S0..S3 test points on the PCB indicate the current state of the TAP controller for each FPGA. Hex Table 7: TAP Controller States State Binary Description 0 0000 Test Logic Reset 1 0001 Run Test Idle 2 0010 Select DR Scan 3 0011 Capture DR 4 0100 Shift DR 5 0101 Exit1 DR 6 0110 Pause DR 7 0111 Exit2 DR 8 1000 Update DR 9 1001 Select IR Scan A 1010 Capture IR B 1011 Shift IR C 1100 Exit1 IR D 1101 Pause IR E 1110 Exit2 IR F 1111 Update IR Page 26 of 62

Virtex JTAG Registers Virtex FPGA Instruction Register This registers stores a 5-bit JTAG instruction. Instruction bits are shifted in LSB first from TDI. A fixed bit pattern of B"1001" is shifted out on TDO during the Shift-IR JTAG state to aid in software debugging. (Is this true for AM design?) Concentrator instructions select which one of the configuration registers is placed between TDI and TDO during JTAG data cycles. Instructions and data are shifted in from TDI in the order LSB first. Table 8: Virtex JTAG instructions for ALCT2001. Binary Hex OpCode Description Selected Data Register Length 00000 00 RdID Read ID Register ID Register 40 00001 01 RdHCM Read Hot Channel Mask Hot Channel Mask 288,384,672 2 00010 02 WrHCM Write Hot Channel Mask Hot Channel Mask 288,384,672 2 00110 06 RdCfg Read Configuration Register Configuration Register Shadow 69 00111 07 WrCfg Write Configuration Register Configuration Register 69 00011 03 RdTrig Read Trigger Register Trigger Register Shadow 5 00100 04 WrTrig Write Trigger Register Trigger Register 5 ASIC Delay Write selected chain (see specs of the delay line 01101 0D Wdly control register) Data Register 120 01101 0E Rdly ASIC Delay Read selected chain (see specs of the delay line control register) Data Register 121 10011 13 CollMaskRead Read collision mask register Data Register 168,224,392 2 10100 14 CollMaskWrite Write collision mask register Data Register 168,224,392 2 10101 15 DelayCntrlRead Delay line control register read 5,6,9 2 10110 16 DelayCntrlWrite Delay line control register write 5,6,9 2 10111 17 InputEnable Write this command into the JTAG instruction register to enable input register clock. Used for debugging. No data 11000 18 InputDisable Write this command into the JTAG instruction register to disable input register clock. Used for debugging. No data 11001 19 Yrwrite Output register write. For Output register 31 2 Three numbers are shown for ALCT 288, 384 and 672, respectively. Page 27 of 62

Binary Hex OpCode Description Selected Data Register Length debugging with UCLA test board 11010 1A Osread Output FIFO read. Used for debugging via JTAG and for FAST site operation while TMB is not available Output storage data 49,49,51 3 11111 1F Bypass Bypass Scan Register Bypass Register 1 3 Three numbers are shown for ALCT 288, 384 and 672, respectively. Page 28 of 62

Virtex ID Register This is a 40-bit read-only register that contains fixed information about the Virtex chip, firmware version number, and chip ID number. Typical values are shown below, but the date and version fields can change value whenever the Xilinx logic is re-compiled. The chip ID number is hard-wired on the printed circuit board. Field Bits Table 9: Virtex ID Register Default [Hex] Description [3..0] 4 7 Chip ID number, fixed at 7 [7..4] 4 C Software Version ID [0-F] [23..8] 16 2001 Year: 4 BCD digits [31..24] 8 17 Day: 2 BCD digits [39..32] 8 09 Month: 2 BCD digits Total 40 Page 29 of 62

Virtex Configuration Register This is a read/write shift-register that contains all of the programmable configuration bits for the logic. Field Bits Default [Hex] Table 10: Virtex Configuration Register Name Description Virtex Trigger Modes [1..0] 2 0 trig_mode[1..0] Virtex Trigger Mode: 0 = Pre-Trigger on either Collision muon or Accelerator muon pattern 1 = Only Pre-Trigger on Accelerator muon patterns 2 = Only Pre-Trigger on Collision muon patterns 3 = Pre-Trigger on Collision muons, accelerator muon vetoes Pre-Trigger [2] 1 0 ext_trig_en External Trigger Enable: 0 = disable external trigger 1 = enable external trigger In the external trigger mode, the board monitors the ext_trig input signal. The input data on each clock will be processed only if ext_trig input is ==1 in this clock. Pre-Trigger Controls [15..13] 3 2 nph_thresh[2..0] Number of Planes Hit Threshold for Pre-Trigger Range = 0 to 6 CSC layers If the board encounters nph_thresh or more layers hit in collision or accelerator patterns for a particular key WG, the pattern detection process starts for this particular WG. This event is named pretrigger. Pretriggers for different key WGs are independent and can happen simultaneously. They are not reported to the next stages of the ALCT logic. Pretrigger is used to mark the exact number of the bunch-crossing when the track crossed the chamber. [18..16] 3 4 nph_pattern[2..0] Pattern hits required after drift delay to allow an LCT-trigger Range = 0 to 6 CSC layers If there was a pretrigger for a key WG, drift_delay clocks later the board counts the layers hit in the patterns for this key WG again. If the number of layers hit in one of the patterns is equal or more than nph_pattern, this event is reported to the next stages of trigger logic. This event is named trigger. Triggers for different key WGs are independent and can happen simultaneously [20..19] 2 3 drift_delay[1..0] Drift delay after pre-trigger, 25n steps Range = 0 to 3 [0 to 75ns] See description of nph_pattern parameter for explanation. Raw Hits FIFO Controls [25..21] 5 7 fifo_tbins[4..0] Total number of FIFO time bins per wire group Range = 0 to 31 decimal [25ns steps] [30..26] 5 1 fifo_pretrig[4..0] FIFO time bins before trigger [included in total] Range = 0 to 31 decimal [25ns steps] Raw hits dump in DAQ readout will show the raw hits starting from the moment of time (fifo_pretrig 12) clocks before the trigger event. The total number of time bins in DAQ readout is determined by fifo_tbins parameter. [32..31] 2 1 fifo_mode[1..0] FIFO Mode 0 = No raw hits dump 1 = Full dump [all LCT chips] 2 = Local dump [only LCT chips with hits] (not yet implemented) Page 30 of 62

Field Bits Default [Hex] Table 10: Virtex Configuration Register (Continued) Name Description Level 1 Accept [43..36] 8 78h l1a_delay[7..0] Level 1 Accept delay after trigger Range = 0 to 255 decimal L1A signal is expected in the time window from l1a_delay to l1a_delay+ l1a_window clocks after the trigger event. If L1A arrives in this window, the DAQ data for this trigger event will be reported during DAQ readout. [47..44] 4 3 l1a_window[3..0] Level 1 Accept window width [25ns steps] See description of l1a_delay parameter. [51..48] 4 0 l1a_offset[3..0] Level 1 Accept counter Pre-Load value [arbitrary value] Range = 0 to F hex [52] 1 0 l1a_internal L1A generated internally during L1A window 0 = L1A comes from CCB via TMB 1 = L1A generated internally in L1A window for each track found in any key WG. Board ID, BXN, CCB [55..53] 3 5 board_id[2..0] ALCT2001 circuit board ID [arbitrary value] Range = 0 to 7 ALCT-Bus [65..64] 2 0 alct_amode[1..0] ALCT Accelerator Muon Mode [affects all LCT chips] 0 = Ignore accelerator muons [give them pattern 0] 1 = Prefer Collision-muons by adding Promotion bit to them 2 = Prefer Accelerator-muons by adding Promotion bit to them 3 = Ignore Collision muons [give them pattern 0] [67] 1 1 trig_info_en 0 = do not write trigger information to the output FIFO. ALCT output will be written into the output FIFO only when DAQ readout is in progress. 1 = write trigger information to the output FIFO. If the valid track is detected in this clock, the entire ALCT output is written into the output FIFO. Please see Output FIFO section of this document. [68] 1 0 sn_select Selector of the serial number device to read via JTAG: 0 = ALCT serial number 1 = Mezz card serial number Total 69 Page 31 of 62

Virtex Trigger Register is a 5-bit read/write shift-register that generates various internal triggers. During a register-read instruction, the "shadow" copy of the actual Trigger Register is shifted out on JTAG TDO, so the read operation is non-destructive. Data in bits 1, 0 Table 11: Virtex Trigger Register Description Binary Hex 00 0 Do Nothing 11 3 Self-generate External Test Pulse (AFEB) Data in bits 2, 3 Binary Hex 00 0 Pulse generated with the JTAG command goes to test pulse output (see table above) 01 1 Adb_sync_pulse goes to test pulse output 10 2 Adb_async_pulse goes to test pulse output 11 3 External test pulse signal from LEMO connector goes to test pulse output Data bit 4 if set to 1 inverts the test pulse output. Description Page 32 of 62

Virtex Bypass Register is a 1-bit read/write shift-register that is inserted between TDI and TDO when no other registers have been selected, or when the Bypass instruction is selected. Hot Channel Mask Register is a 288, 384 for 672-bit register setting the hot channel mask. Bits Default state Layer HCmask[ n-1: 0] All 1s 1 HCmask[2n-1: n] All 1s 2 HCmask[3n-1:2n] All 1s 3 HCmask[4n-1:3n] All 1s 4 HCmask[5n-1:4n] All 1s 5 HCmask[6n-1:5n] All 1s 6 n in this table is 48 for ALCT-288, 64 for ALCT-384, 112 for ALCT-672 Delay Line Register. There are 3,4 or 7 4 chains by 6 delay lines each connected to Virtex FPGA. The selection which chain to work with is done using the Delay line control register (see section below). Please use the alct_fast_lib.c function alct_download_delay to write the delay codes and patterns into them. See the description of this library for details. Delay line control register. This is the 5,6 or 9-bit 4 register which selects which delay line chain you are working with, and allows to set or reset the control signals common for all delay lines. Format of this register is shown below: {cs_dly[(2,3,6 4 ):0], settst_dly, rs_dly} cs_dly settst_dly rs_dly chain-select signals settst signal common for all delay lines reset signal common for all delay lines Please use the function alct_download_delay from alct_fast_lib.c library to write the delay codes and patterns into them. This library handles the Delay line and control registers correctly. See the description of this library for details. Collision mask register is accepting 6,8 or 14 4 28-bit masks. Mask 0 is working for WG 0-7, mask 1 for WG 8-15, and so on, one mask for 8 WGs. Each mask contains 14 bits for each of the two possible collision patterns. The bit mapping for the first collision mask is shown below: 4 Three numbers are shown for ALCT 288, 384 and 672, respectively. Page 33 of 62

Pattern A: ly0 2 1 0 ly1 4 3 ly2 5 ly3 7 6 ly4 10 9 8 ly5 13 12 11 Pattern B: ly0 16 15 14 ly1 18 17 ly2 19 ly3 21 20 ly4 24 23 22 ly5 27 26 25 As you can see, the table forms the shape of the envelope of all possible patterns. The numbers are the bit positions in the collision mask, responsible for this particular hit in the pattern. Setting some of the mask bits to 0 you can disable the corresponding hits and make the FPGA analyze only the enabled hits, forming any pattern in the limits of the envelope. This can also be used for disabling some layers completely. Default is all 1s. Please see algorithm description section for details. Output register was designed to be used with the UCLA test board. It allows to set any combination of bits on the output of the ALCT, so it can be written into the test board. Format of this register is shown below: {YRenable, YRadd, YRd, YRO, YRX, YRS_B, YRI, YRIclkEn} All names and lengths of the fields correspond to the names of the inputs of the UCLA test board with the YR prefix, except: YRenable this one-bit signal if set to 1 makes ALCT output the contents of the output register instead of the normal outputs. YRIclkEn if set to 1, YRI bit outputs the 40 MHz clock for the test board, otherwise it outputs whatever is written into YRI field. Please see the UCLA test board design documents for details. Output FIFO is used to log any relevant output data coming from ALCT. Whatever appears on the output connectors of ALCT triggering information, DAQ readout information is simultaneously written into this FIFO, but only if valid bit is set for the best muon or DAQ readout is in progress, or both conditions are met simultaneously. OSread command allows to read one 49-bit word from this FIFO at a time. The format of this word is shown below: Page 34 of 62

Name Description Bit position FIFOempty If equal to 1 than FIFO is empty. Typically used for polling MSB FIFO. FirstAcceleratorFlag Shows if the first best track is accelerator track FirstQuality[1:0] Quality of the first best track FirstKeyWG[(5,5,6 5 ):0] Key wire group of the first best track FirstPatternB If equal to 1 and FirstAcceleratorFlag == 0, collision pattern B was found for this track, otherwise pattern A SecondAcceleratorFlag Shows if the second best track is accelerator track SecondQuality[1:0] Quality of the second best track SecondKeyWG[(5,5,6 5 ):0] Key wire group of the second best track SecondPatternB If equal to 1 and SecondAcceleratorFlag == 0, collision pattern B was found for this track, otherwise pattern A DAQinfo[18:0] DAQ readout information. See Table 12 for details. bxn[8:0] Bunch crossing counter LSB Output FIFO write operation is enabled if: YRIclkEnr is set to 1 (see output register description) AND Input clock is enabled (see Table 8, InputEnable command). Triggering information is written into the FIFO only if trig_info_en bit of the configuration register is set to 1 (see Table 11). Output FIFO depth is 1023 words, which allows reading the DAQ information for up to 10 time bins. If output FIFO is used for DAQ readout, fifo_tbins parameter in the configuration register should be less of equal to 10. 5 Three numbers are shown for ALCT 288, 384 and 672, respectively. Page 35 of 62

DAQ data format for ALCT2001 Table 12 ALCT DAQ data format Frm # 18 /wr 17 DAV 16 last 15 ddu 14 Spcl 13 d13 first 12 d12 last 11 d11 abrt 10 d10 FIFO Control LCT Ctrl + Data LCT Data 1 DAV - - - - - - - - - - - - - - - - - 0 0 DAV 0 0 1 1 0 0 Board ID [2..0] CSC ID [3..0] L1A Number [3..0] 1 0 DAV 0 0 0 Reserved 2nd 1st Ext L1A # Time Bins [4..0] FIFO Mode 2 0 DAV 0 0 0 Reserved Full BXN [11..0] 3 0 DAV 0 0 0 Active LCT chips [6..0] LCT chips Read Out [6..0] 4 0 DAV 0 0 LCT0 [14..0] 5 0 DAV 0 0 LCT0 [29..14] 6 0 DAV 0 0 LCT1 [14..0] 7 0 DAV 0 0 LCT1 [29..0] 8 0 DAV 0 0 LCT Chip 0 Tbin 0 Ly0[7..0] 9 0 DAV 0 0 LCT Chip 0 Tbin 0 Ly0[15..8] 10 0 DAV 0 0 LCT Chip 0 Tbin 0 Ly1[7..0] 11 0 DAV 0 0 LCT Chip 0 Tbin 0 Ly1[15..8] 12 0 DAV 0 0 LCT Chip 0 Tbin 0 Ly2[7..0] 13 0 DAV 0 0 LCT Chip 0 Tbin 0 Ly2[15..8] 14 0 DAV 0 0 LCT Chip 0 Tbin 0 Ly3[7..0] 15 0 DAV 0 0 LCT Chip 0 Tbin 0 Ly3[15..8] 16 0 DAV 0 0 LCT Chip 0 Tbin 0 Ly4[7..0] 17 0 DAV 0 0 LCT Chip 0 Tbin 0 Ly4[15..8] 18 0 DAV 0 0 LCT Chip 0 Tbin 0 Ly5[7..0] 19 0 DAV 0 0 LCT Chip 0 Tbin 0 Ly5[15..8] -- -- -- 236 0 DAV 0 0 LCT Chip 3 Tbin 4 Ly0[7..0] 237 0 DAV 0 0 LCT Chip 3 Tbin 4 Ly0[15..8] 238 0 DAV 0 0 LCT Chip 3 Tbin 4 Ly1[7..0] 239 0 DAV 0 0 LCT Chip 3 Tbin 4 Ly1[15..8] 240 0 DAV 0 0 LCT Chip 3 Tbin 4 Ly2[7..0] 241 0 DAV 0 0 LCT Chip 3 Tbin 4 Ly2[15..8] 242 0 DAV 0 0 LCT Chip 3 Tbin 4 Ly3[7..0] 243 0 DAV 0 0 LCT Chip 3 Tbin 4 Ly3[15..8] 244 0 DAV 0 0 LCT Chip 3 Tbin 4 Ly4[7..0] 245 0 DAV 0 0 LCT Chip 3 Tbin 4 Ly4[15..8] 246 0 DAV 0 0 LCT Chip 3 Tbin 4 Ly5[7..0] 247 0 DAV 0 0 LCT Chip 3 Tbin 4 Ly5[15..8] 248 0 DAV 0 0 0 0 0 0 CRC [10:0] 249 0 DAV 0 0 0 0 0 0 CRC[21:11] 250 0 DAV 0 0 0 0 0 Evener: "E0D" Hexadecimal [11..0] 251 0 DAV 1 1 1 0 1 0 A=0 Frame Count [9..0] 1 DAV - - - - - - - - - - - - - - - - - 9 d9 8 d8 7 d7 6 d6 5 d5 4 d4 3 d3 2 d2 1 d1 0 d0 Page 36 of 62

1. The data format shown above will be modified. This is the version which was prepared for beam test in May 2003. 2. DAV bit is not related to DAQ format anymore. It is set to one 17 clocks after L1A was received if ALCT has valid DAQ data for this L1A. 3. CRC is calculated for data bits [15:0] using the following parameters: Poly = 10000000000000000000011 Data width = 16 CRC width = 22 CRC init = 0 Data bit first = MSB Evener and frame count are not included into CRC. Frame count includes CRC words. 4. LCT chip field is two-bit wide. For ALCT672, however, it should change from 0 to 6 that requires 3 bits. For compatibility with ALCT2000, this field is left untouched, and in ALCT 672 DAQ data it changes as shown below: 0,1,2,3,0,1,2 5. LCT0 and LCT1 fields format is shown below: Table 13 Two best muons LCT data Bits Name Description 0 Valid This track is valid if this bit is 1 2:1 Quality Quality of the track 3 Accelerator muon This track is detected as accelerator pattern if this bit is 1 4 Pattern B This track is detected by pattern B if this bit is 1, otherwise it is detected by pattern A. 11:5 Key wiregroup number Shows what key wiregroup detected this pattern 16:12 Bxn Five low bits of the bunch-crossing number. 29:17 Reserved ALCT-2001 algorithm description. This section describes the basics of the ALCT-384-2001 algorithm, which is implemented in XCV600E FPGA for ALCT288, ALCT384, and XCV100E for ALCT672. This description is provided only for the reference for program model writers, and does not include some information (timing, some control registers, DAQ readout description, etc.). The algorithm is pipelined. Shown below are the steps of this pipeline: 1. One-shots. Page 37 of 62

One-shots detect the rising edge on each of the 288,384 or 672 input bits, and start the output pulse at this moment. The output pulse duration is 6 clocks (150 ns). This is used to allow any drifting ions created by the charged particle to reach the wires. 2. Pattern detectors The outputs of the one-shots are supplied to the pattern detectors. There are 48,64 or 112 of them because there are as many key wire groups for which the patterns can be found. Each pattern detector can detect the following patterns: Two programmable collision patterns (A and B) One fixed accelerator pattern The input data for the collision pattern detector are selected as shown below: n-2 n-1 n Layer 1 n-1 n Layer 2 n Layer 3 n n+1 Layer 4 n n+1 n+2 Layer 5 n n+1 n+2 Layer 6 n in this diagram is the key wire group number, which this particular pattern detector is searching the patterns for. As you can see, the input bits form the pattern envelope identical to the pattern used in the ALCT-2000 design. The programming of the two programmable collision patterns A and B is implemented as a simple masking-out of the bits, which we do not want to include in the pattern. Shown below is the pseudo-language formula for pattern detection: number of layers hit for collision pattern A or B = (L1[n-2]& m1) (L1[n-1]& m2) (L1[n] & m3) + (L2[n-1]& m4) (L2[n] & m5) + (L3[n] & m6) + (L4[n] & m7) (L4[n+1]& m8) + (L5[n] & m9) (L5[n+1]& m10) (L5[n+2]& m11) + (L6[n] & m12) (L6[n+1]& m13) (L6[n+2]& m14) ; Lx in this expression means Layer x, [y] means bit y (from the layer), mz means collision pattern A or B mask bit z. The user can program different masks for collision patterns A and B. The accelerator pattern is a vertical pattern which cannot be reprogrammed. The formula for it looks like this (see formula for collision pattern diagram above for explanation): number of layers hit in the accelerator pattern = L1[n] + L2[n] + L3[n] + L4[n] + L5[n] + L6[n] ; Each pattern detector reports the number of the layers hit in collision and accelerator patterns minus (nph_pattern - 1) value. These outputs are called quality of track (see explanation below). One collision and one accelerator pattern are reported. The patb output bit shows which collision pattern (A or B) was found. There are several parameters, which the user can adjust, that change the functionality of the pattern detector. They are described in this document, Table 10. Their names are: trig_mode nph_thresh nph_pattern drift_delay 3. Ghost Cancellation Logic (GCL) Page 38 of 62

The outputs of the pattern detectors are connected to the ghost cancellation logic. This block is totally new to ALCT-2001 design, it was not present in the ALCT-2000. Tracks passing through the chamber often get registered by two or more pattern detectors, especially if the user programmed wide patterns. This way the ghost track(s) are reported along with the actual track. To avoid that, GCL analyzes the pattern detector s outputs, and the ghost gets cancelled if: There is track in the neighboring key wire group This other track has better quality than the ghost This other track was detected in the same clock or up to 4 clocks before the ghost Please note that if the ghost and the actual track have the same quality, nothing is cancelled, because the algorithm does not know which track is a ghost. (We are still thinking how to improve that) The cancellation is done separately for collision and accelerator patterns. 4. Best track selector. The outputs of the GCL are connected to the best track selector, which simply selects the track with the best quality. The algorithm for it is directly borrowed from the ALCT-2000 design. 5. Track promotion. The best collision and accelerator tracks that are found in the previous step are modified according to the following configuration variable: alct_amode Please see Table 10 for details. 6. Mask out the best track. This step just masks out the best track in the data coming from pattern detectors, so the next steps can search for the second best track. 7. Second best track selection and promotion. This step repeats steps 4 and 5 for the second best track. Finally, the following parameters for each of the two best tracks are reported to the output of the board: Quality of track Key wire group Pattern B flag (0 means pattern A was found, 1 means pattern B) Accelerator muon flag (1 means accelerator pattern was found) Page 39 of 62

Slow Control JTAG Programming Slow Control Instruction Register This stores a 6-bit JTAG instruction. Instruction bits are shifted in LSB first from TDI. A fixed bit pattern of B"100001" is shifted out on TDO during the Shift-IR JTAG state to aid in software debugging. Slow Control instructions select either one of the configuration registers or the Serial Bus to be placed between TDI and TDO during JTAG data cycles. Page 40 of 62 Table 14: Slow Control JTAG Instruction Op Codes Op Code Selected Op Code Description Chip Select Length Binary Octal Register 000 000 00 RdID Read ID Register None ID Register 40 000 001 01 WThrs Reset Threshold DAC /thr_reset Bypass 1 000 010 02 DRst Reset Delay ASIC /dly_reset Bypass 1 000 100 03 WTp Write Test Pulse DAC /cs_test_pulse Serial Bus 8 001 000 10 WThr0 Write Threshold DAC 0 /cs_write_thr0 Serial Bus 12 001 001 11 WThr1 Write Threshold DAC 1 /cs_write_thr1 Serial Bus 12 001 010 12 WThr2 Write Threshold DAC 2 /cs_write_thr2 Serial Bus 12 001 011 13 WThr3 Write Threshold DAC 3 /cs_write_thr3 Serial Bus 12 010 000 20 RThr0 Read Threshold ADC 0 /cs_read_thr0 Serial Bus 10 010 001 21 RThr1 Read Threshold ADC 1 /cs_read_thr1 Serial Bus 10 010 010 22 RThr2 Read (shared) ADC 2 /cs_read_thr2 Serial Bus 10 010 011 23 RThr3 Read Threshold ADC 3 /cs_read_thr3 Serial Bus 10 010 100 24 RThr4 Read Threshold ADC 4 /cs_read_thr4 Serial Bus 10 011 000 30 WDly0 Write Delay ASIC Grp0 /cs_write_dly0 Serial Bus 24 011 001 31 WDly1 Write Delay ASIC Grp1 /cs_write_dly1 Serial Bus 24 011 010 32 WDly2 Write Delay ASIC Grp2 /cs_write_dly2 Serial Bus 24 011 011 33 WDly3 Write Delay ASIC Grp3 /cs_write_dly3 Serial Bus 24 011 100 34 WDly4 Write Delay ASIC Grp4 /cs_write_dly4 Serial Bus 24 011 101 35 WDly5 Write Delay ASIC Grp5 /cs_write_dly5 Serial Bus 24 011 110 36 WDly6 Write Delay ASIC Grp6 /cs_write_dly6 Serial Bus 24 100 000 40 WTpg Write Test Pulse Group None tp_group[] 7 100 001 41 RTpg Read Test Pulse Group None tp_group[] 7 100 010 42 WTps Write Test Pulse Strip None tp_strip[] 6 100 011 43 RTps Read Test Pulse Strip None tp_strip[] 6 100 100 44 WSbr Write Standby Register None /standby[] 42 100 101 45 RSbr Read Standby Register None /standby[] 42 100 110 46 WTpd Write TP Power Down None /tp_pd[] 1 100 111 47 RTpd Read TP Power Down None /tp_pd[] 1 111 111 77 Bypass Bypass Scan None Bypass 1

Slow Control ID Register is a 40-bit read-only register that contains fixed information about the Slow Control chip, Altera logic, and chip ID number. Typical values are shown below, but the date and version fields can change value whenever the Altera logic is re-compiled. The chip ID number is hardwired on the printed circuit board. Field Table 15: Slow Control ID Register Bits Default [Hex] Description [3..0] 4 8 Chip ID number, fixed at 8 [7..4] 4 B Software Version ID [0-F] [23..8] 16 2001 Year: 4 BCD digits [31..24] 8 09 Day: 2 BCD digits [39..32] 8 07 Month: 2 BCD digits Total 40 Reset Threshold DAC pulses /thr_reset to send a 1 TCK-wide pulse to reset the threshold DACs to their mid-range setting (127 counts = 1.240V). The 1-bit Bypass Register is inserted between TDI and TDO. Reset Delay ASIC pulses /dly_reset to send a 1 TCK-wide pulse to reset the Delay ASICs to 0 delay time. The 1-bit Bypass Register is inserted between TDI and TDO. Write Test Pulse DAC asserts /cs_test_pulse and connects the JTAG bus to the Slow Control Serial Bus. The Serial Bus is inserted between TDI and TDO. This 8-bit DAC controls the amplitude of the Analog Test Pulse sent to the AFEBs. 1 LSB = 2.500V/256 = 9.8mV and V(n)=2.500V * n/256,where n=0..255. Write Threshold DAC(i, i=0..3) asserts /cs_write_thr(i) and connects the JTAG bus to the Slow Control Serial Bus. The Serial Bus is inserted between TDI and TDO. These 8-bit DACs control the amplitude of the AFEB threshold voltage. 1 LSB = 2.500V/256 = 9.8mV and V(n)=2.500V * n/256, where n=0..255. The DACs are organized as 12 channels of 12 data bits per DAC-chip. The 12 data bits contain 8 DAC data bits [7..0] and 4 DAC address bits [11..8]. The DACs use the SPI data format, which sends the MSB first (JTAG is LSB first). See the manufacturers data sheet for more detail (Texas Instruments, www.ti.com, device TLC542DW) Page 41 of 62

DAC Chip Ch AFE B Table 16: Threshold DAC Channel Assignments 6 DAC Chip Ch AFE B DAC Chip Ch AFE B DAC Chip DAC0 0 0 DAC1 0 12 DAC2 0 24 DAC3 0 36 DAC0 1 1 DAC1 1 13 DAC2 1 25 DAC3 1 37 DAC0 2 2 DAC1 2 14 DAC2 2 26 DAC3 2 38 DAC0 3 3 DAC1 3 15 DAC2 3 27 DAC3 3 39 DAC0 4 4 DAC1 4 16 DAC2 4 28 DAC3 4 40 DAC0 5 5 DAC1 5 17 DAC2 5 29 DAC3 5 41 DAC0 6 6 DAC1 6 18 DAC2 6 30 DAC3 6 DAC0 7 7 DAC1 7 19 DAC2 7 31 DAC3 7 DAC0 8 8 DAC1 8 20 DAC2 8 32 DAC3 8 DAC0 9 9 DAC1 9 21 DAC2 9 33 DAC3 9 DAC0 10 10 DAC1 10 22 DAC2 10 34 DAC3 10 DAC0 11 11 DAC1 11 23 DAC2 11 35 DAC3 11 Ch AFE B Read Threshold ADC(i, i=0..4) asserts /cs_read_thr(i) and connects the JTAG bus to the Slow Control Serial Bus. The Serial Bus is inserted between TDI and TDO. These 10-bit ADCs read-back digitized AFEB threshold voltages, power supply voltages, currents, and the on-board temperature. 1 LSB = 2.500V/1023 = 9.8mV and V(n)=2.500V * n/1023, where n=0..1023. The ADCs are organized as 12 channels of 10 data bits per ADC-chip. Only 11 channels are available for ALCT voltages, the 12 th channel reads the ADC internal reference voltage. As the 10 data bits are shifted out to the Serial Bus (MSB first), the 4-bit address for the next channel to be read is shifted in (along with 6 dummy bits. The ADCs use the SPI data format, which sends the MSB first (JTAG is LSB first). For more detail, see the manufacturers data sheet (Analog Devices, www.analogdevices.com, device AD8802AR). ADC chips 3 and 4 are not implemented on ALCT2001-384, and their signals are not defined. 6 Only DAC0 and DAC1 are implemented on ALCT2001-384 Page 42 of 62

Table 17: ADC Channel Assignments. Chip Ch Function Conversion ADC0 0 AFEB 23 Threshold 1 ADC mv = 1 DAC mv ADC0 1 AFEB 22 Threshold 1 ADC mv = 1 DAC mv ADC0 2 AFEB 21 Threshold 1 ADC mv = 1 DAC mv ADC0 3 AFEB 20 Threshold 1 ADC mv = 1 DAC mv ADC0 4 AFEB 19 Threshold 1 ADC mv = 1 DAC mv ADC0 5 AFEB 18 Threshold 1 ADC mv = 1 DAC mv ADC0 6 AFEB 17 Threshold 1 ADC mv = 1 DAC mv ADC0 7 AFEB 16 Threshold 1 ADC mv = 1 DAC mv ADC0 8 AFEB 15 Threshold 1 ADC mv = 1 DAC mv ADC0 9 AFEB 14 Threshold 1 ADC mv = 1 DAC mv ADC0 10 AFEB 13 Threshold 1 ADC mv = 1 DAC mv ADC1 0 AFEB 12 Threshold 1 ADC mv = 1 DAC mv ADC1 1 AFEB 11 Threshold 1 ADC mv = 1 DAC mv ADC1 2 AFEB 10 Threshold 1 ADC mv = 1 DAC mv ADC1 3 AFEB 9 Threshold 1 ADC mv = 1 DAC mv ADC1 4 AFEB 8 Threshold 1 ADC mv = 1 DAC mv ADC1 5 AFEB 7 Threshold 1 ADC mv = 1 DAC mv ADC1 6 AFEB 6 Threshold 1 ADC mv = 1 DAC mv ADC1 7 AFEB 5 Threshold 1 ADC mv = 1 DAC mv ADC1 8 AFEB 4 Threshold 1 ADC mv = 1 DAC mv ADC1 9 AFEB 3 Threshold 1 ADC mv = 1 DAC mv ADC1 10 AFEB 2 Threshold 1 ADC mv = 1 DAC mv ADC2 0 AFEB 1 Threshold 1 ADC mv = 1 DAC mv ADC2 1 AFEB 0 Threshold 1 ADC mv = 1 DAC mv ADC2 2 Current +1.8V ADC2 3 Current +3.3V ADC2 4 Current +5.5V_1 ADC2 5 Current +5.5V_2 ADC2 6 Voltage +1.8V ADC2 7 Voltage +3.3V ADC2 8 Voltage +5.5V_1 ADC2 9 Voltage +5.5V_2 ADC2 10 Temperature Tc=25+100*(Vadc-0.750V) ADC3 0 AFEB 24 Threshold? 1 ADC mv = 1 DAC mv ADC3 1 AFEB 25 Threshold? 1 ADC mv = 1 DAC mv ADC3 2 AFEB 26 Threshold? 1 ADC mv = 1 DAC mv ADC3 3 AFEB 27 Threshold? 1 ADC mv = 1 DAC mv ADC3 4 AFEB 28 Threshold? 1 ADC mv = 1 DAC mv ADC3 5 AFEB 29 Threshold? 1 ADC mv = 1 DAC mv ADC3 6 AFEB 30 Threshold? 1 ADC mv = 1 DAC mv ADC3 7 AFEB 31 Threshold? 1 ADC mv = 1 DAC mv ADC3 8 AFEB 32 Threshold? 1 ADC mv = 1 DAC mv ADC3 9 AFEB 33 Threshold? 1 ADC mv = 1 DAC mv ADC3 10 AFEB 34 Threshold? 1 ADC mv = 1 DAC mv ADC4 0 AFEB 35 Threshold? 1 ADC mv = 1 DAC mv ADC4 1 AFEB 36 Threshold? 1 ADC mv = 1 DAC mv ADC4 2 AFEB 37 Threshold? 1 ADC mv = 1 DAC mv ADC4 3 AFEB 38 Threshold? 1 ADC mv = 1 DAC mv ADC4 4 AFEB 39 Threshold? 1 ADC mv = 1 DAC mv ADC4 5 AFEB 40 Threshold? 1 ADC mv = 1 DAC mv ADC4 6 AFEB 41 Threshold? 1 ADC mv = 1 DAC mv ADC4 7? ADC4 8? ADC4 9? ADC4 10? Page 43 of 62

Write Delay ASIC Group(i, i=0..6) asserts /cs_write_dly(i) and connects the JTAG bus to the Slow Control Serial Bus. The Serial Bus is inserted between TDI and TDO, and writes delay times into the Delay ASICs. The ASICs have 4-bit serial registers that use the same MSB-first SPI data format as the DACs and ADCs. Groups of 6 Delay ASICs make up a 24-bit serial chain, with the lowest numbered chip at the start of the chain. The full-scale delay is determined by external resistors, and is nominally 32ns. The output pulse width also is determined by external resistors, and is about 35ns. Table 18: Delay ASIC Group Assignments 7 24-bit AFEBs In Group Group 0 AFEB 0-5 1 AFEB 6-11 2 AFEB 12-17 3 AFEB 18-23 4 AFEB 24-29 5 AFEB 30-35 6 AFEB 36-41 Write Test Pulse Group stores the bits tp_group[] to specify which groups are enabled for the Analog Test Pulse. The Analog Test pulse is initiated either by an external TTL signal or by a command to the Virtex Chip (for synchronization to the 40MHz clock). Individual AFEBs can not be selected to receive the Test Pulse, but instead are arranged in groups of 6: Table 19: Analog Test Pulse AFEB Group Assignments Group 0 AFEBs 00,01,02, 12,13,14 Group 1 AFEBs 03,04,05, 15,16,17 Group 2 AFEBs 06,07,08, 18,19,20 Group 3 AFEBs 09,10,11, 21,22,23 Group 4-6 Not implemented on ALCT2001-384 Read Test Pulse Group is a non-destructive readout of a copy of the bits stored in the tp_group[] register. Bits shifted in by JTAG TDI are ignored. Write Test Pulse Strip stores the bits tp_strip[] to specify which CSC Anode strips are enabled for the Analog Test Pulse. The register bits are mapped one-to-one with the Pulse Strips. 7 Only groups 0..3 are implemented on ALCT2001-384 Page 44 of 62

Read Test Pulse Strip is a non-destructive readout of a copy of the bits stored in the tp_strip[] register. Bits shifted in by JTAG TDI are ignored. Write Standby Register stores the bits /standby[]. Logic 0 shuts down the Anode Discriminator Board power regulator for the selected boards. The register bits are mapped one-to-one with the AFEB cards. Read Standby Register is a non-destructive readout of a copy of the bits stored in the /standby[] register. Bits shifted in by JTAG TDI are ignored. Write TP Power Down stores the Test Pulse Generator control bit /tp_pd[]. Logic 0 shuts down the Test Pulse Generator. Read TP Power Down is a non-destructive readout of a copy of the bit stored in the /tp_pd[] register. Bits shifted in by JTAG TDI are ignored. Bypass Scan is a 1-bit read/write shift-register that is inserted between TDI and TDO when no other registers have been selected. Page 45 of 62

Configuration Jumpers Various configuration options can be selected with the 3-pin PCB jumpers. Shorting plugs ("shunts") are used to connect either pins 1 and 2 or pins 2 and 3: Table 20: ALCT2001 PCB Jumpers. Jumper Schematics Section Short 1-2 Short 2-3 SW1 Digital Part Clock comes from on-board crystal SW2 SCSI Connectors JTAG chain select bit 0 from Xblaster or TMB. SW3 SCSI Connectors JTAG chain select bit 1 from SW4 Mezzanine Card Connectors Xblaster or TMB. LEDs D10-D29 are enabled Clock comes from Clk_Main from TMB JTAG chain select bit 0 held low. JTAG chain select bit 1 held low. LEDs D10-D29 are disabled Note that at SW2 and SW3 the connection from Xblaster at pin 1 must be cut if you want to select individual chains using the jumpers, as for instance when using Windows/Foundation software. Our Linux software doesn t require this mutilation. Page 46 of 62

ALCT2001 Connectors Listed below (Table 21) is a summary of the signals grouped by type, not including AFEB or test pulse signals. Table 21: ALCT2001 Input/Output Signals. Type Number Direction Description 27 Out Trigger path. Synchronous outputs, 20 Out DAQ path. multiplexed at 80 MHz 5 Out Synchronous control outputs. Synchronous inputs, multiplexed at 80 MHz 16 In Synchronous control inputs. Asynchronous inputs 4 In Asynchronous Clock and Control signals. 3 In JTAG (TCK, TMS, TDI) JTAG I/O 1 Out JTAG (TDO) 3 In Chain select. Listed below (Table 22) is a summary of all of the external connections to the ALCT2001 board. Following sections describe the signals on each connector in detail. Table 22: ALCT2001 Connectors ID Pins Type Function J1 10 Header Xilinx LVDS X-Blaster (prototype was J8) J2 8 Power Header Power Supply Input (was J7) J3 1 LEMO Coax External Test Pulse Trigger Input (was J12) J4 50 SCSI TMB Cable 2 (was J11) J5 50 SCSI TMB Cable 1 (was J10) J6 1 LEMO Coax Strip 0 Test Pulse Output (was J1) J7 1 LEMO Coax Strip 1 Test Pulse Output (was J2) J8 1 LEMO Coax Strip 2 Test Pulse Output (was J3) J9 1 LEMO Coax Strip 3 Test Pulse Output (was J4) J10 1 LEMO Coax Strip 4 Test Pulse Output (was J5) J11 1 LEMO Coax Strip 5 Test Pulse Output (was J6) J12 40 Header AFEB-0 I/O (was J13) J29 40 Header AFEB-17 I/O (was J30) OR (384-channel variant). J35 40 Header AFEB-23 I/O (was J36) OR (672-channel variant). J53 40 Header AFEB-41 I/O (was J54) Page 47 of 62

J1 Xilinx LVDS X-Blaster Connector Function: connects ALCT2001 to LVDS X-Blaster for programming FPGAs and PROMs. The LVDS signals and voltage sources on this connector are not directly compatible with the standard Xilinx programming cable. The X-Blaster is a small card that connects a PC parallel port (TTL-level signals) to these LVDS-level signals. The names of the signals are TCK, TMS, TDI (input), TDO (output), and SEL(1:0). The SEL is a 2-bit coding of which JTAG chain is being addressed: Chain 0 is for control registers in the Slow Control FPGA. Chain 1 is for programming the Slow Control FPGA. Chain 2 is for control registers in the Mezzanine card FPGA. Chain 3 is for programming the Mezzanine card FPGA. Connector Type: PCB: 3M 3314-5002 14-pin right angle center key Cable: 3M 3385-6600 14-pin center bump J2 Power Connector Function: Table 23: Xilinx LVDS X-Blaster Connector Signal I/O Pin Pin I/O Signal +TCK In 1 2 In -TCK +TDO Out 3 4 Out -TDO +TMS In 5 6 In -TMS +3.3V Out 7 8 - GND +TDI In 9 10 In -TDI SEL0 In 11 12 In SEL1 +3.3V Out 13 14 In JTAG Power supply inputs. Connector Type: PCB: Molex-Waldom 39-29-4089 [30µ" gold over brass, was -5083] Cable: Molex-Waldom 39-01-2085 [was 2080] Terminal: Molex-Waldom 39-00-0182 [gold over phosphor-bronze, was - 0154] Figure 6: ALCT2001 Power Connector Looking from cable toward PCB Pin 8 DGND Pin 7 DGND Pin 6 AGND Pin 5 AGND Pin 4 +1.8 Pin 3 +3.3 Pin 2 +5.5A Pin 1 +5.5B Power Requirements Page 48 of 62

The power requirements are determined by measuring actual power currents and adding some margin. In particular, the 1.8v and 3.3v power current can depend on the programming of the Virtex chip. The currents measured for the 384-channel variant of ALCT2001 are listed in Table 24. The currents extrapolated to 288-channel and 672-channel variants are listed in Table 25. The DC power required by ALCT2001 depends on the number of LCT FPGAs and the number of AFEB cards installed. The first channel of +5.5v power is partly used for on-alct purposes. The rest of the first channel of +5.5v power and all of the second channel of +5.5v power is passed through ALCT to the AFEB cards. The AFEB power is distributed as follows: for 288-channel cards, the first 6 AFEBs are powered from +5.5v_1 and the last 12 are powered from +5.5v_2. For 384-channel cards, the first 12 AFEBs are powered from +5.5v_1 and the last 12 are powered from +5.5v_2. For 672-channel cards, the first 24 AFEBs are powered from +5.5v_1 and the last 18 are powered from +5.5v_2. Note: (24- Sep-01) I would like to change ALCT-288 so that all 18 AFEBs are powered from +5.5v_1 so that we don t have to worry about the 2 nd power supply in this case. Most but not all of the +3.3v power is used by the ALCT motherboard. Only the mezzanine card uses +1.8v power (the Virtex chip core voltage). The current consumption also depends somewhat on the choice of programmed JTAG configuration options. However, power consumption is approximately the same whether the LCT logic is idle or whether it is processing events at a high rate. The 1.8v and +3.3v power should be supplied with ±5% precision, i.e. 1.8±0.1v and 3.30±0.15v. The 5.5v power should actually be a little higher. A spec of 5.7±0.10v has been agreed to: there is about 0.042v drop in the slow-blow fuse to the AFEB, but more stringent requirement from on-board ALCT situation: power regulator can drop 0.5v, the minimum voltage spec. to the variable-gain amplifier is 5.0v, would like 0.1v margin, also the ADC reading of these voltages is gotten through a resistor-divider using two 0.1% resistors. A deviation of 0.2% would give voltage reading that is incorrect by 10 mv, also the maximum error of the 10-bit ADC is about 4 LSB, corresponding to about 20 mv. Page 49 of 62 Supply Voltage +5.5V_1 [24 AFEBs] +5.5V_2 [24 AFEBs] Table 24: Measured Power Supply Currents [ALCT2001-384]. AFEBs Standby AFEBs ON Test Pulse Test Pulse Test Pulse Test Pulse OFF OFF 10kHz 10kHz 0.15A 0.16A 1.38A 1.40A 0.04A 0.06A 1.18A 1.22A +3.3V [no mezz] 0.24A 0.32A +3.3V [unprogrammed mezz] +3.3V [programmed mezz] +1.8V [unprogrammed mezz] +1.8V [programmed mezz] 0.95A 0.08A 0.54A Power [ALCT] 5.3W Power [AFEB] 13.2W 18.5W Power [ALCT+AFEB]

Wire Groups (per layer) Table 25: Power Estimate for ALCT2001 Variants (simple scaling). AFEBs AFEB AFEB AFEB ALCT2001 Current I(+5.5_1) I(5.5_2) Power +1.8V +3.3 +5.5_1 +5.5_2 48 18 1.8A 9.9W 0.41A 0.71A 0.12A 0.05A 4.0W 64 24 2.4A 13.2W 0.54A 0.95A 0.16A 0.06A 5.3W 112 42 4.2A 23.1W 0.95A 1.66A 0.28A 0.11A 9.3W ALCT2001 Power LVDB power supply specifications are listed in Table 26. Information as of 10-Sept-2001 (Wahl) is that LVDB regulators will be designed to supply up to 10A. Power Protection Table 26: ALCT2001 Power Requirements. Pin Voltage Setting (V) +/- Tolerance Max. I (A) 1 +5.65 +.05/-.05 V 2.5 2 +5.65 +.05/-.05 V 2.2 3 +3.3 +/-0.16v (5%) 3.3 4 +1.8 +/- 0.09v (5%) 1.9 All input power sources are protected against shorts with 5A fuses. The 1.8v supply is protected against overvoltage with a 2.5v Zener diode, the 3.3v supply is protected with a 3.9v Zener diode, and each 5.5v supply is protected with a 6.2v Zener. Each AFEB is protected individually against shorts or high current conditions (e.g. latchup) with 1.0A resettable fuses. Page 50 of 62

J3 External test pulse input Function: Allows an external TTL test pulse to fire the test pulse circuit. Routed through the Mezzanine card so that firmware is required to pass this signal through to the test pulse circuit. Connector Type: PCB: LEMO FPL.00.250.NTL J4 and J5: SCSI connectors for TMB I/O Two 25-pair cables connect from ALCT to the Trigger Mother Board. To reduce the number of cable pairs, the synchronous inputs and outputs are 2-to-1 multiplexed at 80MHz in the ALCT FPGA. Asynchronous inputs and JTAG signals are not multiplexed, and are assigned dedicated pairs in the TMB cables. TMB cable 1 (J5) carries output signals at 80MHz. TMB cable 2 (J4) carries some inputs at 80MHz and some non-multiplexed inputs at 40MHz. The few remaining outputs that would not fit on the first cable have been moved to the second cable. What follows is first a logical description of the ALCT-TMB signals, then a physical description of implementation in the J4 and J5 connectors. Logical Description of ALCT-TMB Signals Page 51 of 62

J5 TMB Cable 1 Function: Receives 80MHz and 40MHz inputs from TMB Connector Type: PCB: AMP 787190-5 Cable: AMP 749111-4 Shell: AMP 749889-3 [with latches] Table 27: TMB Cable 1 Signal and Pin Assignments Modified 4/12/01 to match ALCT2001 PCB. Stinking bad signal inversion = Pair Inverted Pin Dir Logic Multiplexed Signals + - First in Time Second in Time 1 1+ 2- Out LVDS first_valid second_valid 2 49+ 50- Out LVDS first_amu second_amu 3 3+ 4- Out LVDS first_quality0 second_quality0 4 47+ 48- Out LVDS first_quality1 second_quality1 5 5+ 6- Out LVDS first_key0 second_key0 6 45+ 46- Out LVDS first_key1 second_key1 7 7+ 8- Out LVDS first_key2 second_key2 8 43+ 44- Out LVDS first_key3 second_key3 9 9+ 10- Out LVDS first_key4 second_key4 10 41+ 42- Out LVDS first_key5 second_key5 11 11+ 12- Out LVDS first_key6 second_key6 12 39+ 40- Out LVDS bxn0 bxn3 13 13+ 14- Out LVDS bxn1 bxn4 14 37+ 38- Out LVDS bxn2 /wr_fifo 15 15+ 16- Out LVDS daq_data0 daq_data7 16 35+ 36- Out LVDS daq_data1 daq_data8 17 17+ 18- Out LVDS daq_data2 daq_data9 18 33+ 34- Out LVDS daq_data3 daq_data10 19 19+ 20- Out LVDS daq_data4 daq_data11 20 31+ 32- Out LVDS daq_data5 daq_data12 21 21+ 22- Out LVDS daq_data6 daq_data13 22 29+ 30- Out LVDS lct_special first_frame 23 23+ 24- Out LVDS seq_status0 seu_status0 24 27+ 28- Out LVDS seq_status1 seu_status1 25 25+ 26- Out LVDS ddu_special last_frame Page 52 of 62

J4 TMB Cable 2 Function: Transmits 80MHz outputs to TMB. Connector Type: PCB: AMP 787190-5 Cable: AMP 749111-4 Shell: AMP 749889-3 [with latches] Table 28: TMB Cable2 Connector Modified 4/12/01 to match ALCT2001 PCB. Stinking bad signal inversion Pair Inverted Pin Dir Logic Multiplexed Signals + - First in Time Second in Time 1 1+ 2- In LVDS tdi 2 49+ 50- In LVDS tms 3 3+ 4- In LVDS tck 4 47+ 48- In LVDS jtag_select0 5 5+ 6- In LVDS jtag_select1 6 45+ 46- In LVDS ccb_brcst0 ccb_brcst4 7 7+ 8- In LVDS ccb_brcst1 ccb_brcst5 8 43+ 44- In LVDS ccb_brcst2 ccb_brcst6 9 9+ 10- In LVDS ccb_brcst3 ccb_brcst7 10 41+ 42- In LVDS brcst_str1 subaddr_str 11 11+ 12- In LVDS dout_str bx0 12 39+ 40- In LVDS ext_inject ext_trig 13 13+ 14- In LVDS level1_accept sync_adb_pulse 14 37+ 38- In LVDS seq_cmd0 seq_cmd2 15 15+ 16- In LVDS seq_cmd1 reserved_in4 16 35+ 36- In LVDS reserved_in0 8 reserved_in2 17 17+ 18- In LVDS reserved_in1 reserved_in3 18 33+ 34- In LVDS async_adb_pulse 19 19+ 20- In LVDS /hard_reset 20 31+ 32- In LVDS clock_en 21 21+ 22- In LVDS clock 22 29+ 30- Out LVDS tdo 23 23+ 24- Out LVDS first_patb second_patb 24 27+ 28- Out LVDS reserved_out1 reserved_out3 25 25+ 26- Out LVDS active_feb_flag cfg_done 8 Reserved cable input signals connect to ALCT FPGA user input pins Page 53 of 62

J4/J5 TMB Connectors 9 Figure 7: 50-Pin PCB Connector (Female) (Looking into PCB Connector) ------------------------------------- \ 25 1/ \ 26 50/ --------------------------------- Figure 8: 50 Pin Cable Connector (Male) (Looking into Cable Connector) ------------------------------------- \ 1 25/ \ 50 26/ --------------------------------- Table 29: AMP 50-Pin SCSI PCB Connector PCB Side (Looking at top of PCB) Cable Side 1 50 2 49 3 48 4 47 5 46 6 45 7 44 8 43 9 42 10 41 11 40 12 39 13 38 14 37 15 36 16 35 17 34 18 33 19 32 20 31 21 30 22 29 23 28 24 27 25 26 9 Copied from CFEB design: http://www.physics.ohio-state.edu/~gujh/works/cmpdata.html Page 54 of 62

J6-J11 Strip Test Pulse Outputs Function: Outputs Analog Test Pulse to CSC Strip Pulse Inputs. Connector Type: PCB: LEMO FPL.00.250.NTL J12-J29 or J12-35 or J12-53 AFEB Board I/O Function: Receives 16 LVDS discriminator signal pairs from AFEB cards. Sends power, test pulse, and regulator control signals to AFEB cards. Connector Type: PCB: AMP 102153-9 Ejector: AMP 102320-1 Cable: AMP 746285-9 Table 30: J13-J36 AFEB I/O Connector +Outs0 1 2 -Outs0 +Outs1 3 4 -Outs1 +Outs2 5 6 -Outs2 +Outs3 7 8 -Outs3 +Out_0 9 10 -Out_0 +Out_1 11 12 -Out_1 +Out_2 13 14 -Out_2 +Out_3 15 16 -Out_3 +Outs4 17 18 -Outs4 +Outs5 19 20 -Outs5 +Outs6 21 22 -Outs6 +Outs7 23 24 -Outs7 +Out_4 25 26 -Out_4 +Out_5 27 28 -Out_5 +Out_6 29 30 -Out_6 +Out_7 31 32 -Out_7 GND 33 34 GND /Stand_By 35 36 Vthr +5.5VA 37 38 GND(was -4.3VA) Test_Pulse 39 40 GND Page 55 of 62

Mechanical Specs Mechanics for 384-channel version The material in this section is to document the hole locations for mounting the 384 channel version of the ALCT and it s stiffener plate. PCB Footprint Figure 9: ALCT2001-384 PCB footprint. Page 56 of 62

Stiffener Plate Dimensions Figure 10: ALCT2001-384 Stiffener Plate footprint. Page 57 of 62

Mechanics for 672-channel version The material in this section is to document the hole locations for mounting the 672 channel version of the ALCT and it s stiffener plate. PCB Footprint Figure 11: ALCT2001-672 PCB footprint. Page 58 of 62

Stiffener Plate Dimensions Figure 12: ALCT2001-672 Stiffener Plate footprint. Page 59 of 62

Mechanics for 288-channel version The material in this section is to document the hole locations for mounting the 288 channel version of the ALCT and it s stiffener plate. PCB Footprint Figure 13: ALCT2001-288 PCB footprint. Page 60 of 62