ACS College of Engineering. Department of Biomedical Engineering. Logic Design Lab pre lab questions ( ) Cycle-1

Similar documents
ELCT 501: Digital System Design

FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1

(ii) Simplify and implement the following SOP function using NOR gates:

Digital Design with FPGAs. By Neeraj Kulkarni

Hardware Description Language VHDL (1) Introduction

Abi Farsoni, Department of Nuclear Engineering and Radiation Health Physics, Oregon State University

VHDL Examples Mohamed Zaky

Department of Technical Education DIPLOMA COURSE IN ELECTRONICS AND COMMUNICATION ENGINEERING. Fifth Semester. Subject: VHDL Programming

ECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic

ECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic

Digital Systems Design

Code No: R Set No. 1

Field Programmable Gate Array

VHDL 2 Combinational Logic Circuits. Reference: Roth/John Text: Chapter 2

R10. II B. Tech I Semester, Supplementary Examinations, May

Code No: 07A3EC03 Set No. 1

QUESTION BANK FOR TEST

Lecture 1: VHDL Quick Start. Digital Systems Design. Fall 10, Dec 17 Lecture 1 1

2/14/2016. Hardware Synthesis. Midia Reshadi. CE Department. Entities, Architectures, and Coding.

Code No: R Set No. 1

CONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)

Injntu.com Injntu.com Injntu.com R16

Federal Urdu University of Arts, Science and Technology, Islamabad VLSI SYSTEM DESIGN. Prepared By: Engr. Yousaf Hameed.

LABORATORY MANUAL VLSI DESIGN LAB EE-330-F

Lecture 12 VHDL Synthesis

ECE 545 Lecture 5. Data Flow Modeling in VHDL. George Mason University

Lab 3: Standard Combinational Components

Principles of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.

Control and Datapath 8

VALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS

Lecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language)

Verilog Tutorial (Structure, Test)

VHDL. ELEC 418 Advanced Digital Systems Dr. Ron Hayne. Images Courtesy of Cengage Learning

Chapter 2 Basic Logic Circuits and VHDL Description

Code No: R Set No. 1

FPGA BASED SYSTEM DESIGN. Dr. Tayab Din Memon Lecture 9 & 10 : Combinational and Sequential Logic

SRI SUKHMANI INSTITUTE OF ENGINEERING AND TECHNOLOGY, DERA BASSI (MOHALI)

Institute of Engineering & Management

Concurrent Signal Assignment Statements (CSAs)

Department of Electronics & Communication Engineering Lab Manual E-CAD Lab

EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE

VLSI DESIGN (ELECTIVE-I) Question Bank Unit I

CS303 LOGIC DESIGN FINAL EXAM

COE 405 Design Methodology Based on VHDL

ECE 545 Lecture 8. Data Flow Description of Combinational-Circuit Building Blocks. George Mason University

HANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment

Experiment 8 Introduction to VHDL

[VARIABLE declaration] BEGIN. sequential statements

Introduction to Verilog

Hardware Description Languages (HDLs) Verilog

Written exam for IE1204/5 Digital Design Thursday 29/

IT T35 Digital system desigm y - ii /s - iii

EE6301 DIGITAL LOGIC CIRCUITS UNIT V VHDL PART A

UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS PART-A (2 MARKS)

VERILOG CODES //SPECIAL COMBINATIONAL LOGIC CIRCUITS

COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I

Mid-Term Exam Solutions

Tutorial on Verilog HDL

END-TERM EXAMINATION

Combinational Logic. Prof. Wangrok Oh. Dept. of Information Communications Eng. Chungnam National University. Prof. Wangrok Oh(CNU) 1 / 93

Verilog Fundamentals. Shubham Singh. Junior Undergrad. Electrical Engineering

SUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3

CSCI Lab 3. VHDL Syntax. Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\

DIGITAL SYSTEM DESIGN

Hours / 100 Marks Seat No.

PART B. 3. Minimize the following function using K-map and also verify through tabulation method. F (A, B, C, D) = +d (0, 3, 6, 10).

Combinational Logic Circuits

DIGITAL SYSTEM DESIGN

VHDL: A Crash Course


10EC33: DIGITAL ELECTRONICS QUESTION BANK

VHDL VS VERILOG.

Review. LIBRARY list of library names; USE library.package.object; ENTITY entity_name IS generic declarations PORT ( signal_name(s): mode signal_type;

CS211 Digital Systems/Lab. Introduction to VHDL. Hyotaek Shim, Computer Architecture Laboratory

N-input EX-NOR gate. N-output inverter. N-input NOR gate

Introduction to Verilog HDL. Verilog 1

R a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS

2008 The McGraw-Hill Companies, Inc. All rights reserved.

II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit.

NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni

3. The high voltage level of a digital signal in positive logic is : a) 1 b) 0 c) either 1 or 0

Review of Digital Design with VHDL

The VHDL Hardware Description Language

Lecture 3: Modeling in VHDL. EE 3610 Digital Systems

Topics. Midterm Finish Chapter 7

DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY

Outline. CPE/EE 422/522 Advanced Logic Design L05. Review: General Model of Moore Sequential Machine. Review: Mealy Sequential Networks.


VHDL for FPGA Design. by : Mohamed Samy

Declarations of Components and Entities are similar Components are virtual design entities entity OR_3 is

R07. Code No: V0423. II B. Tech II Semester, Supplementary Examinations, April

Contents. Chapter 3 Combinational Circuits Page 1 of 34

CS429: Computer Organization and Architecture

Department of Computer Science & Engineering. Lab Manual DIGITAL LAB. Class: 2nd yr, 3rd sem SYLLABUS

Chap 6 Introduction to HDL (d)

Philadelphia University Student Name: Student Number:

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT

ECE 331: N0. Professor Andrew Mason Michigan State University. Opening Remarks

St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad

Transcription:

ACS College of Engineering Department of Biomedical Engineering Logic Design Lab pre lab questions (2015-2016) Cycle-1 1. What is a combinational circuit? 2. What are the various methods of simplifying the Boolean function? 3. What do you mean by minterm? 4. What do you mean by minterm? 5. What is a half adder? 6. What is a full adder? 7. What is parallel adder? 8. What is the internal structure of 7483 IC? 9. What do you mean by code conversion? 10. What is a multiplexer? 1. What is a latch? 2. What is a flip flop? 3. What is a register? 4. What is a counter? 5. What is a synchronous counter? 6. What is a state diagram? 7. What is signal? How it is declared? 8. What is entity? 9. What is architecture? Cycle-2

Cycle-3 1)Describe the main difference between a gated S-R latch and an edge-triggered S-R flip-flop. 2)How does a JK flip-flop differ from an SR flip-flop in its basic operation? 3)Describe the basic difference between pulse-triggered and edge-triggered flip-flops. 4)What is use of characteristic and excitation table? 5) What is relay?

ACS College of Engineering Department of Biomedical Engineering Logic Design Lab pre lab questions (2016-2017) Cycle-1 1. What is a combinational circuit? 2. What are the various methods of simplifying the Boolean function? 3. What do you mean by minterm? 4. What do you mean by minterm? 5. What is a half adder? 6. What is a full adder? 7. What is parallel adder? 8. What is the internal structure of 7483 IC? 9. What do you mean by code conversion? 10. What is Demultipxer? 1. What is a latch? 2. What is a flip flop? 3. What is a register? 4. What is a counter? 5. What is a synchronous counter? 6. What is a state diagram? 7. What is signal? How it is declared? 8. What is entity? 9. What is architecture? 10. What is behavioral model? 11. What are data types? Cycle-2

Cycle-3 1)Describe the main difference between a gated S-R latch and an edge-triggered S-R flip-flop. 2)How does a JK flip-flop differ from an SR flip-flop in its basic operation? 3)Describe the basic difference between pulse-triggered and edge-triggered flip-flops. 4) What is use of characteristic and excitation table? 5) What is relay? 6) What is the work of seven segment display? Content beyond the syllabus: 1) Write a verilog program for decoder? 2) Write VHDL program for logic gates?

Verilog program for decoder (3:8) module decoder(d,x,y,z); output [7:0] d; input x,y,z; assign d[0] = ~x & ~y & ~z; assign d[1] = ~x & ~y & z; assign d[2] = ~x & y & ~z; assign d[3] = ~x & y & z; assign d[4] = x & ~y & ~z; assign d[5] = x & ~y & z; assign d[6] = x & y & ~z; assign d[7] = x & y & z; endmodule 2) Write VHDL program for logic gates? library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity gates is Port ( a,b : in std_logic; c,d,e,f,g,h,i : out std_logic); end gates;

architecture dataflow of gates is c<= a and b; d<= a or b; e<= not a; f<= a nand b; g<= a nor b; h<= a xor b; i<= a xnor b; end dataflw;

ACS College of Engineering Department of Biomedical Engineering Logic Design Lab pre lab questions (2017-2018) Cycle-1 11. What is a combinational circuit? 12. What are the various methods of simplifying the Boolean function? 13. What do you mean by minterm? 14. What do you mean by minterm? 15. What is a half adder? 16. What is a full adder? 17. What is parallel adder? 18. What is the internal structure of 7483 IC? 19. What do you mean by code conversion? 20. What is Demultipxer? 12. What is a latch? 13. What is a flip flop? 14. What is a register? 15. What is a counter? 16. What is a synchronous counter? 17. What is a state diagram? 18. What is signal? How it is declared? 19. What is entity? 20. What is architecture? 21. What is behavioral model? 22. What are data types? Cycle-2

Cycle-3 1)Describe the main difference between a gated S-R latch and an edge-triggered S-R flip-flop. 2)How does a JK flip-flop differ from an SR flip-flop in its basic operation? 3)Describe the basic difference between pulse-triggered and edge-triggered flip-flops. 4)What is use of characteristic and excitation table? 5) What is relay? 6) What is the work of seven segment display? 7) what is the working principle of stepper motor? Content beyond the syllabus: 1) Write a verilog program for encoder? 2) Write VHDL program for logic gates and half adder? 3) Write verilog program for full adder?

1) Write a verilog program for encoder? module WPencode(en,Din,Dout) input en; input [ 7 : 0 ] Din; output [ 2 : 0 ] Dout; reg [ 2 : 0 ] Dout; always@(en,din) if(en == 1) Dout = 3 bzzz; end else Case (Din) 8 b00000001:dout = 3 b000; 8 b00000010:dout = 3 b001; 8 b00000100:dout = 3 b010; 8 b00001000:dout = 3 b011; 8 b00010000:dout = 3 b100; 8 b00100000:dout = 3 b101; 8 b01000000:dout = 3 b110; 8 b01000000:dout = 3 b111; end case end end end module

2) Write VHDL program for logic gates and half adder? library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity gates is Port ( a,b : in std_logic; c,d,e,f,g,h,i : out std_logic); end gates; architecture dataflow of gates is c<= a and b; d<= a or b; e<= not a; f<= a nand b; g<= a nor b; h<= a xor b; i<= a xnor b; end dataflw; Half Adder entity Halfadder is Port ( a,b, : in std_logic; sum,cout : out std_logic); end Halfadr;

architecture data of halfadr is sum<=a xor b ; cout<= ( a and b); end data; 3)Write verilog program for full adder? module fulladder ( a, b, c,s,cout) input a, b,c; output s, cout; assign s= a ^ b^c; assign cout= a & b & c; endmodule

2024 © technodocbox.com Privacy Policy | Terms of Service | Feedback