HOMEWORK 10 CMPEN 411 Due: 4/28/2016 11:30pm Instruction First, fabrication ready the full 8 bit RISC microprocessor chip: redesign the chip (its components) to fit the entire chip fitted into the 40 pin 'tiny' chip pad frame. Optimize as much as possible the size, speed, and power consumption. Second, full documentation of your chip: chip data sheet and the User's Guide, including the simulation results. Do verify the functioning and timing from the 'pad-to-pad' simulation. Third, chip test plan: write the detail procedure of the chip testing plan. 1. Homework 10 preparation: Create a directory 'hw10yourlastname' under c411 directory (assuming you have c411 directory in your home for this class). Change the current directory to hw10yourlastname. Set up the directory for a new Cadence Virtuoso library. Then start the hw10 design project. For example, my hw10 directory will be 'hw10choi' and I will be running the following unix commands right after I login to my account: % cd c411 % mkdir hw10choi % cd hw10choi % runcds % virtuoso & You can follow the same except that you need to use your last name after 'hw10'. 2. Once the Virtuoso is running, create the new library named 'hw10yourlastname' first. Attach the NCSU_TechLib_ami06 technology to your 'hw10yourlastname' library. Then exit the Virtuoso to add the pad frame library path and your hw9 library path to your hw10 project. One must manually add the pad frame library path and your hw9 library paths to hw10 project library and copy all the necessary cells from those library to the new hw10 library. After copying all the cells, one MUST delete the other library paths, leaving only the 'hw10yourlastname' library, containing all the cells for the complete chip. 3. Start the Virtuoso, and open the top cell schematic and layout. Visit every cell (with x short cut key 'Descend into cell') and be sure that they are properly copied into the hw10 library. If any missing cell, the chip cannot be verified and cannot be fabricated. 4. Redesign the cells that are too large (or too slow, etc.) to fit the entire chip inside of the 40 pin 'tiny' chip pad frame. 5. Use hierarchical design method to manage design complexity. That is, design simple cells and design top cell which combines simple cells. The Cadence tool Virtuoso assumes all design is done this way, uses cellview to manage cells. Use meaningful names for the cells; for example, use 8bitMicroprocessor rather than hw8 for the microprocessor. For your hw10 project, you MUST name 'aaamicro8top' as the top cell - the complete chip. 6. Use bit-slices and include the inter-cell wiring. Using the top metal layers, route the signal lines over the cells and not around the cells. This way, the separate wiring space on the silicon area is minimized. 7. Once the full 8 bit RISC microprocessor core is placed into the 40 pin 'tiny' chip pad frame, do verify the functioning and timing from the 'pad-to-pad' Hspice simulation. 8. As in any chip design, the design goal is to layout the circuit in a small area, and achieve faster signal communication. You may want to re-shape and update your design so that it can be as small as possible. Do assign each pin pad for the input, output, program data, vdd, gnd, clock, reset, etc. There are only 40 pins, any left-over pins can be used for testing signals.
9. The pads in the frame can be re-arranged. Any pad can be replaced with another pad. There are input signal pad, output signal pad, in/out bidirectional signal pad, vdd pad, gnd pad, space pad, etc. pin 1 10. The final chip pin signal assignment must be made in the following way: 11. Final chip die will be placed in the 40 pin Dual In-line Package (DIP), the bonding wire placement from the chip pads to the package pin leads is shown below (top view):
12. Be sure to connect all of the power vdd! and gnd! lines with thicker metal layers (m1 or m2 or m3). Also use as many contacts as possible for the power line connections. The metal wires for the vdd! and gnd! power must be extra wider than any signal wires. 13. Be sure to put the signal labels on the bonding pad with m3 layer. Also be sure to include at least one vdd pad and one gnd pad, and label them. On the top cell, make only one vdd! label and one gnd! label. 14. The design must be free from the DRC errors and pass the LVS checking. 15. Extract the circuit from the layout including the parasitic capacitances. Then hspice simulate the extracted circuit netlist. Any of the timing measurements required for the questions below must use the simulation of the extracted circuit from the layout including the parasitic capacitances. Place 1pF load capacitors on the output pads, in.hsp file for the pad to pad simulation. 16. Open extract view, select the vdd! wire or gnd! wire to highlight them, to visually inspect that all vdd! are connected and all gnd! wires are connected.
17. To verify the functioning, design the Hspice simulation files:.hsp,.s, and.sp files. Your simulation output must show all signals. Design your.hsp file to show the following eight instruction executions in sequence. However, the program execution must be proceeded by the program storing in the program memory through the pads. So, the simulation must include program storing and then program execution. Explain your simulation: writing and execution sequence with the signals. The timing must include pads and load capacitors on the output pads. MV 0,0 MV #9,5 MV #8,7 MV 7,0 ADD 5,0 SUB 5,7 BC 6 IN 3 OUT 3 18. You can always add more labels on the layout to see the microprocessor internal signals on the simulation output. This will help debugging the processor, visualizing the signal propagation, and analyzing the circuits. 19. For your microprocessor simulation, explain the instruction execution time. How do you measure the instruction execution time from the simulation result? Please explain. What is the worst case instruction execution time of your microprocessor? Please explain the worst case instruction execution time. 20. How fast can you repeat the clock signal CK while the program properly executing? 21. From the instruction execution simulation, list the delay times of each sub operations, which will be added to make up the one instruction execution cycle. Do for all 7 instructions. Which instruction is the fastest? Which instruction is the slowest? Why? Explain. 22. Which component is the slowest? Why does it take so long? How can we make it faster? Design the.hsp file to demonstrate the worst case instruction execution of the microprocessor while maintaining the correct output result. What limits the maximum speed of operation? Show the simulation plot to substantiate your answer. 23. How many transistors are used in your microprocessor chip design (including the pads)? 24. Did you use static, dynamic, or pass transistor logic? 25. Are there any errors in schematic? 26. Is there an error in layout? Does your layout pass the DRC checking without errors (including the pads)? 27. Is there a miss match on the schematic versus layout? Does your design pass the LVS checking without errors (including the pads)? 28. Extract the circuit from the layout including the parasitic capacitances. Then hspice simulate the extracted circuit netlist. Be sure that your signal label is placed at the pad so that the simulation is 'pad-to-pad' signal simulation. What is the worst case output signal rise time, fall time, and delay time? The worst case delay time is from which input to which output? Explain the signal path for the worst case delay time (this is called critical signal path)? Worst case delay time: T = nsec. 29. What is the total layout height and width? What is the total layout area measured in um**2? Area: A = um**2 (including the pads).
30. What is the AT**2 measure of your design? AT**2 = um**2 nsec**2 (including the pads). 31. What are the improvements made from the hw9? List improved cell names and the improvements: layout size, speed, power, etc. 32. Create a hw10 report file hw10yourlastname.doc and include captured image of layout and the simulation results. Add your explanations and comments. On the Linux machines in room 218 IST, one can use 'openoffice.org' program for the document creating and editing, and use 'gimp' program for the image capture and processing from the screen. 33. The hw10 report file must include full documentation of your chip: chip data sheet and the User's Guide, including the simulation results and answers to the questions. Show the functioning and timing of your chip from the 'pad-topad' simulation. 34. Also the hw10 report file MUST include chip test plan: write the detail procedure of the chip testing plan. 35. The hw10 report file can be in.doc or.pdf, must include a cover page for student information such as 'CMPEN 411, Homework 10, your name, etc. Please use the sample Homework 10 report format, the sample hw10 report file is posted: Sample hw10 Report 36. Create a tarred zip file of your hw10yourlastname directory in c411 directory. It will contain the schematics, symbols, layouts,.hsp,.sp files, and.doc report file. In your c411 directory, use the following unix commands % tar -czvf hw10yourlastname.tgz hw10yourlatname to create a tarred zip file of hw10yourlastname library. For example, % tar -czvf hw10choi.tgz hw10choi will archive the directory hw10choi and create a zipped file hw10choi.tgz in my c411 project directory. For the grading, the command tar xzvf hw10choi.tgz will be used to restore project. Please delete.tr0 files before zipping, for their sizes are usually large. 37. Turn-in your project zip file through Penn State ANGEL. Deposit your zip file into the Homework 10 DropBox under CLASS tab in CMPEN 411 Course. 38. Make sure that you include all the files necessary into your project folder, in order to verify for grading. Turn-in your project before 11:30pm on the due date.