Digital VLSI Design with Verilog

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John Williams Digital VLSI Design with Verilog A Textbook from Silicon Valley Technical Institute Foreword by Don Thomas Sprin ger

Contents Introduction xix 1 Course Description xix 2 Using this Book xx 2.1 Contents of the CD-ROM xx 2.2 Performing the Lab Exercises xx 2.3 Proprietary Information and Licensing Limitations xxi References xxi 1 Week 1 Class 1 1 1.1 Introductory Lab 1 1 1.1.1 Lab 1 Postmortem 11 1.2 Verilog Vectors 13 1.3 Operator Lab 2 16 1.3.1 Lab Postmortem 17 1.4 First-Day Wrapup 17 1.4.1 VCD File Dump 17 1.4.2 The Importance of Synthesis 18 1.4.3 SDFFileDump 18 1.4.4 Additional Study 19 2 Week 1 Class 2 21 2.1 More Language Constructs 21 2.2 Parameter and Conversion Lab 3 29 2.2.1 Lab Postmortem 30 2.3 Procedural Control 30 2.3.1 Procedural Control in Verilog 30 2.3.2 Combinational and Sequential Logic 31 2.3.3 Verilog Strings and Messages 33 2.3.4 Shift Registers 35 2.3.5 Reconvergence Design Note 36 2.4 Nonblocking Control Lab 4 37 2.4.1 Lab Postmortem 41 2.4.2 Additional Study 42 xi

xii Contents 3 Week 2 Class 1 43 3.1 Net Types, Simulation, and Scan 43 3.1.1 Variables and Constants 43 3.1.2 Identifiers 44 3.1.3 Concurrent vs. Procedural Blocks 44 3.1.4 Miscellaneous Other Verilog Features 45 3.1.5 Backus-Naur Format 45 3.1.6 Verilog Semantics 46 3.1.7 Modelling Sequential Logic 48 3.1.8 Design for Test (DFT): Scan Lab Introduction 50 3.2 Simple Scan Lab 5 53 3.2.1 Lab Postmortem 59 3.2.2 Additional Study 59 4 Week 2 Class 2 61 4.1 PLLs and the SerDes Project 61 4.1.1 Phase-Locked Loops 61 4.1.2 A 1 x Digital PLL 61 4.1.3 Introduction to SerDes and PCI Express 67 4.1.4 The SerDes of this Course 69 4.1.5 A 32 x Digital PLL 70 4.2 PLL Clock Lab 6 71 4.2.1 Lab Postmortem 81 4.2.2 Additional Study 82 5 Week 3 Class 1 83 5.1 Data Storage and Verilog Arrays 83 5.1.1 Memory: Hardware and Software Description 83 5.1.2 Verilog Arrays 84 5.1.3 A Simple RAM Model 87 5.1.4 Verilog Concatenation 87 5.1.5 Memory Data Integrity 88 5.1.6 Error Checking and Correcting (ECC) 90 5.1.7 Parity for SerDes Frame Boundaries 93 5.2 Memory Lab 7 95 5.2.1 Lab Postmortem 99 5.2.2 Additional Study 99 6 Week 3 Class 2 101 6.1 Counter Types and Structures 101 6.1.1 Introduction to Counters 101 6.1.2 Terminology: Behavioral, Procedural, RTL, Structural 102 6.1.3 Adder Expression vs. Counter Statement 104 6.1.4 Counter Structures 105

Contents xiii 6.2 Counter Lab 8 108 6.2.1 Lab Postmortem Ill 6.2.2 Additional Study Ill 7 Week 4 Class 1 113 7.1 Contention and Operator Precedence 113 7.1.1 Verilog Net Types and Strengths 113 7.1.2 Race Conditions, Again 116 7.1.3 Unknowns in Relational Expressions 119 7.1.4 Verilog Operators and Precedence 120 7.2 Digital Basics: Three-State Buffer and Decoder 122 7.3 Strength and Contention Lab 9 123 7.3.1 Strength Lab postmortem 129 7.4 Back to the PLL and the SerDes 129 7.4.1 Named Blocks 129 7.4.2 The PLL in a SerDes 130 7.4.3 The SerDes Packet Format Revisited 131 7.4.4 Behavioral PLL Synchronization (language digression)... 132 7.4.5 Synthesis of Behavioral Code 140 7.4.6 Synthesizable, Pattern-Based PLL Synchronization 140 7.5 PLL Behavioral Lock-In Lab 10 141 7.5.1 Lock-in Lab Postmortem 144 7.5.2 Additional Study 144 8 Week 4 Class 2 145 8.1 State Machine and FIFO design 145 8.1.1 Verilog Tasks and Functions 145 8.1.2 A Function for Synthesizable PLL Synchronization 148 8.1.3 Concurrency by fork-join 149 8.1.4 Verilog State Machines 150 8.1.5 FIFO Functionality 151 8.1.6 FIFO Operational Details 154 8.1.7 A Verilog FIFO 158 8.2 FIFO Lab 11 164 8.2.1 Lab Postmortem 167 8.2.2 Additional Study 168 9 Week 5 Class 1 169 9.1 Rise-Fall Delays and Event Scheduling 169 9.1.1 Types of Delay Expression 169 9.1.2 Verilog Simulation Event Queue 172 9.1.3 Simple Stratified Queue Example 174 9.1.4 Event Controls 177 9.1.5 Event Queue Summary 178

xiv Contents 9.2 Scheduling Lab 12 179 9.2.1 Lab Postmortem 184 9.2.2 Additional Study 184 10 Week 5 Class 2 185 10.1 Built-in Gates and Net Types 185 10.1.1 Verflog Built-in Gates 185 10.1.2 Implied Wire Names 186 10.1.3 Net Types and their Default 186 10.1.4 Structural Use of Wire vs. Reg 187 10.1.5 Port and Parameter Syntax Note 188 10.1.6 A D Flip-flop from SR Latches 189 10.2 Netlist Lab 13 192 10.2.1 Lab Postmortem 194 10.2.2 Additional Study 194 11 Week 6 Class 1 195 11.1 Procedural Control and Concurrency 195 11.1.1 Verflog Procedural Control Statements 195 11.1.2 Verflog case Variants 199 11.1.3 Procedural Concurrency 202 11.1.4 Verilog Name Space 204 11.2 Concurrency Lab 14 207 11.2.1 Lab Postmortem 209 11.2.2 Additional Study 209 12 Week 6 Class 2 211 12.1 Hierarchical Names and generate Blocks 211 12.1.1 Hierarchical Name Access 211 12.1.2 Verilog Arrayed Instances 213 12.1.3 generate Statements 214 12.1.4 Conditional Macroes and Conditional generates 214 12.1.5 Looping Generate Statements 216 12.1.6 generate Blocks and Instance Names 216 12.1.7 A Decoding Tree with Generate 220 12.1.8 Scope of the generate Loop 224 12.2 Generate Lab 15 224 12.2.1 Lab Postmortem 229 12.2.2 Additional Study 230 13 Week 7 Class 1 231 13.1 Serial-Parallel Conversion 231 13.1.1 Simple Serial-Parallel Converter 231 13.1.2 Deserialization by Function and Task 232 13.2 Lab Preface: The Deserialization Decoder 234 13.2.1 Some Deserializer Redesign - An Early ECO 236 13.2.2 A Partitioning Question 237

Contents xv 13.3 Serial-Parallel Lab 16 238 13.3.1 Lab Postmortem 242 13.3.2 Additional Study 242 14 Week 7 Class 2 243 14.1 UDPs, Timing Triplets, and Switch-level Models 243 14.1.1 User-Defined Primitives (UDPs) 243 14.1.2 Delay Pessimism 246 14.1.3 Gate-Level Timing Triplets 247 14.1.4 Switch-Level Components 249 14.1.5 Switch-Level Net: The Trireg 253 14.2 Component Lab 17 254 14.2.1 Lab Postmortem 257 14.2.2 Additional Study 258 15 Week 8 Class 1 259 15.1 Parameter Types and Module Connection 259 15.1.1 Summary of Parameter Characteristics 259 15.1.2 ANSI Header Declaration Format 259 15.1.3 Traditional Header Declaration Format 260 15.1.4 Instantiation Formats 260 15.1.5 ANSI Port and Parameter Options 261 15.1.6 Traditional Module Header Format and Options 261 15.1.7 Defparam 262 15.2 Connection Lab 18 263 15.2.1 Connection Lab Postmortem 267 15.3 Hierarchical Names and Design Partitions 268 15.3.1 Hierarchical Name References 268 15.3.2 Scope of Declarations 268 15.3.3 Design Partitioning 269 15.3.4 Synchronization Across Clock Domains 271 15.4 Hierarchy Lab 19 273 15.4.1 Lab Postmortem 276 15.4.2 Additional Study 277 16 Week 8 Class 2 279 16.1 Verilog Configurations 279 16.1.1 Libraries 279 16.1.2 Verilog Configuration 279 16.2 Timing Arcs and specify Delays 281 16.2.1 Arcs and Paths 281 16.2.2 Distributed and Lumped Delays 282 16.2.3 specify Blocks 285 16.2.4 specparams 286 16.2.5 Parallel vs. Full Path Delays 287 16.2.6 Conditional and Edge-Dependent Delays 288

xvi Contents 16.2.7 Conflicts of specify with Other Delays 289 16.2.8 Conflicts Among specify Delays 289 16.3 Timing Lab 20 289 16.3.1 Lab Postmortem 293 16.3.2 Additional Study 293 17 Week 9 Class 1 295 17.1 Timing Checks and Pulse Controls 295 17.1.1 Timing Checks and Assertions 295 17.1.2 Timing Check Rationale 296 17.1.3 The Twelve Verilog Timing Checks 297 17.1.4 Negative Time Limits 300 17.1.5 Timing Check Conditioned Events 302 17.1.6 Timing Check Notifiers 302 17.1.7 Pulse Filtering 303 17.1.8 Improved Pessimism 305 17.1.9 Miscellaneous time-related Types 305 17.2 Timing Check Lab 21 306 17.2.1 Additional Study 310 18 Week 9 Class 2 311 18.1 The Sequential Deserializer 311 18.2 PLL Redesign 312 18.2.1 Improved VFO Clock Sampler 313 18.2.2 Synthesizable Variable-Frequency Oscillator 314 18.2.3 Synthesizable Frequency Comparator 316 18.2.4 Modifications for a 400 MHz 1 x PLL 318 18.2.5 Wrapper Modules for Portability 321 18.3 Sequential Deserializer I Lab 22 322 18.3.1 Lab Postmortem 335 18.3.2 Additional Study 335 19 Week 10 Class 1 337 19.1 The Concurrent Deserializer 337 19.1.1 Dual-porting the Memory 338 19.1.2 Dual-clocking the FIFO State Machine 338 19.1.3 Upgrading the FIFO for Synthesis 338 19.1.4 Upgrading the Deserialization Decoder for Synthesis 339 19.2 Concurrent Deserializer II Lab 23 339 19.2.1 Lab Postmortem 360 19.2.2 Additional Study 360 20 Week 10 Class 2 361 20.1 The Serializer and The SerDes 361 20.1.1 The SerEncoder Module 362

Contents xvii 20.1.2 The SerialTx Module 362 20.1.3 The SerDes 362 20.2 SerDes Lab 24 362 20.2.1 Lab Postmortem 373 20.2.2 Additional Study 373 21 Week 11 Class 1 375 21.1 Design for Test (DFT) 375 21.1.1 Design for Test Introduction 375 21.1.2 Assertions and Constraints 376 21.1.3 Observability 376 21.1.4 Coverage 377 21.1.5 Corner-Case vs. Exhaustive Testing 378 21.1.6 Boundary Scan 379 21.1.7 Internal Scan 380 21.1.8 BIST 382 21.2 Scan and BIST Lab 25 383 21.2.1 Lab postmortem 392 21.3 DFT for a Full-Duplex SerDes 392 21.3.1 Full-Duplex SerDes 392 21.3.2 Adding Test Logic 393 21.4 Tested SerDes Lab 26 393 21.4.1 Lab Postmortem 403 21.4.2 Additional Study 403 22 Week 11 Class 2 405 22.1 SDF Back-Annotation 405 22.1.1 Back-Annotation 405 22.1.2 SDF Files in Verilog Design Flow 405 22.1.3 Verilog Simulation Back-Annotation 406 22.2 SDF Lab 27 407 22.2.1 Lab Postmortem 411 22.2.2 Additional Study 411 23 Week 12 Class 1 413 23.1 Wrap-up: The Verilog Language 413 23.1.1 Verilog-1995 vs. 2001 (or 2005) Differences 413 23.1.2 Verilog Synthesizable Subset Review 413 23.1.3 Constructs Not Exercised in this Course 414 23.1.4 List of all Verilog System Tasks and Functions 415 23.1.5 List of all Verilog Compiler Directives 417 23.1.6 Verilog PLI 417 23.2 Continued Lab Work (Lab 23 or later) 418 23.2.1 Additional Study 418

xviii Contents 24 Week 12 Class 2 421 24.1 Deep-Submicron Problems and Verification 421 24.1.1 Deep Submicron Design Problems 421 24.1.2 The Bigger Problem 424 24.1.3 Modern Verification 424 24.1.4 Formal Verification 425 24.1.5 Nonlogical Factors on the Chip 426 24.1.6 System Verflog 427 24.2 Continued Lab Work (Lab 23 or later) 428 24.2.1 Additional Study 428 Index 429

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