دوازدهمين سمينار ساليانه دانشكده مهندسي برق فناوری های الکترونيک قدرت اسفند 93 Introduction to DSP/FPGA Programming Using MATLAB Simulink By: Dr. M.R. Zolghadri Dr. M. Shahbazi N. Noroozi
2 Table of main context Section III FPGA basic concepts MATLAB/Simulink for FPGA implementation Xilinx system generator Conclusion
3 Summary Section III Introduction to FPGA Matlab/Simulink for Model-based Design and Implementation of FPGAs Xilinx System Generator Review of Fixed-point Representation Overview of HDL Coder
4 History of Evolution FPGAs belong to a class of devices named as FPD(field programmable device) PLD(programmable logic devices)
5 PLD Programmable Logic Array (PLA): Programmable AND plane followed by programmable or wired OR plane. Sum of product form Programmable Array Logic (PAL) Programmable AND plane and fixed OR plane. Low cost and size Less flexible than PLA
6 PLD Part of the logic diagram of the PAL 16L8.
7 What s inside an FPGA Logic Clock resources Extremely high-bandwidth RAM Multipliers Lots of wire that can be connected in any fashion
8 FPGA vs ASIC FPGA advantages: Faster time-to-market Simpler design cycle Field programmability (easy to upgrade firmware) ASIC advantages: Full custom capabilities Lower unit cost Higher performance Not suitable in power applications
9 How is an FPGA programmed Write a program in HDL (VHDL, Verilog, ) Simulate Synthesis Place and route Timinig-maximum clockrate Resuting.bin file to be programmed on FPGA
10 Can FPGA do anything Yes and no Like a microprocessor it need a program: P IP: intellectual property You can buy parts of the program or write it entirely yourself Free IP
11 Challenges in FPGA design It is harder to master than micro. Design can be time consuming. In software, when you are 80% complete, you are 80% done. With FPGA when you are 80% one you are 20% through your project.
12 Do I need an FPGA? You may need an FPGA if: Yu need very fast interrupts You need many interrupts You have very complex operations You have many interrupt sources that should be in parallel Real-time requirements Very large bandwidth is needed
13 Do I need an FPGA? You have lots of logic on your PCB Replace lots of small components with an FPGA Fewer PCB spins Some operations are impossible on microcontrller
14 Soft CPUs An FPGA can implement a CPU ARM7/9 performance This is offered by all FPGA vendors
15 FPGA application Replace logic DSP Communication Video Non-standard interface
16 FPGA application in power electronics Time constraint High switching frequency (low voltage SMPS) Increased control quality (mimic analog controller in sensor-less EKF) Parallelism constraints (combined multiphase multilevel) Hardware in the loop application Real-time digital simulator Artificial intelligence
17 FPGA architecture There are three primary configurable elements in FPGA 1) Configurable Logic Block(CLB) -implement different functions. 2) Input/Output Block(IOB) - provides the interface between -external pins and internal -signal lines 3) Programmable Routing Channel -controls the connections among different blocks
18 Logic Blocks Purpose: to implement combinational and sequential logic functions. Logic blocks can be implemented by: Transistor pairs Multiplexers Look up tables( LUT) Wide fan-in AND-OR structure.
19 Simplified CLB Structure
20 Example: 4-input AND gate A B C D O 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 A B C D A B C D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 O D SET CLR Q Q MUX 0 O 1 0 1 0 0 1 0 1 1 0 Configuration bits 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1
21 Interconnection Network
22 Placement: Select CLBs Input1 Input2 CLB0 SB0 CLB1 SB1 SB2 SB3 Input3 CLB2 SB4 CLB3 Output
23 Routing: Select path SB1 Configuration bits Input1 0 0 0 Input2 CLB0 SB0 CLB1 0 1 0 SB1 SB2 SB3 SB4 Configuration bits Input3 CLB2 SB4 CLB3 Output 0 1 0 0 0 0
24 Configuration Bitstream The configuration bitstream must include ALL CLBs and SBs, even unused ones CLB0: 00011 CLB1: 01100 CLB2: XXXXX CLB3: 01001 SB0: 000000 SB1: 000010 SB2: 000000 SB3: 000000 SB4: 000001
25 Summary Section III Introduction to FPGA Matlab/Simulink for Model-based Design and Implementation of FPGAs Xilinx System Generator Review of Fixed-point Representation Overview of HDL Coder
26 Mathworks and Xilinx Workflow MathWorks: accelerate the pace of engineering and science by providing best in class Software for: Development and verification of algorithms and control logic - development and verification of algorithms and control logic Embedded Systems implementation Xilinx: providing best in class Silicon including FPGAs and embedded system hardware platforms : Offers FPGAs and Zynq an Extensible Processing Platform Partner with MathWorks to provide an integrated workflow
27 MATLAB
28 Simulink Simulink - Visual data flow environment for modeling and simulation of dynamical systems Fully integrated with the MATLAB engine Graphical block editor Event-driven simulator Models parallelism Extensive library of parameterizable functions Simulink Blockset - math, sinks, sources DSP Blockset - filters, transforms, etc. Communications Blockset - modulation, DPCM, etc.
29 Who uses Model-based Design
30 Why Model-based Design?
31 Summary Section III Introduction to FPGA Matlab/Simulink for Model-based Design and Implementation of FPGAs Xilinx System Generator Review of Fixed-point Representation Overview of HDL Coder
32 The Challenges for a DSP Software Platform Industry Trends Trend towards platform chips (FPGAs, DSP) resulting in greater complexity Highly flexible systems required to meet changing standards Multiple design methodologies - control plane/data-path Challenges in modeling and implementing an entire platform Hardware in the loop verification is useful in complex system design and System Generator supports it System Design Challenges Leveraging legacy HDL code Modeling & implementing control logic and datapath No expert exists for all facets of system design
33 Traditional approach to FPGA programming Hardware description languages (HDL) like Verilog/VHDL allow designers to specify at a higher level than logic gates high-level (=easier to understand) Simulation possibility Hard to master Challenges in modeling and implementing an entire platform The only solution for a long time
34 Model-based approach in FPGA programming Hardware description languages (HDL) like Verilog/VHDL allow designers to specify at a higher level than logic gates We will use an even higher level tool called System Generator Alternative for Altera FPGAs: DSPBuilder Graphical programming environment within Matlab s Simulink
35 System Generator Overview Industry s system-level design environment (IDE) for FPGAs Integrated design flow from Simulink to bit file Leverages existing technologies Matlab/Simulink R13.1 or R14 from The MathWorks HDL synthesis IP Core libraries FPGA implementation tools Simulink library of arithmetic, logic operators and DSP functions (Xilinx Blockset) Bit and cycle true to FPGA implementation Arithmetic abstraction Arbitrary precision fixed-point, including quantization and overflow Simulation of double precision as well as fixed point
36 System Generator Overview VHDL code generation for Virtex-II Pro, Virtex -II, Virtex -E, Virtex, Spartan -3, Spartan -IIE and Spartan -II devices Hardware expansion and mapping Synthesizable VHDL with model hierarchy preserved Mixed language support for Verilog Automatic invocation of CORE Generator to utilize IP cores ISE project generation to simplify the design flow HDL testbench and test vector generation Constraint file (.xcf), simulation.do files generation HDL Co-Simulation via HDL C-Simulation Verification acceleration using Hardware in the Loop
37 System Generator Basics System Generator provides two key tools Blocks for building your model Hardware generator: model HDL Simulink provides a test environment for your design Generate test vectors with MATLAB or Simulink blocks Visualize and analyze output of design Leverage MATLAB expressions within design Simulation and hardware will match bit true and cycle true
38 System Generator
39 System Generator Example Simulink blocks are your signal sources and sinks Xilinx blocks are your to-be-synthesized FPGA design
40 System Generator Example These will be realized in hardware
41 System Generator Example Configures simulation & hardware parameters Relates sample period to hardware clock Used to synthesize model Sets target FPGA device for model
42 System Generator Example Convert between floating and fixed point values Top-level ports in HDL model Must set precision & sample rate in Gateway In
43 System Generator Example Must be outside System Generator gateways Operate on floating point values Good for data sources & analysis Source: continuous-time floating point constant Sink: signal vs. time scope
44 System Generator Basics Every model needs a System Generator token Models start and end with Gateway blocks : double to fixed point conversion : fixed point to double conversion Any Simulink blocks can be used outside gateways Good for data sources and output analysis Only Xilinx blocks can be used inside gateways Synthesis treats gateways as top-level ports
45 Creating a System Generator Design Exactly like conventional Simulink design
46 Blocks Xilinx blockset has nine major sections Basic elements. Counters, delays Communication Error correction blocks Control Logic. MCode, Black Box Data Types Convert, Slice DSP.. FDATool, FFT, FIR Index. All Xilinx blocks quick way to view all blocks Math. Multiply, accumulate, inverter Memory Dual Port RAM, Single Port RAM Tools. ModelSim, Resource Estimator
47 Configure Blocks Double-click or go to Block Parameters to view a block s configurable parameters Arithmetic Type: Unsigned or twos complement Implement with Xilinx Smart-IP Core (if possible)/ Generate Core Latency: Specify the delay through the block Overflow and Quantization: Users can saturate or wrap overflow. Truncate or Round Quantization Override with Doubles: Simulation only Precision: Full or the user can define the number of bits and where the decimal point is for the block Sample Period: Can be inherent with a -1 or must be an integer value Note: While all parameters can be simulated, not all are realizable
48 Values Can Be Equations You can also enter equations in the block parameters, which can aid calculation and your own understanding of the model parameters The equations are calculated at the beginning of a simulation Useful MATLAB operators + add - subtract * multiply / divide ^ power pi (3.1415926535897. ) exp(x) exponential (ex)
49 Summary Section III Introduction to FPGA Matlab/Simulink for Model-based Design and Implementation of FPGAs Xilinx System Generator Review of Fixed-point Representation Overview of HDL Coder
50 Matlab and Sysgen, Fixed Point OR Floating Point? MATLAB generally uses high precision values 64-bit floating point - huge dynamic range Impractical in hardware System Generator uses fixed point numbers instead Limited, but flexible, range & precision Pro: smaller hardware Con: requires attention to overflow & quantization
51 Fixed-Point Representation
52 Fixed-Point Representation
53 Range vs. Precision
54 Range vs. Precision
55 Range vs. Precision
56 Fixed Point Arithmetic Addition & multiplication are provided Adders use general logic Multipliers use dedicated blocks Division expensive to implement and rarely used Multi-cycle operation Try to replace with shifts
57 Fixed Point Arithmetic More bits needed with each operation for full precision May not always want to expand bitwidth, but must understand risk of overflow and/or quantization
58 Fixed Point Quantization Occurs when available fractional bits are insufficient Truncate (default): just drop bits past LSB; more efficient Round: choose nearest representable value
59 Fixed Point Overflow Occurs when available integer bits are insufficient Required bits increase with every operation This can add up very fast Think of a long FIR filter Most blocks Error on Overflow option Great for debugging in simulation Sim stops with error when overflow occurs Overflow in hardware is very hard to isolate: simulate to check first
60 Fixed Point Overflow Overflow Options Bit growth
61 Fixed Point Overflow Overflow Options Happens by default in hardware if you don t give enough bits Not always bad; sometimes this is intentional Often the source of nonsensical results
62 Fixed Point Overflow Overflow Options Stops at max/min to prevent overflow Sign of answer will be correct More expensive in hardware (requires comparator & mux for every operation)
63 Summary Section III Introduction to FPGA Matlab/Simulink for Model-based Design and Implementation of FPGAs Xilinx System Generator Review of Fixed-point Representation Overview of HDL Coder
64 Sample Period Every SysGen signal must be sampled ; transitions occur at equidistant discrete points in time called sample times Each block in a Simulink design has a Sample Period and it corresponds to how often that block s function is calculated and the results outputted This sample period must be set explicitly for: Gateway in Blocks w/o inputs (note: constants are idiosyncratic) Sample period can be derived from input sample times for other blocks
65 Sample Period The units of the sample period can be thought of as arbitrary, BUT a lot of Simulink source blocks do have an essence of time For example, a sample period of 1/44100 means the function will be executed every 1/44100 of a sec block s Remember Nyquist Theorem (Fs 2f max ) when setting sample periods The sample period of a block DIRECTLY relates to how that block will be clocked in the actual hardware
66 System Generator Clocking Both simulation and hardware are discrete time Model has a master system sample period Related to FPGA clock in System Generator token An x sec system period = 1 FPGA clock period
67 Multiple Clock Domains All clock domains are multiples of master System Period Every other clock period is derived from master FPGA clock period System sample period must be the smallest period in the model
68 System Generator Clocking Sample periods propagate with signals Some blocks can override the propagation Feedback loops often require explicit sample periods Most blocks are single rate (eq. logic & arithmetic) Many blocks are multi-rate: upsample & downsample, interpolate & decimate, serial-parallel conversion
69 Multiple Clock Domains Example Up-sample, filter, and down-sample a 25 MHz (40 ns) signal Error: sample rates not multiple of sample period
70 Multiple Clock Domains Example Up-sample, filter, and down-sample a 25 MHz (40 ns) signal
71 Sample Times Example Matlab lets us use sample time colors
72 Resource Estimation Any model of any size can be simulated Device resource limitations affect HW implementation Sysgen provides Resource Estimator block Adds up resource requirements before synthesis Good estimate - but not always right! Only post-place & route report is guaranteed
73 System Generator Tips Show port data types and sample times Use variables instead of constants, initialize in a script Avoid explicit sample periods (except for feedback loops) Use keyboard shortcuts ctrl-click to wire blocks ctrl-drag to duplicate selected blocks ctrl-d to update/error check model Use subsystems and give them meaningful names Too much precision is okay at first, use Error on Overflow to optimize later Avoid saturation and rounding options
74 System Generator Tips Black Box: Let s you import any VHDL or Verilog file to your design
75 System Generator Tips Black Box: Once assigned the HDL file, input/outputs are automatically added Can be used to simulate HDL files
76 System Generator Example IO control Blinking some LEDs
77 System Generator Example Input pin
78 System Generator Example Output pin
79 System Generator Example Pulse on output
80 System Generator Example HDL Generation
81 System Generator Example HDL Generation
82 Use generated HDL HDL generation completed Next steps in ISE A project is built for ISE
83 ISE design suit Xilinx design suit for working with it s FPGAs Create project Synthesis Implement Generate programming file
84 ISE environment
85 Synthesis-Implement-Generate Programming File
86 View RTL Schematics
87 Programming the Device
88 Programming the Device
89 Programming the Device
90 System Generator Example PWM
91 System Generator Example Deadtime circuit for PWM
92 System Generator Example ADC interface for AD7822/5/9 2MSPS up to 8 channels
93 System Generator Example Channel selection for AD7822/5/9
94 Efficiency example
95 Design Example DSPbuilder for Altera FPGAs Example: Back to back three-phase converter
96 Design Example Overview of the control blocks Each subsystem contains some of control functionalities.
97 Design Example Example: implementation of Park conversion
98 Summary Section III Introduction to FPGA Matlab/Simulink for Model-based Design and Implementation of FPGAs Xilinx System Generator Review of Fixed-point Representation Overview of HDL Coder
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103 Thanks for your attention! zolghadr@sharif.edu nenoroozi@gmail.com mahmoodshahbazi@gmail.com