PCI Express TM Architecture. PHY Electrical Test Considerations Revision 1.1

PCI Express TM Architecture PHY Electrical Test Considerations Revision 1.1 February 2007 i

PHY ELECTRICAL TEST CONSIDERATIONS, REVISION 1.1 REVISION REVISION HISTORY DATE 1.0 Initial Release. 4/26/2004 1.1 Revision Specification 1.1 Update 1/04/2007 1.1b Revision of Rev1.1 due to feedback to restore assertion numbers. 2/04/2007 PCI-SIG disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to update the information contained herein. Contact the PCI-SIG office to obtain the latest revision of this document. Questions regarding this document or membership in PCI-SIG may be forwarded to: Membership Services www.pcisig.com E-mail: administration@pcisig.com Phone: 503-291-2569 Fax: 503-297-1090 Technical Support techsupp@pcisig.com DISCLAIMER This document is provided "as is" with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. PCI Express is a trademark of PCI-SIG. All other product names are trademarks, registered trademarks, or servicemarks of their respective owners. Copyright 2004 PCI-SIG ii

TABLE OF CONTENTS1....INTRODUCTION 1 2. TEST ASSERTIONS... 3 2.1 TABLE OF ASSERTIONS - GENERAL... 3 2.2 TABLE OF ASSERTIONS - TRANSMITTER... 4 2.3 TABLE OF ASSERTIONS - RECEIVER... 9 2.4 TABLE OF ASSERTIONS SYSTEM BOARD... 10 2.5 TABLE OF ASSERTIONS ADD-IN CARD... 11 3. GENERAL TEST OVERVIEW AND TOPOLOGY... 12 3.1 OVERVIEW PHY ELECTRICAL TESTS... 12 4. TEST DESCRIPTIONS... 14 4.1 TEST 1.1 BIT RATE CLOCK ACCURACY... 14 4.2 TEST 1.2 SSC TRANSMITTER DATA AND MODULATION RATE... 14 4.3 TEST 1.3 SSC TRANSMITTER DATA RATE TRACKING... 15 4.4 TEST 1.4 NON-SSC TRANSMITTER DATA RATE (REQUIRED FOR INTEGRATOR LIST QUALIFICATION)... 15 4.5 TEST 1.5 SIGNAL QUALITY (REQUIRED FOR INTEGRATOR LIST QUALIFICATION)... 16 4.6 TEST 1.6 TX DC COMMON MODE VOLTAGE... 17 4.7 TEST 1.7 TX L0 TO ELECTRICAL IDLE TO L0... 17 4.8 TEST 1.8 RX DETECT - MAXIMUM VOLTAGE CHANGE... 18 4.9 TEST 1.9 RX DETECTION - HIGH RECEIVER IMPEDANCE... 18 4.10 TEST 1.10 RX DETECTION - LOW RECEIVER IMPEDANCE... 18 4.11 TEST 1.11 LANE-TO-LANE OUTPUT SKEW... 19 4.12 TEST 1.12 TX OUTPUT RISE/FALL TIME... 19 4.13 TEST 1.13 TX RMS AC COMMON MODE VOLTAGE... 20 4.14 TEST 1.14 RX DC COMMON MODE VOLTAGE... 20 4.15 TEST 1.15 TX ELECTRICAL IDLE VOLTAGE... 20 4.16 TEST 1.16 TX TRANSITIONS FROM ELECTRICAL IDLE... 21 4.17 TEST 1.17 RECEIVER DETECTION SEQUENCE... 21 4.18 TEST 1.18 BEACON OR WAKE#... 22 4.19 TEST 1.19 ELECTRICAL IDLE EXIT DETECTION... 22 4.20 TEST 1.20 RECEIVER DC DIFFERENTIAL MODE IMPEDANCE... 23 4.21 TEST 1.21 RECEIVER SENSITIVITY... 23 4.22 TEST 1.22 UNEXPECTED ELECTRICAL IDLE EXIT DETECTION... 24 4.23 TEST 1.23 MAXIMUM RECEIVER SKEW... 25 4.24 TEST 1.24 WAKE ENABLED PLATFORM VAUX POWER... 25 4.25 TEST 1.25 NON-WAKE ENABLED PLATFORM VAUX POWER... 26 4.26 TEST 1.26 PLATFORM POWER... 26 4.27 TEST 1.27 INITIAL ACTIVE LINK TRAINING... 27 4.28 TEST 1.28 DOWN-SHIFTING X8 TO X4... 27 4.29 TEST 1.29 BEACON PROPAGATION UPSTREAM... 27 4.30 TEST 1.30 WAKEUP INDICATION PROPAGATION UPSTREAM... 28 4.31 TEST 1.31 ADD-IN CARD POWER... 28 4.32 TEST 1.32 SYSTEM REFERENCE CLOCK PHASE JITTER (REQUIRED FOR INTEGRATOR LIST QUALIFICATION)... 29

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PHY Electrical Test Considerations for PCI Express* Architecture 1. Introduction This document provides the test criteria and test descriptions for PCI Express electrical testing. It is relevant for anyone building Root Complexes (RC), Endpoints (EP), Switches (SW), Bridges (BR), Add-in Expansion Cards (EC) and Motherboards (MB). This specification does not describe the full set of PCI Express electrical tests and assertions for these devices. The document is divided into two major areas. The first is requirements criteria and the second is test descriptions. This document provides a list of test assertions for PCI Express Electrical testing. The assertions provide a partial list of criteria that a device must meet as required by the PCI Express specifications. This revision includes assertions derived from the following specifications, ECNs and addendums: PCI Express Base Specification Revision 1.1 PCI Express Card Electromechanical Specification Revision 1.1 75w Power ECN PCI Express 1.1 Errata Future revisions to the referenced documents and/or additional specifications will need to be incorporated as they become available. Test descriptions provide more detailed information on how each of the assertions can be tested. In addition devices must also meet the applicable requirements and tests described in the latest versions of the following documents, as well as any other tests provided by the PCI-SIG: Electrical Test Considerations for PCI Express Architecture Config SpaceTest Considerations for PCI Express Architecture Platform Bios Test Considerations for PCI Express Architecture Link Test Considerations for PCI Express Architecture Transaction Test Considerations for PCI Express Architecture The test assertions provide a complete list of the requirements that are covered by this document. The test descriptions can be referenced to obtain specific details on how the assertions will be tested or for more information when the assertions by themselves are unclear. 1

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2. Test Assertions Test Assertions apply to all component types unless otherwise specified. The Table of Assertions is divided up into five sections. These sections are: Electrical PHY General test assertions that apply to all categories of PCI Express devices. Transmitter test assertions that apply to all transmitters. Receiver test assertions that apply to all receivers. Electrical Mechanical System board test assertions that are specific to motherboard/system board designs. These requirements encompass any PCI Express Riser boards up to and including the PCI Express connector. Add-in Card test assertions that are specific to Add-in Card implementations. 2.1 Table of Assertions - General Checklist Assertion # Assertion Description - General Test # General PHY.3.1#1 PHY.3.1#2 PHY.3.1#3 PHY.3.1#4 The bit rate clock source for transmitter and receiver must be +/- 300 ppm or better. If SSC is used, the data rate must be down-spread and modulated no more than 0.5% of the nominal data rate frequency. If SSC is used, the modulation rate must not exceed the range of 30 khz - 33Khz. If SSC is used, the two communicating ports must track modulation frequencies such that they never exceed 600 ppm difference. Test 1.1 Test 1.2 Test 1.2 Test 1.3

PHY ELECTRICAL TEST CONSIDERATIONS, REVISION 1.1 2.2 Table of Assertions - Transmitter Checklist Assertion # Assertion Description - Transmitter Test # Transmitter PHY.3.1#12 PHY.3.1#14 PHY.3.1#17 PHY.3.1#18 PHY.3.1#19 PHY.3.1#23 PHY.3.1#24 The TX DC common mode voltage (Vtx-dc-cm) must be held at the same value during all states. The allowable range for Vtxdc-cm is 0 to 3.6 V (+/- 100mV). Test 1.6 During the receiver detection sequence, the maximum change in voltage can be no more than 600mV (Vtx-rcv-detect) Test 1.8 The Receiver Detection circuit of the Transmitter must detect that the receiver terminations are in high impedance (or are disconnected) with the worst case interconnect capacitance to ground of 3 nf in parallel with 200k Ohms (Zrx-high-imp-dc Min). The Receiver Detection circuit of the Transmitter must detect that the receiver terminations are low impedance with the smallest AC coupling capacitance allowable of 75nF (Ctx Min) in series with 40 Ohms (Zrx-com-dc Min) to ground. Test 1.9 Test 1.10 The transmitter must meet all TX differential data signal specifications when transitioning from Electrical Idle to sending differential data within 20 UI after leaving an Electrical Idle condition (Ttx-idle-to-diff-data). After this 8 ns debounce interval the differential signal must meet the requirements of the Transmitter Compliance Eye Diagram of Figure 4-24*. *Note: Mobile Graphics that are designed in accordance with the Mobile Graphics Low Power Addendum must meet the transmitter eye requirements of the addendum. Test 1.16 Before entering Electrical Idle, a transmitter must send the Electrical Idle ordered-set, a K28.5 (COM) followed by three K28.3 (IDL). Test 1.7 After sending the last symbol of the Electrical Idle ordered-set the transmitter must be in a valid Electrical Idle state within 20 UI (Ttx-idle-set-to-idle). This 8 ns interval is a debounce time for the Transmitter to meet Electrical Idle voltage requirements after transitioning from L0. Test 1.7 4

Checklist Assertion # PHY.3.1#26 PHY.3.1#27 PHY.3.1#30 PHY.3.1#31 PHY.3.1#32 PHY.3.1#33 PHY.3.2#1 PHY.3.2#2 Assertion Description - Transmitter Test # The transmitter must meet the DC common mode voltage specification when transitioning into and out of Electrical Idle. It must maintain 25 mv DC CM (Vtx-cm-dc-line-delta) between data lines at all times and maintain 100 mv DC CM (Vtx-cm-dc-active-idle-delta) absolute delta between L0 and Electrical Idle states. Any time a transmitter enters Electrical Idle it must remain in electrical idle for a minimum of 50 UI (Ttx-idle-min). This 20 ns is utilized by the receiver to start looking for an Electrical Idle Exit after successfully receiving an Electrical Idle ordered set. A transmitter must start at a stable voltage prior to the detect common-mode shift. This voltage can be any stable common mode voltage between VDD and GND. During the receiver detection sequence, if the common-mode voltage on D+ and D- is equal to VDD, the common-mode voltage change must be towards GND. During the receiver detection sequence, if the common-mode voltage on D+ and D- is equal to GND, the common-mode voltage change must be towards VDD. During the receiver detection sequence, if the common-mode voltage on D+ and D- is between VDD and GND, the common-mode voltage change direction is important and must be in the opposite direction the voltage moved to get to this initial common-mode voltage. De-emphasis must be implemented* when multiple bits of the same polarity are output in succession. Subsequent bits are driven at a differential voltage level 3.5 db (+/- 0.5 db) below the first bit (Vtx-de-ratio) *Note: Mobile Graphics that are designed in accordance with the Mobile Graphics Low Power Addendum must have deemphasis disabled. All bits following a transition, with the exception of a Beacon signal, must be driven between the 0.8 and 1.2 V DIFFp-p (Vtx-diffp-p)* *Note: Mobile Graphics that are designed in accordance with the Mobile Graphics Low Power Addendum must be driven between 0.4 and 1.2 V Diff p-p (Vtx-diff p-p ) Test 1.6 Test 1.7 Test 1.17 Test 1.17 Test 1.17 Test 1.17 Test 1.5 Test 1.5

PHY ELECTRICAL TEST CONSIDERATIONS, REVISION 1.1 Checklist Assertion # PHY.3.2#3 PHY.3.2#4 PHY.3.2#5 PHY.3.2#6 PHY.3.2#7 PHY.3.2#8 PHY.3.2#9 PHY.3.2#11 PHY.3.2#13 Assertion Description - Transmitter Test # Support for Beacon is required for all universal PCI Express components that support a remote wakeup mechanism in order to function in form factors that require the use of Beacon. Otherwise it is optional. All Beacons must be transmitted and received on at least Lane 0 of multi-lane links. The Beacon is a DC balanced signal of periodic arbitrary data, which is required to contain some pulse widths 2 ns but no larger than 16 us.. The Beacon signal must be DC balanced (i.e., contain an equal number of 1 s and 0 s). Following pulses, DC balance must be restored within a maximum time of 32 us. The output Beacon voltage level must be at 6 db de-emphasis level for Beacon pulses with a width greater than 500 ns. The output Beacon voltage level can range between the transition (Vtx-diff p-p ) and corresponding 3.5 db voltage levels for Beacon pulses smaller than 500 ns. When a Switch receives a Beacon or wakeup indication at a Downstream Port, that component must propagate this Beacon or wakeup indication upstream. This wakeup indication must use the appropriate wakeup mechanism required by the system or form factor associated with the Upstream Port. While sending a Beacon, the maximum time between qualifying pulses (2ns x 16 us) can be no larger than 16 us. Support for Wake# is required for all universal PCI Express components that support a remote wakeup mechanism in order to function in form factors that require the use of Wake#. Otherwise it is optional. Test 1.18 Test 1.18 Test 1.18 Test 1.18 Test 1.18 Test 1.18 Test 1.29 Test 1.18 Test 1.18 6

Checklist Assertion # PHY.3.2#14 PHY.3.2#15 PHY.3.3#1 PHY.3.3#2 PHY.3.3#3 PHY.3.3#4 PHY.3.3#5 PHY.3.3#6 Assertion Description - Transmitter Test # Mobile Graphics topologies that are designed in accordance with the Mobile Graphics Low Power Addendum must meet the following requirements: Reduce the minimum TX output differential voltage by half while keeping the maximum TX output differential voltage the same. Reducing the minimum TX output differential voltage also reduces the worst case interconnect loss by a half, which implies shorter topology lengths. Transmitter de-emphasis must be disabled. Satisfy the Transmitter Compliance Eye Diagram specified in Figure 2-1 of the PCI Express Mobile Graphics Low Power Addendum v1.0 When a Bridge receives a wakeup indication (for example: PME), that component must propagate a wakeup indication upstream. This wakeup indication must use the appropriate wakeup mechanism required by the system or form factor associated with the Upstream Port. All PCI Express Device Types must meet the Transmitter eye diagram as specified in section 4.3.3.1, Fig. 4-24: Minimum Transmitter Timing and Voltage Output Compliance Specifications as measured at the package pins into the Compliance Test and Measurement Load, defined in section 4.3.3.2. The eye diagram must be valid for any 250 consecutive UIs. Each UI must be 400ps +/- 0.03% (+/-300ppm). This UI does not account for SSC dictated variations. The minimum D+/D- Tx output 20-80% rise and fall times must be 50ps as measured at the package pins of the transmitter. The time between the jitter median and the maximum deviation from the median must be 60 ps (Ttx-eye-medianto-max-jitter) The maximum allowable RMS AC (>30Khz) common mode voltage is 20mV (Vtx-cm-acp) as measured at the package pins of the transmitter using the Compliance Test and Measurement Load. The Electrical Idle differential peak output voltage (Vtx-idlediffp) must be 20 mv as measured at the package pins of the transmitter using the Compliance Test and Measurement Load. Test 1.5 Test 1.30 Test 1.5 Test 1.4 Test 1.12 Test 1.5 Test 1.13 Test 1.15

PHY ELECTRICAL TEST CONSIDERATIONS, REVISION 1.1 Checklist Assertion # PHY.3.3#7 PHY.3.3#8 PHY.3.3#9 Assertion Description - Transmitter Test # Electrical idle exit occurs when a signal larger than the minimum Vrx-idle-det-diffpp (65mV) is detected at a Receiver. Test 1.19 The Lane-to-Lane output skew (Ltx-skew) must be 1300 ps (500 ps + 2 UI). This is the static skew between any two Transmitter lanes within a single Link. Test 1.11 The minimum TX eye width (Ttx-eye) must be 280 ps as measured at the transmitter package pins using the Compliance Test and Measurement Load. This requirement is met if the transmitter meets the eye diagram requirements of section 4.3.3.1. Test 1.5 8

2.3 Table of Assertions - Receiver Checklist Assertion # Receiver Assertion Description - Receiver Test # PHY.3.1#10 When in the low impedance state, the receiver DC differential mode impedance must be 80 and 120 ohms (Zrx-diff-dc). This impedance is required during all LTSSM states. Test 1.20 PHY.3.1#11 The receiver DC common mode voltage must be 0 V +/- 10mV during all states. Test 1.14 PHY.3.4#1 The receiver must reliably receive all data that meets the differential receiver input specifications as shown in Figure 4-26: Minimum Receiver Eye Timing and Voltage Compliance Specification as shown in the PCI Express Base Specification. The parameters are specified using the Compliance Test and Measurement Load in place of the RX component pins. The RX component designer should provide additional margin to adequately compensate for package and silicon effects on the RX signal quality. Test 1.21 PHY.3.4#2 Receivers must reliably receive data when there is less than 150mV of AC (>30Khz) peak common mode input voltage (Vrx-cm-acp). Test 1.21 PHY.3.4#3 The receiver must detect an unexpected Electrical Idle state if the peak to peak differential voltage, as measured at the Rx pins, drops below 65mV (Vrx-idle-det-dffp-p min) for greater than 10ms as measured at the package pins of the Receiver. PHY.3.4#6 Receivers must be able to reliably receive data with up to 120 ps between the jitter median and maximum deviation from the median (Trx-eye-median-to-max-jitter) as measured using the Compliance Test and Measurement Load. PHY.3.4#9 Receivers must reliably receive and aggregate data when the total skew across all lanes on a Link does not exceed 20 ns (Lrx-skew). This includes variation in the length of a SKP ordered set at the RX as well as any delay differences arising from the interconnect itself. Test 1.22 Test 1.21 Test 1.23

PHY ELECTRICAL TEST CONSIDERATIONS, REVISION 1.1 2.4 Table of Assertions System Board Checklist Assertion # Assertion Description System Board Test # System Board EM1.4#4 EM2.4#5 EM3.4#7 EM4.4#14 EM5.4#16 EM6.4#20 EM7.4#22 Not In Checklist If the platform is wake enabled the +3.3Vaux rail must be supplied to all PCI Express add-in card connectors and be able to source 375 ma per connector. Test 1.24 If the platform is non-wake enabled (does not support the WAKE# signal) and provides the +3.3Vaux rail it must be able to source 20 ma per connector. Test 1.25 The power delivered to the PCI Express connectors must meet the specifications called out in Table 4-1* of the PCI Express Card Electromechanical Specification. *Note: System boards designed in accordance with the 75W Power ECN must meet the additional power requirements. Test 1.26 System boards must minimize jitter to within the values specified in table 4-4 of section 4.6.3 of the PCI Express Card Electromechanical Specification. Test 1.5 System boards must minimize the lane-to-lane skew to within 1.25 ns on all physical lanes as specified in table 4-5 of section 4.6.5 of the PCI Express Card Electromechanical Specification. Test 1.9 System boards must meet the System Board Transmitter Path Compliance Eye Requirements specified in table 4-8 of section 4.7.3 of the PCI Express Card Electromechanical Specification as measured after the connector with an ideal load. Test 1.5 System board receivers must meet the receiver sensitivity requirements as specified in the System board Card Minimum Receiver Path Sensitivity Requirements specified in table 4-9 of section 4.7.4 of the PCI Express Card Electromechanical Specification. Test 1.21 The system reference clock should not have more than 86ps of phase jitter between 1.5 and 22MHz. Test 1.32 10

2.5 Table of Assertions Add-in Card Checklist Assertion Description Add-in Card Test # Assertion # Add-in Card EM.2#27 EM.4#13 EM.4#15 EM.4#19 EM.4#21 EM.4#23 EM.6#4 Each component must enter the initial active Link Training state (exit electrical idle) within 80 ms of the end of PERST#. Test 1.27 Add-in cards must minimize jitter to within the values specified in table 4-4 of section 4.6.3 of the PCI Express Card Electromechanical Specification. Add-in cards must minimize the lane-to-lane skew to within 0.35 ns on all physical lanes as specified in table 4-5 of section 4.6.5 of the PCI Express Card Electromechanical Specification. Add-in cards must meet the Add-in Card Transmitter Path Compliance Eye Requirements specified in table 4-6 of section 4.7.1 of the PCI Express Card Electromechanical Specification as measured at the card edge-fingers. Add-in card receivers must meet the receiver sensitivity requirements as specified in the Add-in Card Minimum Receiver Path Sensitivity Requirements specified in table 4-7 of section 4.7.2 of the PCI Express Card Electromechanical Specification. Add-in cards must adhere to the maximum power numbers specified in the PCI Express Card Electromechanical Specification, Table 4-2* of Section 4.2 (Power Consumption). *Note: X16 graphics add-in cards designed in accordance with the 75W Power ECN must must not exceed the power requirements specified in the ECN. A x8 add-in card (and endpoint) must operate as a x4 card (and endpoint) when plugged into a x8 connector that has only the first four lanes routed. Test 1.5 Test 1.5 Test 1.5 Test 1.21 Test 1.31 Test 1.28

PHY ELECTRICAL TEST CONSIDERATIONS, REVISION 1.1 3. General Test Overview and Topology 3.1 Overview PHY Electrical Tests. The PHY electrical tests cover the electrical requirements defined in Chapter 4 of the PCI Express Base Specification and Chapter 2-4 of the PCI Express Card Electromechanical Specification. 12

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PHY ELECTRICAL TEST CONSIDERATIONS, REVISION 1.1 4. Test Descriptions 4.1 Test 1.1 Bit Rate Clock Accuracy Assertions Covered : PHY.3.1#1 Notes : Normal This test is only necessary when one side of a link does not directly use the root clock. In this case the device s secondary clock domain must track and replicate the root clock domain (including SSC if applicable). For each PCI Express Link: 1. Measure the bit rate clock source for the transmitter using a frequency counter or equivalent. If spread spectrum (SSC) is used a modulation domain analyzer is recommended for complete spread spectrum characterization of the 100 Mhz reference clock. 2. Measure the bit rate clock source for the receiver using a frequency counter or equivalent. If SSC is used a modulation domain analyzer is recommended for complete spread spectrum characterization of the 100 Mhz reference clock. 3. Verify that the bit rate clocks for the transmitter and receiver of each link are within 600 PPM of each other at all times in both SSC and non-ssc modes. One possible method is to use a real-time oscilloscope to capture outputs from both clocks simultaneously and use post-processing software to calculate and compare the frequency of each clock at any given time in the sample. Results Interpretation The bit rate clock sources for the transmitter and receiver are not within 600 PPM of each other at all times. 4.2 Test 1.2 SSC Transmitter Data and Modulation Rate Assertions Covered : PHY.3.1#2, PHY.3.1#3 Normal 1. Place transmitter under test in compliance pattern mode. 2. Measure transmitted waveform with high speed oscilloscope. To accurately test the minimum SSC modulation rate the measurement should be performed for at least 30.3 us. 3. Compute data rate from waveform data. Compute SSC modulation rate from waveform data. Results Interpretation 14

Data rate must be within 2.5 Gb/s + 300ppm/-5300ppm. This data rate does account for SSC dictated variations. Fmax = 2.50075 Gb/s, Fmin = 2.48675 Gb/s. - 2.50075 Gb/s = Nominal UI + 300 ppm, upper frequency limit. - 2.48675 Gb/s = Nominal UI 5000 ppm (SSC Budget) 300 ppm, lower frequency limit. SSC modulation rate must be within 30-33Khz. 4.3 Test 1.3 SSC Transmitter Data Rate Tracking Assertions Covered : PHY.3.1#4 Normal 1. Place one end of a PCI Express Link in loopback mode. 2. During data transfer measure the transmitter data rates on the upstream and corresponding downstream paths simultaneously. 3. Verify that the two communicating ports do not exceed 600 ppm difference. Note: This test can be performed during normal data transfers. Results Interpretation Data rates for the two communicating ports exceeds 600 ppm. 4.4 Test 1.4 Non-SSC Transmitter Data Rate (Required for Integrator List Qualification) Assertions Covered : PHY.3.1#1 Required for PCI-SIG Integrator List Qualification: Yes Compliance: Tested as part of Signal Quality SW. See Test 1.5 for detailed. Normal 1. Place transmitter under test in compliance pattern mode. 2. Measure transmitted waveform with high speed oscilloscope. 3. Compute data rate from waveform data. Data rate must be within 2.5 Gb/s +/- 0.03%. This data rate does not account for SSC dictated variations. 1. 2.50075 Gb/s = Nominal UI + 300 ppm, upper frequency limit. 2. 2.49925 Gb/s = Nominal UI 300 ppm, lower frequency limit. Results Interpretation The transmitter data rate is outside the specification limits.

PHY ELECTRICAL TEST CONSIDERATIONS, REVISION 1.1 4.5 Test 1.5 Signal Quality (Required for Integrator List Qualification) Assertions Covered : PHY.3.2#1, PHY.3.2#2, PHY.3.2#14, PHY.3.3#1, PHY.3.3#4, PHY.3.3#9, EM4.4#14, EM6.4#20, EM.4#13, EM.4#15, EM.4#19. Required for PCI-SIG Integrator List Qualification: Yes Description : Signal quality eye pattern test. This test is run on each transmitter for all lanes of a device link. This test measures the ability of a transmitter to transmit valid PCI Express signaling. A high speed oscilloscope with single ended active probes or direct feed to 50 ohm scope inputs are used to capture waveform data. Post processing software is used to translate the acquired data to an eye pattern. The transmit eye pattern obtained must meet the requirements specified at the probing location. Compliance: Signal Quality tests are required by the PCI-SIG for Add-In Card, System, and PCI-SIG Integrator List qualification. Oscilloscope vendor specific procedures, SIG-TEST software, and text fixtures for performing compliance tests can be downloaded from the PCI-SIG website at: http://www.pcisig.com/specifications/pciexpress/compliance/compliance_library SIG-TEST software Ver. 2.1 (or higher) is required for Rev1.1 compliance. Add-In Card Compliance Test Methodology: CBB1 (Rev1.1 Compliance Base Board) is used for Add-In card testing. For Add-In cards a clean clock is distributed from the CBB to the Add-In Card and each data lane is tested using SIG-TEST software. System Compliance Test Methodology: CLB (Compliance Load Board) is used for System card testing. For System testing, each data lane is tested using SIG-TEST software. Jitter Measurement Methodology: The methodology for recovering the clock from the data and performing jitter measurements is described in the PCI Express Jitter White Paper located at: http://www.pcisig.com/specifications/pciexpress/technical_library This test is run with devices in the Polling.Compliance state. The Polling.Compliance substate must be supported to perform this test. 1. Attach the Compliance Test Load on all of the transmitter data lines for the DUT. 2. Place transmitter in compliance pattern mode. 3. Measure transmitted waveform with high speed oscilloscope. 4. Confirm waveform is a compliance pattern 5. Measure Median-Max-Outlier jitter from acquired waveform 6. Generate eye pattern diagram from data. 7. Compare with PCI Express transmit eye pattern specified for the probing location. 8. Compute the time between the jitter median and the maximum deviation from the median. 16

Results Interpretation The transmitter signaling violates any of the eye pattern limits as specified at the probing location. Jitter is out of spec. 4.6 Test 1.6 TX DC Common Mode Voltage Assertions Covered : PHY.3.1#12, PHY.3.1#26 Notes : Normal 1. Using the math functions of an oscilloscope or using post processing software, measure the TX DC common mode voltage for all states. 2. Measure the absolute delta of DC common mode voltage between D+ and D-. The TX DC common mode voltage must fixed within the range of 0 3.6 V during all states. Any variation of this fixed value must be within +\- 100 mv. The absolute delta is greater than 25 mv. 4.7 Test 1.7 TX L0 to Electrical Idle to L0 Assertions Covered : PHY.3.1#23, PHY.3.1#24, PHY.3.1#27 Notes : This test requires the ability of the tester to control the bus state of the DUT. To make the appropriate measurements it is required to be able to configure the DUT to issue the Electrical Idle ordered-set and then transition normally to Electrical Idle. This can be done using implementation specific hardware or software methods. L0 1. Set up the oscilloscope to trigger when the transmitter transistions to electrical idle. 2. Force the DUT transmitter to issue the Electrical Idle ordered-set and transistion to Electrical Idle. 3. Verify that the DUT sends a K28.5 (COM) followed by three K28.3 (IDL) before entering Electrical Idle. 4. Verify the transmitter is in a valid Electrical Idle state within 20 UI of the last symbol of the Electrical Idle ordered-set. 5. Rerun the above steps while forcing the DUT to transition from L0 to Electrical Idle to L0 again using implementation specific hardware or software methods. 6. Verify the transmitter remains in Electrical Idle for a minimum of 50 UI.

PHY ELECTRICAL TEST CONSIDERATIONS, REVISION 1.1 The DUT doesn t sends a K28.5 (COM) followed by three K28.3 (IDL) before entering Electrical Idle. The transmitter is not in a valid Electrical Idle state within 20 UI of the last symbol of the Electrical Idle ordered-set. 4.8 Test 1.8 RX Detect - Maximum Voltage Change Assertions Covered : PHY.3.1#14 Notes : Description : Test is run on all device types. Normal 1. Measure the maximum change in voltage during receiver detection. The maximum voltage change during receiver detection is greater than 600 mv. 4.9 Test 1.9 RX Detection - High Receiver Impedance Assertions Covered : PHY.3.1#17 Notes : Normal 1. Place 200k Ohms (Zrx-com-high-imp-dc Min) to ground in parallel with 3nF on the transmitter data lines. 2. Verify that the associated TXs of the DUT do not enter CMM. The RX detection circuit of the TX detects a receiver present as determined by the DUT entering CMM mode. 4.10 Test 1.10 RX Detection - Low Receiver Impedance Assertions Covered : PHY.3.1#18 Notes : 18

Normal 1. Place 40 Ohms (Zrx-com-dc Min) in series with 75nF (Ctx Min) to ground on the transmitter data lines. 2. Verify that the associated TXs of the DUT enter CMM. The RX detection circuit of the TX does not detect a receiver present as determined by the DUT entering CMM mode. 4.11 Test 1.11 Lane-to-Lane Output Skew Assertions Covered : PHY.3.3#8 Notes : Designs must minimize the bit-to-bit skew on all physical lanes within a Link. A high speed oscilloscope with single ended active probes or direct feed to scope inputs are used to capture waveform data. DM or DP of two different lanes within the same Link should be monitored and compared (DM-to-DM or DP-to-DP) to determine the bit-to-bit skew between lanes. Description : This test is run on all device types L0, Polling.Compliance substate 1. Place all lanes of the device under test in compliance pattern mode. 2. Measure the bit-to-bit skew between all Lanes of the same Link. Ensure the measurement is made on equivalent data state transitions. Bit-to-Bit skew is out of specified limits. 4.12 Test 1.12 TX Output Rise/Fall Time Assertions Covered : PHY.3.3#3 Notes : This parameter is specified at the package pins of the component under test. For ease of measurement it can be measured at the connector with the understanding that a passing edge rate may still fail if measured at the package pins. However, a failing edge rate indicates that it would fail if measured at the package pins. Description : This test is run on all ports. Compliance pattern mode with 50 ohm loads to ground attached to the D+ and D- package pins. 1. Connect 50 ohm loads to ground to the package pins of the silicon under test. 2. Place the silicon under test in polling.compliance mode.

PHY ELECTRICAL TEST CONSIDERATIONS, REVISION 1.1 3. Measure the timing and voltage parameters within 0.2 inches of the package pins. The D+/D- tx output 20-80% rise and fall times are less than 50 ps. 4.13 Test 1.13 TX RMS AC Common Mode Voltage Assertions Covered : PHY.3.3#5 Notes : This parameter is specified at the package pins of the component under test. For ease of measurement it can be measured at the connector with the understanding that a failing voltage level may pass if measured at the package pins. However, a passing voltage indicates that it would likely pass if measured at the package pins. Description : This test is run on all ports. Compliance pattern mode with 50 ohm loads to ground attached to the D+ and D- transmitter package pins. 1. Place the lane under test in polling.compliance mode. 2. Measure RMS AC common mode voltage of the transmitted signal. The RMS AC common mode voltage is greater than 20mV. 4.14 Test 1.14 RX DC Common Mode Voltage Assertions Covered : PHY.3.1#11 Notes : Normal 1. Using a DVM, measure the DC voltage with respect to ground of RX D+ (PERpX) and D- (PERnX) for all lanes. Ensure the ground referenced is near the component silicon ground. The RX DC common mode voltage is > 0 +/- 10 mv for all states. 4.15 Test 1.15 TX Electrical Idle Voltage Assertions Covered : PHY.3.1#23, PHY.3.1#24, PHY.3.3#6 20

Notes : This test requires the ability of the tester to control the bus state of the DUT. To make the appropriate measurements it is required to be able to configure the DUT to issue the Electrical Idle ordered-set and then transition normally to Electrical Idle. This can be done using implementation specific hardware or software methods. L0 1. Set up the oscilloscope to trigger when the transmitter transistions to electrical idle. 2. Force the DUT transmitter to issue the Electrical Idle ordered-set and transistion to Electrical Idle. 3. Verify that the DUT sends a K28.5 (COM) followed by three K28.3 (IDL) before entering Electrical Idle. 4. Verify the transmitter is in a valid Electrical Idle state within 20 UI of the last symbol of the Electrical Idle ordered-set. 5. Verify that the Electrical Idle differential peak output voltage is no greater than 20 mv. The DUT doesn t sends a K28.5 (COM) followed by three K28.3 (IDL) before entering Electrical Idle. The DUT Electrical Idle differential peak output voltage is greater than 20 mv. 4.16 Test 1.16 TX Transitions from Electrical Idle Assertions Covered : PHY.3.1#19 Notes : This test requires the ability of the tester to control the bus state of the DUT. To make the appropriate measurements it is required to be able to configure the DUT to go into Electrical Idle and then transition to transmitting differential data. This can be done using implementation specific hardware or software methods. Electrical Idle 1. Set up the oscilloscope to trigger when the transmitter transistions from electrical idle to sending differential data. 2. Force the DUT transmitter to leave Electrical Idle. 3. Verify that the DUT meets all TX differential data signal specifications within 20 UI. The DUT fails to meet all TX differential data signal specifications within 20 UI after leaving electrical idle. 4.17 Test 1.17 Receiver Detection Sequence Assertions Covered : PHY.3.1#30, PHY.3.1#31, PHY.3.1#32, PHY.3.1#33

PHY ELECTRICAL TEST CONSIDERATIONS, REVISION 1.1 Notes : This test requires the ability of the tester to be able to initiate the receiver detection sequence using implementation specific hardware or software methods. Powered off 1. Set up the oscilloscope to trigger on the Receiver Detection sequence. 2. Verify that the transmitter starts at a stable voltage between VDD and GND prior to performing the common-mode shift. 3. If the common-mode voltage is equal to VDD the shift must be towards GND. 4. If the common-mode voltage is equal to GND the shift must be towards VDD. 5. If the common-mode voltage is between VDD and GND the shift must be in the opposite direction the voltage moved to get to this initial common-mode voltage. The DUT fails to meet the receiver detection requirements listed above. 4.18 Test 1.18 Beacon or Wake# Assertions Covered : PHY.3.2#3, PHY.3.2#4, PHY.3.2#5, PHY.3.2#6, PHY.3.2#7, PHY.3.2#8, PHY.3.2#11, PHY.3.2#13 Notes : This test requires the DUT to support Beacon or Wake#. If the DUT is a universal PCI Express component it must support Beacon or Wake# in order to function in form factors that require the use of Beacon or Wake#. Otherwise it is optional.. L2 1. Set up the oscilloscope to trigger on the DUT Beacon or Wake#. 2. Verify that the Beacon is transmitted on at least Lane 0 of multi-lane links, if supported. 3. Ensure Beacon pulse widths and DC balance meet the assertion requirements, if supported. 4. Verify the output Beacon voltage levels meet assertion requirments, if supported. 5. Verify the output Beacon pulse interval meets assertion requirements, if supported. 6. If Wake# is supported, verify the Wake# is generated in accordance with specification requirements. The DUT fails to meet the requirements listed above. 4.19 Test 1.19 Electrical Idle Exit Detection Assertions Covered : PHY.3.3#7 22

Notes : This test requires the ability of the tester to control the bus state of the DUT. To make the appropriate measurements it is required to be able to configure the DUT to issue the Electrical Idle ordered-set and then transition normally to Electrical Idle. This can be done using implementation specific hardware or software methods. Electrical Idle 1. Place the DUT into Electrical Idle. 2. Set up the oscilloscope to trigger when the transmitter leaves electrical idle. 3. Using a data generator or other type of signal source verify that the DUT exits Electrical Idle when a signal larger than 65 mv diffpp is detected at the DUT receiver. 4. Using a data generator or other type of signal source verify that the DUT does not exit Electrical Idle when a signal less than or equal to 65 mv diffpp is present at the DUT receiver. The DUT doesn t exit Electrical Idle when > 65mV diffpp is present at the receiver. The DUT exits Electrical Idle when less than or equal to 65mV diffpp is present at the receiver. 4.20 Test 1.20 Receiver DC Differential Mode Impedance Assertions Covered : PHY.3.1#10 Notes : The specification requires that this condition is met for all LTSSM states. However, this measurement would required the tester to be able to control the bus state of the DUT and keep it in the specific state until the measurement is made. For practical reasons this measurement is easiest to make with the DUT connected to the Compliance Test Load. Power off 1. Connect the DUT to the Compliance Test Load. 2. Apply power to the DUT. 3. Measure the DC differential mode impedance of each RX using a DVM. The DUT receiver DC differential mode impedance is not 80 and 120 ohms (Zrx-diff-dc). 4.21 Test 1.21 Receiver Sensitivity Assertions Covered : PHY.3.4#1, PHY.3.4#2, PHY.3.4#6, EM7.4#22, EM.4#21

PHY ELECTRICAL TEST CONSIDERATIONS, REVISION 1.1 Notes : Performance of this test requires an adjustable/calibrated PCI Express signal source or support for loopback and the ability to determine if the TX data of the calibrated source matches the RX data for the DUT. This could be a device with controllable drive strength, an adjustable loss and/or jitter transmission path or some other method that allows the tester to adjust the signal present at the receiver of the DUT to the minimum allowed by the specification. Description : Receiver sensitivity test. This test is run on each receiver for all lanes of a device link. This test measures the ability of a device to accurately receive valid PCI Express signaling. Normal 1. Calibrate the PCI Express signal source by measuring the signal quality as outlined in test 1.5. Adjust the signal quality to the minimum allowable as measured with the Compliance Test Load. 2. Connect the calibrated signal source to the DUT. 3. Verify that all data is accurately received by the DUT. 4. Inject up to 150mV of AC (>30Khz) peak common mode input voltage (Vrx-cm-acp) into the DUT RX path. 5. Verify that all data is accurately received by the DUT. 6. Inject signaling with up to 120 ps between the jitter median and maximum deviation from the median (Trx-eye-median-to-max-jitter) as measured using the Compliance Test and Measurement Load into the DUT RX path. 7. Verify that all data is accurately received by the DUT. An alternate method using loopback is as follows: 1. Adjust the loopback master transmitter jitter and amplitude such that it just meets the minimum eye pattern allowed by the specification. 2. Set the loopback master to detect errors on the returned path or connect a bus analyzer to the return path. 3. Connect the device under test and initiate loopback transfers. 4. Verify that the device reliably re-transmits the received data. 5. Any errors in the loopback master transmitter to loopback slave receiver path will show up as received EBD symbols. Results Interpretation The DUT fails to accurately receive the data. Receivers must reliably receive data when there is less than 150mV of AC (>30Khz) peak common mode input voltage (Vrx-cm-acp). Receivers must be able to reliably receive data with up to 120 ps between the jitter median and maximum deviation from the median (Trx-eye-median-to-max-jitter) as measured using the Compliance Test and Measurement Load. 4.22 Test 1.22 Unexpected Electrical Idle Exit Detection Assertions Covered : PHY.3.4#3 Notes : Performance of this test requires the tester to be able to determine when the DUT has detected an unexpected electrical idle condition. 24

Normal 1. Using a data generator or other type of controllable signal source, inject a signal less than 65 mv peak to peak differential voltage, as measured at the Rx pins (Vrx-idle-det-dffp-p min) for > 10ms. 2. Verify that the DUT detects the electrical idle state. The receiver does not detect an unexpected Electrical Idle state if the for greater than 10ms as measured at the package pins of the Receiver. 4.23 Test 1.23 Maximum Receiver Skew Assertions Covered : PHY.3.4#9 Notes : The test requires a specification compliant PCI Express device (known good device) with a known Skew that is within the specification requirements. To ensure the DUT has adequate margin for RX skew the known good device + DUT should have the maximum allowable skew. Normal 1. Connect the known good device to the DUT. 2. Verify that all data sent by the known good device is accurately received by the DUT. Results Interpretation The DUT fails to accurately receive the data. 4.24 Test 1.24 Wake Enabled Platform Vaux Power Assertions Covered : EM1.4#4 Notes : Due to the Vaux current limitations of system power supplies it may not be economical for the system to support the current requirements of 3 or more wakeup enabled PCI Express connectors under simultaneous full load conditions. Description : This test is run on all systems/platforms that support a wakeup mechanism. Two such mechanisms are defined. Beacon (using in-band signaling) and WAKE# (using sideband signaling). Normal and L2 1. Measure the +3.3 Vaux voltage with no load attached for each PCI Express connector. 2. Attach a 375 ma resistive load to the +3.3 Vaux rail for each PCI Express connector that is wakeup enabled.

PHY ELECTRICAL TEST CONSIDERATIONS, REVISION 1.1 3. Verify that the +3.3 Vaux rail voltage meets specification requirements for each connector under loaded conditions. Results Interpretation The +3.3 Vaux rail voltage does not meet specification requirements under unloaded and loaded conditions. 4.25 Test 1.25 Non-Wake Enabled Platform Vaux Power Assertions Covered : EM2.4#5 Description : This test is run on all systems/platforms that do not support WAKE# or Beacon (nonwake enabled). Normal 1. Measure the +3.3 Vaux voltage with no load attached for each PCI Express connector. 2. Attach a 20 ma resistive load to the +3.3 Vaux rail for each PCI Express connector. 3. Verify that the +3.3 Vaux rail voltage meets specification requirements under fully loaded conditions. Results Interpretation The +3.3 Vaux rail voltage does not meet specification requirements under unloaded and loaded conditions. 4.26 Test 1.26 Platform Power Assertions Covered : EM3.4#7 Description : This test is run on all systems/platform PCI Express connectors. Normal 1. Measure the voltage of all the power rails with no load attached for each PCI Express connector. 2. Fully load each power rail for all PCI Express connectors. 3. Verify that the voltage rails voltage meets specification requirements under fully loaded conditions. Results Interpretation The power delivered to the PCI Express connectors does not meet the specifications called out in Table 4-1 of the PCI Express Card Electromechanical Specification. 26

4.27 Test 1.27 Initial Active Link Training Assertions Covered : EM.2#27 Power off 1. Set up an oscilloscope to trigger on the end of PERST#. 2. Measure the time from the end of PERST# to the initial active Link Training state (exit electrical idle). Results Interpretation Each component must enter the initial active Link Training state (exit electrical idle) within 80 ms of the end of PERST#. 4.28 Test 1.28 Down-Shifting x8 to x4 Assertions Covered : EM.6#4 Notes : Performance of this test requires a PCI Express platform that uses a x8 connector with only the first 4 lanes routed. Description : This test is run on all x8 add-in cards and endpoints. Power off 1. Connect the DUT to the x8 connector on the test platform. This x8 connector should have only the first 4 lanes routed. 2. Apply power to the plaform. 3. Verify that the x8 addin-card is operating as a x4 card. Results Interpretation The x8 card doesn t operate properly or operates as a x1 card. 4.29 Test 1.29 Beacon Propagation Upstream Assertions Covered : PHY.3.2#9 Notes : This test requires the use of a device on a switch downstream port that supports Beacon. This device is referred to as the Beacon initiator in the overview below. Description : This test is run on Switches.

PHY ELECTRICAL TEST CONSIDERATIONS, REVISION 1.1 L2 1. Attach the Beacon initiator to a Switch downstream port. 2. Set up the oscilloscope to trigger on the downstream port Beacon while monitoring the Switch upstream port. 3. Verify that when the Switch receives a Beacon at a Downstream Port it propagates the Beacon upstream. 4. Verify that the upstream Beacon meets all of the requirements of Test 1.18 Beacon as described in the PHY Electrical tests section. 5. Repeat the above steps for all downstream ports. The DUT fails to meet the Beacon requirements listed above. 4.30 Test 1.30 Wakeup Indication Propagation Upstream Assertions Covered : PHY.3.2#9, PHY.3.2#15 Notes : This test requires the use of a bridge or switch and corresponding device that supports wakeup indication. This device is referred to as the wakeup initiator in the overview below. Description : This test is run on bridges and switches that support wakeup. L2 1. Attach the wakeup initiator to a Bridge or Switch downstream port. 2. Set up the oscilloscope to trigger on the downstream port wakeup indication while monitoring the DUT upstream port. 3. Verify that when the DUT receives a wakeup indication it propagates the wakeup indication upstream. This wakeup indication must use the appropriate wakeup mechanism required by the system or form factor associated with the Upstream Port. 4. Repeat the above steps for all downstream ports of the DUT. The DUT fails to propagate the wakeup indication as required. 4.31 Test 1.31 Add-in Card Power Assertions Covered : EM.4#23 Notes : Add-in card power consumption should be tested in all operating configurations to ensure worse case power consumption and power transients do not exceed specification requirements. For ease of testing this test assumes each supported TX lane of the card is running in CMM mode using the compliance base board as the test platform. Description : This test is run on all add-in cards while in CMM. CMM 28

1. Plug the DUT into the compliance base board (CBB) which ideally terminates each transmitter lane. 2. Apply power to the CBB. 3. Measure the current drawn by the DUT for each power rail. Results Interpretation The power drawn by the DUT does not meet the specifications called out in Table 4-1* of the PCI Express Card Electromechanical Specification. *Note: X16 graphics add-in cards designed in accordance with the 75W Power ECN must must not exceed the power requirements specified in the ECN. 4.32 Test 1.32 System Reference Clock Phase Jitter (Required for Integrator List Qualification) Assertions Covered : New test for Rev1.1, Not in Checklists Required for PCI-SIG Integrator List Qualification: Yes Description : Compliance: System eference clock phase jitter test. Signal quality eye pattern test. This test is run on the differential reference clock provided from the system connector. This test measures the phase jitter of the reference clock. A high speed oscilloscope with a differential probe is used to capture waveform data. Post processing software is used to measure the data period, apply the appropriate filter to the period data, and report the Pk-Pk phase jitter. System reference clock phase jitter is required for Rev1.1 Integrator List qualification. Oscilloscope vendor specific procedures, Clock Jitter software, and text fixtures for performing compliance tests can be downloaded from the PCI-SIG website at: http://www.pcisig.com/specifications/pciexpress/compliance/compliance_library Clock Jitter Tool Ver. 1.0 (or higher) is required for Rev1.1 compliance. The RefClk connector on the CLB (Compliance Load Board) is used for this test. Jitter Measurement Methodology: Refer to the Rev1.1 CEM specification for filtering algorithm and parameters required to meet the specification. This test is run after system power on. 9. Attach the CLB to the System under test. 10. Attach a high speed differential probe to the RefClk pins of the CLB. 11. Measure transmitted waveform with high speed oscilloscope. 12. Capture a trend plot (cycle or time) trend of the clock period. 13. Compute the Pk-Pk jitter of the filtered data using the PCI-SIG Clock Jitter tool. Results Interpretation Pk-Pk Jitter is out of spec.