PROGRAMMABLE MODULES SPECIFICATION OF PROGRAMMABLE COMBINATIONAL AND SEQUENTIAL MODULES. psa. rom. fpga THE WAY THE MODULES ARE PROGRAMMED NETWORKS OF PROGRAMMABLE MODULES EXAMPLES OF USES Programmable Modules
PROGRAMMABLE SEQUENTIAL ARRAYS (psa) x inputs n PLA outputs k z present state next state p State register p y Y PSA clk Figure.: PROGRAMMABLE SEQUENTIAL ARRAY (psa). Programmable Modules
Example.: IMPLEMENTATION OF SEQUENTIAL SYSTEMS USING psas SEQUENCE GENERATOR INPUTS: x {, } OUTPUTS: z {,,, 6, 7,, 4} FUNCTION: The transition and output functions x = : z = 4 7 x = : z = 6 x = : z = x = : z = Programmable Modules
4 CLK z z z z State 4 7 4 7 (a) Case x = CLK z z z z State 6 6 (b) Case x = Figure.: TIMING SEQUENCES IN Example.. Programmable Modules
Example. (cont.) 5 y k = k = k k 6 x 6 k 7 k 4 k 4 7 x Y K y {, 4, 5, 8, 9,,,, 5} don t care states K = xy y xy y y ky ky y ky y Y = y y k Y = y y y y k Y = y y Y = y k y k y y Programmable Modules
x k (from state register) y y y y -- programmable connection 6 -- connection made 4 5 6 7 8 9 4 5 6 7 8 y y y y k y y y y y y k y k y k x y y xy y y ky ky y k y y 9 8 7 6 5 4 next state K Y Y Y Y CLK k STATE REGISTER y y y y present state z z z output z Figure.: psa IMPLEMENTATION IN Example.. Programmable Modules
READ-ONLY MEMORIES (rom) 7 E En Address Inputs x x x n- n X k ROM z k- z Outputs Figure.4: READ-ONLY MEMORY (rom) Programmable Modules
EXAMPLE. 8 Address Contents x z Programmable Modules
9 E x x z z z z - - Z Z Z Z NOR Array Vdd (a) pull-up devices Gnd x x Binary decoder word Gnd word word Gnd word E enable three-state buffers z z z z Figure.5: mos IMPLEMENTATION OF A 4 4 READ-ONLY MEMORY: a) THE FUNCTION; b) THE CIRCUIT. (b) Programmable Modules
IMPLEMENTATION OF SWITCHING FUNCTIONS USING roms ROM (5x5) c in x x x x y y y y 7 8 BINARY DECODER 49 56 5 + Input/output mapping: x x c in x x + y y y y c out z z z z z c out z z z Figure.6: rom-based IMPLEMENTATION OF A 4-BIT ADDER. Programmable Modules
IMPLEMENTATION OF SEQUENTIAL SYSTEMS USING roms INPUTS: x = (x, x ), x i {, } OUTPUTS: z {,, } STATE: y = (y, y ), y i {,, } FUNCTION: The transition and output function P S x x y y,,,,,,,,,,,, Y Y, z NS, Output Programmable Modules
ROM address ROM contents y y x x Y Y z present state x x next state CLK ROM 6 X Y Y S y y z - - - - - - - - - - - - (a) next state (b) output Figure.7: rom-based implementation of a sequential system: a) network; b) rom contents. Programmable Modules
TYPES OF rom MODULES MASK-PROGRAMMED rom FIELD-PROGRAMMABLE rom (proms) ERASABLE rom (eprom) ELECTRICALLY ERASABLE rom(flash-memory) or eeprom Programmable Modules
NETWORKS OF PROGRAMMABLE MODULES 4 f (x 4, x, x, x, x ) = one-set(,,,,6,,7) f (x 4, x, x, x, x ) = one-set(5,7,9,,) rom MODULE: 8 x = (x (), x () ) x () = (x 4, x ) x () = (x, x, x ) Programmable Modules
5 x 4 x x x x E= En DECODER Row 4 5 6 7 E E E E ROM ROM ROM ROM Z Z Z Z Z Z f f Figure.8: rom-based NETWORK FOR THE IMPLEMENTATION OF TWO FUNCTIONS. Programmable Modules
x n-,..., x k x k-,..., x 6 n-k N = n-k E En DECODER N- N- k k k k En En En ROM N- ROM N- ROM * * * * three-state outputs (a) f N = n-k x k-,..., x k k En k En k En ROM N- ROM N- ROM x n-,..., x k n-k E N- N- En MULTIPLEXER (b) f Figure.9: IMPLEMENTATIONS OF FUNCTIONS WITH n VARIABLES: a) roms AND DECODER; b) roms AND MULTIPLEXER Programmable Modules
LARGE NUMBER OF SFs 7 E n En n En n En x n-,..., x n ROM ROM ROM f f Figure.: rom-based IMPLEMENTATION OF LARGE NUMBER OF SWITCHING FUNCTIONS. Programmable Modules
FIELD PROGRAMMABLE GATE ARRAYS (FPGA) 8 Switch matrix Input/Output Blocks Programmable Logic Block Switches Input/Output Blocks Input/Output Blocks Input/Output Blocks Wiring channel Figure.: ORGANIZATION OF AN fpga chip. Programmable Modules
BASIC APPROACHES IN PROGRAMMING OF FPGAs 9 - ON-CHIP STATIC RAM LOADED WITH CONFIGURATION BIT PATTERNS (sram-fpgas). (volatile) - ANTIFUSE-PROGRAMMED DEVICES PROGRAMMED ELECTRICALLY TO PROVIDE CONNECTIONS THAT DEFINE CHIP CON- FIGURATION - ARRAY-STYLE eprom and eeprom PROGRAMMED DEVICES USING SEVERAL plas AND A SHARED INTERCONNECT MECHANISM Programmable Modules
SRAM cell Transistor Closed switch Open switch (a) LUT (Look-Up Table) a b c d MUX y=d a b c Decoder y=f(a,b,c) SRAM cells SRAM cells (b) (c) Figure.: sram fpgaprogrammable COMPONENTS: (a) Switch. (b) 4-input multiplexer. (c) Look-up table (LUT). Programmable Modules
Example: XILINX XC X Outputs A B C D Look -Up Table (LUT) G F D Set S Q Y CLK K R Reset SRAM-controlled multiplexer K B C K D A CLB X Y CLB symbol Figure.: A CONFIGURABLE LOGIC BLOCK (CLB) (Courtesy of Xilinx, Inc.) Programmable Modules
A B C D A 4-variable function G F B Q (a) A A B C A -variable function F C D A Q A -variable function M U X F D Q C D A -variable function G A B C D A -variable function G Q (c) Q (b) Figure.4: sram-fpga options in generating functions: (a) One 4-variable function. (b) Two -variable functions. (c) Selection between two functions of variables. (Courtesy of Xilinx, Inc.) Programmable Modules
PROGRAMMABLE INTERCONNECT. DIRECT INTERCONNECTIONS BETWEEN HORIZONTALLY AND VERTICALLY ADJACENT clbs PROVIDE FAST SIGNAL PATHS BETWEEN ADJACENT MODULES. GENERAL-PURPOSE INTERCONNECT CONSISTS OF VERTICAL AND HORIZONTAL WIRING SEGMENTS BETWEEN SWITCH MATRICES. LONG VERTICAL AND HORIZONTAL LINES SPAN THE WHOLE clbarray Programmable Modules
Two vertical long lines Global long line 4 B C K A CLB X Y CLB D Direct connection Horizontal long line Switch Matrices CLB CLB General-purpose interconnect CLB CLB General-purpose interconnect Figure.5: PROGRAMMABLE INTERCONNECT. (Courtesy of Xilinx, Inc.) Programmable Modules
Example.5: BCD ADDER MODULE 5 IMPLEMENT A ONE-DIGIT BCD ADDER USING A sram-fpgamodule OF XC TYPE INPUTS: x = (x, x, x, x ), x j {, }, x {,..., 9} y = (y, y, y, y ), y j {, }, y {,..., 9} c in {, } OUTPUTS: s = (s, s, s, s ), s j {, }, s {,..., 9} c out {, } FUNCTION: x + y + c in = c out + s COMPUTE 6u + v = x + y + c in {,..., 9} using a 4-bit binary adder Programmable Modules
Example.5 (cont.) 6 THREE CASES: BCD OUTPUT u = v 9 s = v c out = u = v > 9 s = v = (v + 6) mod 6 c out = u = s = v + 6 = v + 6 c out = s = (v + 6)mod6 if u = or v v otherwise c out = if u = or v otherwise THE CONDITION u = or v CORRESPONDS TO SWITCHING EXPRESSION t = u v v v v Programmable Modules
Example.5 (cont.) 7 x y x y x y x y u 4-bit Adder v v v v t -bit Adder c out s s s s c in Figure.6: IMPLEMENTATION OF BCD ADDER MODULE Programmable Modules
Example.5 (cont.) 8 SIMPLIFICATION OF THE -BIT ADDER s = v t(v v ) s = v tv s = v t MOREOVER, s = v c out = t Programmable Modules
9 CLB CLB CLB CLB CLB CLB CLB u t s s s c in s x y x y x y x y v v v A X Y B C K D v v v v v v v v v t t t u v c out Programmable Modules
DESIGN WITH FPGAs INVOLVES INTENSIVE USE OF CAD TOOLS AND MODULE LIBRARIES Design entry : A SCHEMATIC ENTRY OR A BEHAVIORAL DESCRIPTION Implementation : PARTITION OF DESIGN INTO SUBMODULES THAT CAN BE MAPPED ONTO clbs, PLACEMENT OF SUBMODULES ONTO CHIP, AND ROUTING OF SIGNALS TO CONNECT THE SUBMODULES Design verification : IN-CIRCUIT TESTING SIMULATION, AND TIMING ANALYSIS Programmable Modules