Controller IP for a Low Cost FPGA Based USB Device Core

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National Conference on Emerging Trends in VLSI, Embedded and Communication Systems-2013 17 Controller IP for a Low Cost FPGA Based USB Device Core N.V. Indrasena and Anitta Thomas Abstract--- In this paper controller for a low cost FPGA based USB device core is described. During the last years, the well known USB standard became the basic communication module for digital systems, replacing the previous and traditional series and parallel communication interfaces. It provides many advantages. USB characteristics include low cost, easiness of use and simple construction. USB standard must be considered as something to be used in any kind of device requiring data communication with other systems or devices. FPGA become more powerful in terms of available reconfigurable hardware resources. A low cost USB device core mainly consists of two parts; the USB controller and the real world interface. Though the USB IP is designed be synthesizable onto an FPGA, it can easily be used to generate the hardware for an ASIC. This paper mainly concentrates on the USB controller. The USB controller IP is capable of carrying out low speed (1.5Mbps) USB transactions. T Keywords --- USB, FPGA, CRC, Endpoint, Transceiver I. INTRODUCTION HE well known USB standard became the basic communication module for digital systems, replacing the previous and traditional series and parallel communication interfaces. It provides many advantages. USB characteristics include low cost, easiness of use and simple construction. USB standard must be considered as something to be used in any kind of device requiring data communication with other systems or devices. The benefits of USB are autoconfiguration, low cost, expandability, hot-plugging and outstanding performance. It also provides power to the bus, enabling many peripherals to operate without the added need for an AC power adapter. USB is now the most used interface to connect devices like mouse, keyboards, PDAs, game-pads, joysticks, scanners, digital cameras, printers, personal media players and flash drives to personal computers. The developments in the electronics industry are aimed to make devices as small as possible and to get them to market quickly. So the designers focus on FPGAs rather than the traditional PCBs. Older connections like RS232 ports can only be connected to one device at a time. The USB standard was developed to overcome the shortcomings of older interfaces to peripheral devices for PCs. USB allows multiple devices to be attached to a single port enabling greater system flexibility. The standard makes interfacing to the PC extremely easy for the end user. This paper aims to develop a controller IP for low cost FPGA based USB device core. The USB controller is responsible for the correct transmission and reception of data through USB interface. It consists of a transmitter and a receiver. USB controller has error checking features built into it. It uses CRC logic for error checking [7]. The controller designed here is having 16 endpoints. It is possible to connect up to 127 devices. The USB controller IP is capable of carrying out low speed (1.5Mbps) USB transactions. Though the USB IP is designed be synthesizable onto an FPGA, it can easily be used to generate the hardware for an ASIC. II. USB DEVICE CORE The FPGA based USB device core mainly consists of a USB controller and a real world interface [1]. Fig 1 shows the schematics of the USB device core. The USB controller is responsible for the correct transmission and reception of data through USB interface. It consists of a transmitter and a receiver. USB controller has error checking features built into it. It uses CRC logic for error checking. The real world interface is used to connect the USB core to external world (say PC). This can be achieved using a Pico Blaze microcontroller which will be in charge of handling the upper level protocol and interfacing with the outside world. There are numerous commercial USB controller IPs and ICs available. The majority of USB controllers available are in the form of ICs. Controller IP has many advantages compared to controller ICs. Controller IP occupies less space on the FPGA or ASIC. It is easy to modify. The main goal of the paper was to develop a USB device controller IP in VHDL that is synthesizable on an FPGA. The simulation tool used here is ModelsimSE6.5. The development board used to test the IP contains a Xilinx SPARTAN XC3S50 FPGA. The low speed USB 1.1 standard was implemented. The data transfer rate of low speed USB is 1.5Mbps. N.V. Indrasena, Department of ECE, Viswajyothi College of Engineering & Technology, Vazhakulam, Kerala, India, Pin 686 670. E- mail:indrasena123@gmail.com Anitta Thomas, Department of ECE, Viswajyothi College of Engineering & Technology, Vazhakulam, Kerala, India, Pin 686 670. E- mail:anittathomas@rediffmail.com

National Conference on Emerging Trends in VLSI, Embedded and Communication Systems-2013 18 III. Fig 1: USB Core Schematics USB CONTROLLER - ARCHITECTURE The USB device controller IP provides an interface that can be used by a USB device to communicate with the USB host controller. Device designers who want to develop ASICs or FPGAs with USB capabilities do not have to use a separate chip if the controller is in the form of IP. The USB controller IP provides a series of endpoints that are used by the USB device to communicate through the controller. The USB Controller places no restrictions on the number of endpoints that it can handle. The number of endpoints is only limited by the device s driver and the device specific logic. Fig2 shows a general block diagram of how the controller is used [2]. The device specific logic can be an FPGA, microcontroller or any other device that is able to generate and read digital signals. The USB controller transmits data to and from endpoints for device specific logic. The device specific logic must let the controller know when it is ready to send data. The device driver will probe the USB controller regularly to see if valid data is in a specific endpoint. If there is data in the requested endpoint the USB controller will send its contents. The USB controller IP can be broken into three subsystems. The three major components of the system under design are the transmitter, receiver and controller. Transmitter and receiver form the data path of the USB controller. The controller is essentially a Mealy state machine. It keeps track of the different sections of a USB transaction. The first state of the USB controller is the start state. The next three states of the controller are used to receive the token packet from the host. The following four states break up the data packet or construct a data packet depending on whether the transaction is IN, OUT or SETUP. The final two states are used to either send or receive a token depending on the type of transaction. Fig 3 shows the block diagram of transmitter. The transmitter must undertake several tasks. It converts data from parallel to serial. This data will then have to be bit stuffed. The USB protocol requires a zero to be stuffed after every six consecutive ones. This is required so that there is a transition at least every six bits of the transmitter output. The stuffed binary data is eventually converted to NRZI encoding before being sent through the transceiver to the USB host. The transmitter is also responsible for forming data and handshake packets before sending them to the host. The transmitter is responsible for calculating the 16-bit CRC included in data packets sent to the host. Fig 2: Block Diagram of USB Controller Fig 3: Block Diagram Transmitter

National Conference on Emerging Trends in VLSI, Embedded and Communication Systems-2013 19 The receiver s function is the inverse of the transmitter. The receiver is more complicated than the transmitter and requires further functionality. The receiver has capabilities to calculate both 5-bit CRC and 16-bit CRC [7]. This is necessary since the receiver receives token packets, which contain a 5-bit CRC and data packets, which contain a 16-bit CRC. The transmitter compares the value it calculated with that received from the packets. If there is any inconsistency, retransmission is requested from the host. Block diagram of receiver [9] is shown in fig 4. Fig 4: Block Diagram Receiver Information generator generates the data packets to be transmitted by the transmitter. It converts the information from the device specific logic to the prescribed field formats that can be transmitted through the USB cable. The multiplexer of the transmitter is responsible for selecting what type of byte should be sent by the transmitter. The byte that should be sent is decided by the controller through the pid select port. Enable the receiver and then transmitter. When the clock arrives, the transmitter starts to send the packets. Initially it sends the synchronization sequence followed by the PID of the packet [6]. Then it sends the CRC value. After these three bytes, it starts to send the data bytes. In order to send the binary sequence, the parallel data is first converted to serial form using a shift register. The bit stuffing is done if needed. If six consecutive 1 s comes in a sequence, the transmitter inserts a zero with that sequence. This zero is the stuffed bit and it introduces a transition in the transmitted signal level. After bit stuffing, the data is encoded using an NRZI encoder [5]. In this encoding scheme, the bit 0 is represented by a transition in the signal level and no transition for bit 1. Then it is transmitted through the D+ line of USB cable. The transmitter also generates the 16bit CRC value. A DPLL module is used for synchronization [3]. Differential signalling is used to provide noise immunity [4]. Two lines (D + and D - ) are used for the transmission of the data. Depending upon the data to be transmitted, the differential lines change their voltage levels. IV. SIMULATION RESULTS The simulation code for USB controller was written in VHDL language. The VHDL code for the USB controller was divided into several modules. There are five modules and they are device transmitter, device receiver, transmit memory, receive memory and DPLL. Function of transmit memory is to store the data bytes to be transmitted. Here the memory stores 24 data bytes. In the transmitter section, different processes are written for the NRZI encoder, bit stuffing, parallel to serial conversion, byte counter, transmit state machine and CRC calculator. DPLL module is used to generate the USB clock to provide proper synchronization between transmitter and receiver. Receiver will detect the synchronization pattern and decode the PID. The NRZI encoded data is decoded to the original bit sequence and stuffed bits are removed. Then the serial data is grouped into bytes and stored in the receive memory. So receiver module performs NRZI decoding, stuffed bit removal, serial to parallel conversion and detection of error. CRC checks are used for error detection. All the modules are coded using VHDL. A test bench program was written to simulate the USB controller. ModelSim is a widely used logic simulation tool for verification and debugging of digital circuits. Here ModelSim6.5 simulator is used. Fig 5 shows the input data bytes in decimal form. When the transmit enable signal is applied, the differential data line (tx_dp) values changes according to the input bytes. Fig 5: Input Data in Decimal form and Transmitted Signal

National Conference on Emerging Trends in VLSI, Embedded and Communication Systems-2013 20 Fig 6 shows the received data bytes in decimal form. When buffer write signal goes high, the buffer data byte is written to the receive memory. The device utilization summary of the USB controller is given in fig 8. From the device utilization summary, it is clear that the USB controller utilizes a small percentage of the available resources. Logic Utilization Number of Slice Flip Flops Number of 4 input LUTs Total Number of 4 input LUTs Used Available Utilization 309 1536 20% 472 1536 30% 685 153 44% Fig 8: Device Utilization Summary Fig 6: Received Data in Decimal Form V. IMPLEMENTATION RESULTS The transmission of data packet was implemented using Spartan3 FPGA (XC3S50) [8]. Due to the lack of input switches, only the transmit enable, receive enable, reset and data bytes to be transmitted are given as the external inputs. The FPGA clock frequency is divided in order to implement the controller on FPGA. An input data indicator is provided using an LED to indicate when to input the external data bytes. Received data bytes are displayed using 8 LEDs. Synthesis converts the VHDL description into a set of primitives or components that can be assembled in the target FPGA. A synthesizer such as Xilinx Foundation series will have to be used in this process. Xilinx ISE8.1 is the synthesis tool used here. Implementation is done using Spartan3 FPGA. Fig 7 shows the inputs and outputs for the implementation. A clock divider is used to divide the clock signal from the FPGA. Receiver and transmitter are enabled. When the DATA_CLK_IND goes high, the system will fetch the input data byte. Four data bytes are transmitted. After the OUT_FLAG goes high, the output LEDs displays the received data bytes. After displaying four data bytes the RX_COMPLETE signal goes high. VI. CONCLUSION USB controller IP was developed which is in the form of synthesizable VHDL code. USB controller IP can be used by System on Chip designers to interface easily to the USB bus system. Due to the limited clock frequency of the FPGA development board, controller for low speed USB was implemented. Low speed USB has a maximum bandwidth of 1.5MHz. However a high speed USB compatible controller can easily be developed with minimal modification to this IP. The goal of the project to develop a USB Controller IP for FPGA designs was achieved. The simulation of the resulting system was done and verified the inputs and outputs. The transmission of data packets was implemented using Spartan3 FPGA. To complete the USB core modifications should be made to this IP. We must add the Pico Blaze microcontroller to interface this to the external world. Because of the limitations of the development board, the IP is low speed USB compatible. There is a minimal modification required to the IP to make the IP usable in high-speed USB 1.1 devices. To handle isochronous transfers, the IP should operate at high speeds. The only major modification that is required is that the IP must be able to detect start of frame packets and make sure they are received in numerical order. ACKNOWLEDGEMENT The authors would like to thank the staff members of Viswajyothi College of Engineering and Technology for their valuable guidance, help and support. Fig 7: Implementation Inputs and Outputs REFERENCES [1] Elio A.A, De Maria, Gho.E, Maidana C.E, A Low cost FPGA based USB device core, 4th Southern Conference on Programmable Logic, 2008, pp. 149 154. [2] Panchbudhe N.S, Prof.Shriramwar S.S, Jichkar G.A, FPGA Implementation of USB 2.0 receiver protocol, International Journal of Advances in Electronics Engineering, pp.199-203 [3] Aweya, J, Digital phase-locked loop for frequency distribution over packet networks, 37th Annual Conference on IEEE Industrial Electronics Society, 2011, pp. 2192 2197. [4] Yeh, P, Wang A., Tseng, B.C, High speed data transmission common mode noise suppression - application to USB 2.0 and IEEE 1394,

National Conference on Emerging Trends in VLSI, Embedded and Communication Systems-2013 21 Proceedings of the 4th International Symposium on Electronic Materials and Packaging, 2002, pp.488 491. [5] Sridhar K, Prasad S, Punitha L, Karunakaran S, EMI issues of universal serial bus and solutions, 8th International Conference on Electromagnetic Interference and Compatibility, 2003, pp.97 100 [6] Don Anderson, Universal Serial Bus System Architecture, 2 nd edition, MindShare Inc. 2001 [7] Universal Serial Bus Specification. September 1998. [8] Spartan 3 FPGA family datasheet.v.2.2. Product specification DS- 099.XilinxInc. May 2007. [9] Myilone Anandarajah, USB Controller IP for FPGA Designs, 2001 Indrasena N V was born in India. She took her B.Tech in Electronics and Communication Engineering from College of Engineering, Munnar (2004). She has done her M.Tech in VLSI and Embedded System at Viswajyothi College of Engineering & Technology, Muvattupuzha, during the year 2010-2012. Her fields of interest include Linear Integrated Circuits and Digital System Design. Anitta Thomas was born in India. She took her B.Tech in Electronics and Communication from Mahatma Gandhi University College of Engineering, Thodupuzha(2004) and M.Tech from Model Engineering College, Thrikkakkara (2010).She is currently working as Assistant Professor in Viswajyothi College of Engineering and Technology, Muvattupuzha.

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