Register Transfer Methodology II

Similar documents
Outline. Register Transfer Methodology II. 1. One shot pulse generator. Refined block diagram of FSMD

EITF35: Introduction to Structured VLSI Design

HIERARCHICAL DESIGN. RTL Hardware Design by P. Chu. Chapter 13 1

Outline HIERARCHICAL DESIGN. 1. Introduction. Benefits of hierarchical design

Overview. Ram vs Register. Register File. Introduction to Structured VLSI Design. Recap Operator Sharing FSMD Counters.

Digital Design Using Digilent FPGA Boards -- Verilog / Active-HDL Edition

Sequential Circuit Design: Principle

SKEE2263 Sistem Digit

EMBEDDED SOPC DESIGN WITH NIOS II PROCESSOR AND VHDL EXAMPLES

Sequential Circuit Design: Principle

EE414 Embedded Systems Ch 2. Custom Single- Purpose Processors: Hardware

RTL HARDWARE DESIGN USING VHDL. Coding for Efficiency, Portability, and Scalability. PONG P. CHU Cleveland State University

3 Designing Digital Systems with Algorithmic State Machine Charts

Hardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University

Register Transfer Level in Verilog: Part I

Contents. Chapter 9 Datapaths Page 1 of 28

Advanced Digital Design Spring 2011 Final Examination Time Limit: 2 Hours

Least Common Multiple (LCM)

Control and Datapath 8

COE 561 Digital System Design & Synthesis Introduction

ECE 545 Lecture 12. Datapath vs. Controller. Structure of a Typical Digital System Data Inputs. Required reading. Design of Controllers

CS 151 Final. (Last Name) (First Name)

Embedded Systems Design: A Unified Hardware/Software Introduction. Chapter 2: Custom single-purpose processors

Synthesis of Language Constructs. 5/10/04 & 5/13/04 Hardware Description Languages and Synthesis

The Need of Datapath or Register Transfer Logic. Number 1 Number 2 Number 3 Number 4. Numbers from 1 to million. Register

UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS PART-A (2 MARKS)

Outline. Finite State Machine. 2. Representation of FSM. 1. Overview on FSM

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS

R10. II B. Tech I Semester, Supplementary Examinations, May

MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences

Lecture 3: Modeling in VHDL. EE 3610 Digital Systems

Lecture 12 VHDL Synthesis

Digitaalsüsteemide disain

Synthesis from VHDL. Krzysztof Kuchcinski Department of Computer Science Lund Institute of Technology Sweden

CHAPTER 4: Register Transfer Language and Microoperations

Controller FSM Design Issues : Correctness and Efficiency. Lecture Notes # 10. CAD Based Logic Design ECE 368

FPGA for Software Engineers

VHDL for Synthesis. Course Description. Course Duration. Goals

Finite State Machine with Datapath

EECE-4740/5740 Advanced VHDL and FPGA Design. Lecture 3 Concurrent and sequential statements

Programmable Logic Devices II

Debouncing a Switch. A Design Example. Page 1

CHAPTER - 2 : DESIGN OF ARITHMETIC CIRCUITS

Verilog for High Performance

CMSC 611: Advanced Computer Architecture

INSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad ELECTRONICS AND COMMUNICATIONS ENGINEERING

VHDL Essentials Simulation & Synthesis

Digital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University

Injntu.com Injntu.com Injntu.com R16

RTL Design (Using ASM/SM Chart)

MLR Institute of Technology

UCT Algorithm Circle: Number Theory

Design of Embedded DSP Processors

System Synthesis of Digital Systems

EITF35: Introduction to Structured VLSI Design

(ii) Simplify and implement the following SOP function using NOR gates:

HANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment

Cpr E 281 FINAL PROJECT ELECTRICAL AND COMPUTER ENGINEERING IOWA STATE UNIVERSITY. FINAL Project. Objectives. Project Selection

St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad

PINE TRAINING ACADEMY

Outline. CPE/EE 422/522 Advanced Logic Design L05. Review: General Model of Moore Sequential Machine. Review: Mealy Sequential Networks.

VHX - Xilinx - FPGA Programming in VHDL

Designing with VHDL and FPGA

Topics. Verilog. Verilog vs. VHDL (2) Verilog vs. VHDL (1)

RISC IMPLEMENTATION OF OPTIMAL PROGRAMMABLE DIGITAL IIR FILTER

VLSI DESIGN (ELECTIVE-I) Question Bank Unit I

Two HDLs used today VHDL. Why VHDL? Introduction to Structured VLSI Design

Rational numbers as decimals and as integer fractions

Embedded Systems Design: A Unified Hardware/Software Introduction. Chapter 2: Custom single-purpose processors

Sequential Circuits. inputs Comb FFs. Outputs. Comb CLK. Sequential logic examples. ! Another way to understand setup/hold/propagation time

Principles of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.

EITF35: Introduction to Structured VLSI Design

University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering

Counters, Timers and Real-Time Clock

VALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS

TSEA44 - Design for FPGAs

EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis

REGISTER TRANSFER LANGUAGE

BeiHang Short Course, Part 2: Description and Synthesis

CS222: Processor Design

Luleå University of Technology Kurskod SMD152 Datum Skrivtid

L11: Major/Minor FSMs

The MIPS Processor Datapath

SoC Design for the New Millennium Daniel D. Gajski

Combinational and sequential circuits (learned in Chapters 1 and 2) can be used to create simple digital systems.

ECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog

A New High Level Model Based on Integer Equations to Check CTL Properties in VHDL Environment

MODELING LANGUAGES AND ABSTRACT MODELS. Giovanni De Micheli Stanford University. Chapter 3 in book, please read it.

Hours / 100 Marks Seat No.

EN164: Design of Computing Systems Lecture 06: Lab Foundations / Verilog 2

TABLE OF CONTENTS CHAPTER NO. TITLE PAGE NO.

Programming with HDLs

Digital System Design with SystemVerilog

EN2911X: Reconfigurable Computing Lecture 05: Verilog (2)

VHDL. VHDL History. Why VHDL? Introduction to Structured VLSI Design. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language

isplever Reed-Solomon Encoder User s Guide October 2005 ipug05_03.0

Chapter 4. The Processor

1. What is y-chart? ans: The y- chart consists of three domains:- behavioral, structural and geometrical.

קורס VHDL for High Performance. VHDL

CSE 140L Final Exam. Prof. Tajana Simunic Rosing. Spring 2008

Transcription:

Register Transfer Methodology II Chapter 12 1

Outline 1. Design example: One shot pulse generator 2. Design Example: GCD 3. Design Example: UART 4. Design Example: SRAM Interface Controller 5. Square root approximation circuit Chapter 12 2

1. One shot pulse generator Sequential circuit divided into Regular sequential circuit: w/ regular next-state logic FSM: w/ random next-state logic FSMD: w/ both Division for code development; no formal definition; Some design can be coded in different types FSMD is most flexible One shot pulse generator as an example Chapter 12 3

Basic block diagram Chapter 12 4

Refined block diagram of FSMD Chapter 12 5

Regular sequential circuit. E.g., mod-10 counter Chapter 12 6

FSM. E.g., edge-detection circuit Chapter 12 7

FSMD. E.g., multiplier Chapter 12 8

One-shot pulse generator I/O: Input: go, stop; Output: pulse gois the trigger signal, usually asserted for only one clock cycle During normal operation, assertion of go activates pulse for 5 clock cycles If go is asserted again during this interval, it will be ignored If stop is asserted during this interval, pulse will be cut short and return to 0 Chapter 12 9

FSM implementation Chapter 12 10

Chapter 12 11

Chapter 12 12

Chapter 12 13

Regular sequential circuit implementation Based on a mod-5 counter Use a flag FF to indicate whether counter should be active Code difficult to comprehend Chapter 12 14

Chapter 12 15

FSMD Implementation Chapter 12 16

Chapter 12 17

Chapter 12 18

Comparison: FSMD is most flexible and easy to comprehend What happens to the following modifications The delay extend from 5 cycles to 100 ccyles The stop signal is only effective for the first 2 delay cycles and will be ignored otherwise Chapter 12 19

Programmable one-shot generator The desired width can be programmed. The circuit enters the programming mode when both go and stop are asserted The desired width shifted in via go in the next three clock cycles Chapter 12 20

Can be easily extended in ASMD chart How about FSM and regular sequential circuit? Chapter 12 21

2. GCD circuit GCD: Greatest Common Divisor E.g, gcd(1, 10)=1, gcd(12,9)=3 GCD without division: Chapter 12 22

Pseudo algorithm Chapter 12 23

Modified pseudo algorithm w/o while loop Chapter 12 24

ASMD chart Chapter 12 25

VHDL code Chapter 12 26

Chapter 12 27

Chapter 12 28

What is the problem of this code? Another observation Chapter 12 29

Chapter 12 30

What is the performance now? Can we do better with more hardware resources Chapter 12 31

Square root approximation circuit A example of data-oriented (computationintensive) application Equation: 0.125x and 0.5y corresponds to shift right 3 bits and 1 bit Chapter 12 32

Pseudo code: Chapter 12 33

Direct data-flow implementation Chapter 12 34

Chapter 12 35

Requires one adder and six subtractors Code contains only concurrent signal assignment statements The order is not important. Sequence of execution is embedded in the flow of data Chapter 12 36

Data flow graph Shows data dependency Node (circle): an operation Arches: input and output variables Note that there is limited degree of parallelism At most two operations can be perform simultaneously Chapter 12 37

RT methodology can be used to share the operator Tasks in converting a dataflow graph to an ASMD chart Scheduling: when a function (circle) can start execution Binding: which functional unit is assigned to perform the operation In square root algorithm, all operations can be performed by a modified addition unit No function unit is needed for shifting Chapter 12 38

Scheduling with two functional units Chapter 12 39

Scheduling with one functional unit Chapter 12 40

ASMD chart Chapter 12 41

Registers can be shared as well reduce the number of unique variables A variable can be reused if its value is no longer needed E.g., Chapter 12 42

Chapter 12 43

VHDL code Needs to manually code the data path two insure functional units sharing One unit for abs and min One unit for abs, min, - and + Can be implemented by using an adder/subtractor with special input and output routing circuits Chapter 12 44

Chapter 12 45

Chapter 12 46

Chapter 12 47

Chapter 12 48

High-level synthesis Convert a dataflow code into ASMD based code (RTL code). RTL code can be optimized for performance (min # clock cycles), area (min # functional units) etc. Perform scheduling, binding Minimize # registers and muxes Mainly for computation intensive applications (e.g., DSP) Chapter 12 49

2024 © technodocbox.com Privacy Policy | Terms of Service | Feedback