Chapter 0 Introduction

Similar documents
Jin-Fu Li. Department of Electrical Engineering. Jhongli, Taiwan

EE3032 Introduction to VLSI Design

Chapter 1 Introduction. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

3D systems-on-chip. A clever partitioning of circuits to improve area, cost, power and performance. The 3D technology landscape

EECS 598: Integrating Emerging Technologies with Computer Architecture. Lecture 10: Three-Dimensional (3D) Integration

Moore s s Law, 40 years and Counting

Il pensiero parallelo: Una storia di innovazione aziendale

More Course Information

DFT Trends in the More than Moore Era. Stephen Pateras Mentor Graphics

Packaging Technology for Image-Processing LSI

Moore s Law: Alive and Well. Mark Bohr Intel Senior Fellow

Jin-Fu Li. Department of Electrical Engineering. Jhongli, Taiwan

3D-IC is Now Real: Wide-IO is Driving 3D-IC TSV. Samta Bansal and Marc Greenberg, Cadence EDPS Monterey, CA April 5-6, 2012

Physical Design Implementation for 3D IC Methodology and Tools. Dave Noice Vassilios Gerousis

From Boolean Algebra to Smart Glass

3D Hetero-Integration Technology for Future Automotive Smart Vehicle System

Emerging IC Packaging Platforms for ICT Systems - MEPTEC, IMAPS and SEMI Bay Area Luncheon Presentation

Interconnect Challenges in a Many Core Compute Environment. Jerry Bautista, PhD Gen Mgr, New Business Initiatives Intel, Tech and Manuf Grp

VLSI Design Automation

DFT-3D: What it means to Design For 3DIC Test? Sanjiv Taneja Vice President, R&D Silicon Realization Group

High Performance Memory in FPGAs

WLSI Extends Si Processing and Supports Moore s Law. Douglas Yu TSMC R&D,

Part 1 of 3 -Understand the hardware components of computer systems

BREAKING THE MEMORY WALL

Xilinx SSI Technology Concept to Silicon Development Overview

ECE 486/586. Computer Architecture. Lecture # 2

From 3D Toolbox to 3D Integration: Examples of Successful 3D Applicative Demonstrators N.Sillon. CEA. All rights reserved

OVERCOMING THE MEMORY WALL FINAL REPORT. By Jennifer Inouye Paul Molloy Matt Wisler

VLSI Design Automation. Calcolatori Elettronici Ing. Informatica

edram to the Rescue Why edram 1/3 Area 1/5 Power SER 2-3 Fit/Mbit vs 2k-5k for SRAM Smaller is faster What s Next?

VLSI Design Automation

3D TECHNOLOGIES: SOME PERSPECTIVES FOR MEMORY INTERCONNECT AND CONTROLLER

TechSearch International, Inc.

Embedded Quality for Test. Yervant Zorian LogicVision, Inc.

HW Trends and Architectures

3D SYSTEM INTEGRATION TECHNOLOGY CHOICES AND CHALLENGE ERIC BEYNE, ANTONIO LA MANNA

High Volume Manufacturing Supply Chain Ecosystem for 2.5D HBM2 ASIC SiPs

When Less Is More: Bigger & Faster Memory in Shrinking Packages for the Mobile Market

inemi Roadmap Packaging and Component Substrates TWG

Vertical Circuits. Small Footprint Stacked Die Package and HVM Supply Chain Readiness. November 10, Marc Robinson Vertical Circuits, Inc

Power dissipation! The VLSI Interconnect Challenge. Interconnect is the crux of the problem. Interconnect is the crux of the problem.

CAD for VLSI. Debdeep Mukhopadhyay IIT Madras

Advanced Heterogeneous Solutions for System Integration

Emerging Platforms, Emerging Technologies, and the Need for Crosscutting Tools Luca Carloni

TechSearch International, Inc.

ROADMAP FOR 2017 EDITION

PicoServer : Using 3D Stacking Technology To Enable A Compact Energy Efficient Chip Multiprocessor

Lecture 1: Introduction

Five Emerging DRAM Interfaces You Should Know for Your Next Design

ECE 471 Embedded Systems Lecture 2

Introduction. Summary. Why computer architecture? Technology trends Cost issues

Processor and DRAM Integration by TSV- Based 3-D Stacking for Power-Aware SOCs

Monolithic 3D Integration using Standard Fab & Standard Transistors. Zvi Or-Bach CEO MonolithIC 3D Inc.

Problem 2 If the cost of a 12 inch wafer (actually 300mm) is $3500, what is the cost/die for the circuit in Problem 1.

Advancing high performance heterogeneous integration through die stacking

Japanese two Samurai semiconductor ventures succeeded in near 3D-IC but failed the business, why? and what's left?

SEMI 大半导体产业网 MEMS Packaging Technology Trend

Introduction to Embedded Systems. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University

TABLE OF CONTENTS III. Section 1. Executive Summary

Microelettronica. J. M. Rabaey, "Digital integrated circuits: a design perspective" EE141 Microelettronica

Wafer Level Packaging The Promise Evolves Dr. Thomas Di Stefano Centipede Systems, Inc. IWLPC 2008

Organization. 5.1 Semiconductor Main Memory. William Stallings Computer Organization and Architecture 6th Edition

3-Dimensional (3D) ICs: A Survey

ECE/CS 757: Advanced Computer Architecture II Interconnects

EE586 VLSI Design. Partha Pande School of EECS Washington State University

for High Performance and Low Power Consumption Koji Inoue, Shinya Hashiguchi, Shinya Ueno, Naoto Fukumoto, and Kazuaki Murakami

William Stallings Computer Organization and Architecture 6th Edition. Chapter 5 Internal Memory

3D Integration & Packaging Challenges with through-silicon-vias (TSV)

ARCHIVE Françoise von Trapp Editorial Director 3D InCites ABSTRACT

The Foundry-Packaging Partnership. Enabling Future Performance. Jon A. Casey. IBM Systems and Technology Group

Advanced Packaging For Mobile and Growth Products

Chapter 1: Introduction to Parallel Computing

ECE520 VLSI Design. Lecture 1: Introduction to VLSI Technology. Payman Zarkesh-Ha

Introduction 1. GENERAL TRENDS. 1. The technology scale down DEEP SUBMICRON CMOS DESIGN

Testable SOC Design. Sungho Kang

Calibrating Achievable Design GSRC Annual Review June 9, 2002

VLSI IMPLEMENTATION OF L2 MEMORY DESIGN FOR 3-D INTEGRATION G.Sri Harsha* 1, S.Anjaneeyulu 2

Lecture-14 (Memory Hierarchy) CS422-Spring

Microarchitecture Overview. Performance

Supercomputing and Mass Market Desktops

IP CORE Design 矽智產設計. C. W. Jen 任建葳.

William Stallings Computer Organization and Architecture 8 th Edition. Chapter 18 Multicore Computers

Thermo Mechanical Modeling of TSVs

machine cycle, the CPU: (a) Fetches an instruction, (b) Decodes the instruction, (c) Executes the instruction, and (d) Stores the result.

Computer Architecture!

Designing Systems in CHIPS Interconnect Fabric. Puneet Gupta Sudhakar Pamarti Ankur Mehta

L évolution des architectures et des technologies d intégration des circuits intégrés dans les Data centers

Packaging Challenges. Driven By The IoT And Migration To The Cloud. Presented by: W. R. Bottoms

Introduction to Embedded Systems

NVIDIA'S DEEP LEARNING ACCELERATOR MEETS SIFIVE'S FREEDOM PLATFORM. Frans Sijstermans (NVIDIA) & Yunsup Lee (SiFive)

IoT as Enabling Technology for Smart Cities Panel PANEL IEEE RTSI

DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422)

Technology Trends Presentation For Power Symposium

Computer Performance

Microprocessor Trends and Implications for the Future

Introduction to Embedded Systems. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University

From Majorca with love

Emergence of Segment-Specific DDRn Memory Controller and PHY IP Solution. By Eric Esteve (PhD) Analyst. July IPnest.

Heterogeneous, Distributed and Scalable Cache-Coherent Interconnect

Network on Chip Architecture: An Overview

Transcription:

Chapter 0 Introduction Jin-Fu Li Laboratory Department of Electrical Engineering National Central University Jhongli, Taiwan

Applications of ICs Consumer Electronics Automotive Electronics Green Power Electronics Biomedical Electronics Jin-Fu Li, EE, NCU 2

System on Chip SOC a product class and design style that integrates technology and design elements from other system driver classes (microprocessor unit, embedded memory, analog/mixed-signal component as well as reprogrammable logic) into a wide range of high-complexity, high-value semiconductor products (ITRS 2011) Jin-Fu Li, EE, NCU 3

Trends for SOC Consumer Portable Driver Source: ITRS 2011 Jin-Fu Li, EE, NCU 4

SOC Consumer Portable Driver Architecture Source: ITRS 2011 Jin-Fu Li, EE, NCU 5

SOC Consumer Portable Design Complexity Source: ITRS 2011 Jin-Fu Li, EE, NCU 6

SOC Consumer Portable Power Consumption Source: ITRS 2011 Jin-Fu Li, EE, NCU 7

SOC Consumer Portable Processing Performance Source: ITRS 2011 Jin-Fu Li, EE, NCU 8

Source: ITRS 2010 Jin-Fu Li, EE, NCU 9

Modern SOC Design Challenges Power issue: Energy consumption, power dissipation, power delivery Reliability issue Variability Soft error (single-event upset) Device degradation Yield issue. Y=e -AD Jin-Fu Li, EE, NCU 10

Architecture of Current SOC Chips Multi-core chip architecture Use multiple identical cores to design a chip Network-on-chip communication infrastructure Multiple point-to-point data links interconnected by switches (i.e., routers) μ Engine RAM unit Compute unit DDR2 Controller DDR2 Controller Source: IEEE Computer, 2005. Source: IEEE Micro, 2007. Jin-Fu Li, EE, NCU 11

Examples SPARC V9 (Sun) Source: IEEE JSSC, 2006. 4x4 mesh built with Xpipes library components Cell Processor (IBM) Teraflops processor (Intel) Source: IEEE JSSC, 2006. Niagara2 (Sun) Source: IEEE Micro, 2007. Source: IEEE JSSC, 2008. Source: IEEE Micro, 2007. Jin-Fu Li, EE, NCU 12

Cell Processor (JSSC, Jan. 2006) Jin-Fu Li, EE, NCU 13

Example: Niagara2 & POWER6 (JSSC, 2008) Niagara2 (Sun) POWER6 (IBM) Design-for-Testability Features: 1. Logic BIST 2. BIST for arrays 3. BISR for arrays 4. Design-for-Testability Features: 1. 32 Scans + ATPG 2. BIST for arrays 3.. Jin-Fu Li, EE, NCU 14

Example: SPARC (JSSC, 2011) Process: TSMC 40nm Metal layers (Cu): 11 Transistor types: 4 # of Cores: 16 6MB L2 cache Die area: 377mm 2 # of pins: 2117 Jin-Fu Li, EE, NCU 15

Number of Transistors per Microprocessor Chip Source: Proceedings of IEEE, May 2012. Jin-Fu Li, EE, NCU 16

Transistor Cost Source: Proceedings of IEEE, May 2012. Jin-Fu Li, EE, NCU 17

Downsizing Rates of Audio/Video Products Source: Proceedings of IEEE, May 2012. Jin-Fu Li, EE, NCU 18

Fundamental Elements of Electronic Systems Processor (multi-core architecture) Computation Memory Data (Content) Communication Interface; Bus; Network Jin-Fu Li, EE, NCU 19

3D Integration Technology Technology evolution Bipolar CMOS Multicore 3D integration + System-in-package (3D-SiP) System-in-package stacking dies using bonding wires Source: ISQED, 2008. Jin-Fu Li, EE, NCU 20

Emerging IC Design Technology 3D IC 3D integration stacking dies using through silicon via (TSV) Chemical & Bio Sensors Other Sensors, Imagers Nano Device MEMS RF ADC DAC Memory Stack Processor Energy/Power Source: IBM, 2008. Source: Proceedings of IEEE, Jan. 2009 Jin-Fu Li, EE, NCU 21

Advantages of 3D IC: Heterogeneous Integration Combine disparate technologies DRAM, flash, RF, etc. Combine different technology nodes For example: 65nm technology and 45nm technology Chemical & Bio Sensors Other Sensors, Imagers Nano Device MEMS RF ADC DAC Memory Stack Processor Energy/Power Source: Proceedings of IEEE, Jan. 2009 Jin-Fu Li, EE, NCU 22

Advantages of 3D IC: Low Power & Small Form Factor Power SOB SIP 3D-IC Technology Jin-Fu Li, EE, NCU 23

Advantages of 3D IC: High Bandwidth 3D IC allows much more IO resources than 2D IC For example, Stacking of processor and memory Memory Memory CPU CPU Bandwidth is limited by IOs Many TSVs are allowed for high bandwidth transportation Jin-Fu Li, EE, NCU 24

Applications of 3D ICs Short-term Midium-term Long-term Memory wall Memory capacity Smart or Trusted Memory Heterogeneous Integration Source: Proceedings of IEEE Source: Proceedings of IEEE Heterogeneous Integration & High Complexity Systems (terabyte of internet traffic/sec; petabytes of data stored in the cloud; etc.) Jin-Fu Li, EE, NCU 25

Possible Applications: Smart Phone An important development direction is the interaction with the user, and sensorbased smartphones. Motion sensors, accelerometers and gesture reading devices should improve a lot this interaction, and combined with the connectivity widespread, it should create a new set of opportunities for consumers. Unfortunately, an aspect which won't mean a major leap in smartphones development is battery life. Augmented Reality Map Jin-Fu Li, EE, NCU 26

Possible Applications: Automotive Cloud Service System Source: IEEE Computer, June 2012. Requirement: high bandwidth (real time) and low power; small form factor Jin-Fu Li, EE, NCU 27

Possible Applications: Active Safety for Automotive Subaru introduced the EyeSight system version 2, introduced in 2010, which can stop a vehicle traveling at up to 30 km/h via a stereo camera mounted inside the front window. A 3D image processor analyzes the images that two cameras capture and estimates the distance to the obstacle. Source: IEEE Computer, June 2012. Jin-Fu Li, EE, NCU 28

Possible Applications: Healthcare Adhesive-bandage-type sensor Source: Proceedings of IEEE, May 2012. Jin-Fu Li, EE, NCU 29

Possible Applications: Healthcare Bionic ear Source: Proceedings of IEEE, May 2012. Jin-Fu Li, EE, NCU 30

Possible Applications: Superspecs Source: Mail Online, 2012. Jin-Fu Li, EE, NCU 31

Challenges of 3D-IC Implementations Yield Design for resiliency Thermal Can we overcome it? Test Reliability Source: IBM, 2008. Jin-Fu Li, EE, NCU 32

What will You Learn from This Course? Memory array Memory Subsystems Control Input Processor Link Input/Output Datapath Output CPU To/from network I/O Source: IEEE JSSC, 2008. Chip Architecture Low-Power Design Testing Jin-Fu Li, EE, NCU 33