Jin-Fu Li. Department of Electrical Engineering. Jhongli, Taiwan
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1 EEA001 VLSI Design Jin-Fu Li Advanced Reliable Systems (ARES) Lab. Department of Electrical Engineering National Central University Jhongli, Taiwan
2 Contents Syllabus Introduction to CMOS Circuits MOS Transistor Theory Fabrication of CMOS Integrated Circuits Electrical Characteristics of CMOS Circuits Elements of Physical Design Combinational Circuit Design Sequential Circuit Design Introduction to 3D Integration Technology Using TSV Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2
3 Reference Books Syllabus N. H. E. Weste and D. Harris, CMOS VLSI Design, a Circuits and Systems Perspective, Third Edition. Addison Wesley, S.-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, McGRAW-HILL, Grading Homework 35% (Overdue homework is not accepted!) (Mid+Final) 65% [Max(Mid, Final)x60%+Min(Mid, Final)x40%] Prerequisite Digital logic design, Microelectronics Key dates Midterm: 18:30-20:30, Thur., Nov. 18, E1-120 Final: 18:30-20:30, Thur., Jan. 13, E1-120 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3
4 Date Week 1 (9/16) Week 2 (9/23) Week 3 (9/30) Week 4 (10/7) Week 5 (10/14) Week 6 (10/21) Week 7 (10/28) Week 8 (11/4) Week 9 (11/11) Week 10 (11/18) Week 11 (11/25) Week 12 (12/2) Week 13 (12/9) Week 14 (12/16) Week 15 (12/23) Week 16 (12/30) Week 17 (1/6) Week 18 (1/13) Lecture Schedule Note 11/18: Midterm 1/13: Final Exam Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4
5 Teaching assistant 周哲緯 (E1-417) Syllabus Course Website: Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5
6 What is This Course all About? Scopes of VLSI design Digital circuits Analog circuits Mixed-signal circuits Memory circuits This course will cover the following contents CMOS devices and manufacturing technology; CMOS inverters and gates; propagation delay; noise margins; CMOS power dissipation; sequential circuits; arithmetic circuits (option); interconnect; memories (option). What will you learn? Understanding, designing, and optimizing digital circuits with respect to different quality metrics: area, speed, and power dissipation Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6
7 ENIAC - The First Electronic Computer (1946) Source: J. Rabaey, 2004 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7
8 The Transistor Revolution First transistor (Bell Labs, 1948) Source: J. Rabaey, 2004 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8
9 The First Integrated Circuits ECL 3-input Gate (bipolar logic), Motorola 1966 Source: J. Rabaey, 2004 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9
10 Intel 4004 Microprocessor 1000 transistors,1 MHz operation, Source: J. Rabaey, 2004 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10
11 Intel Pentium (IV) microprocessor Source: J. Rabaey, 2004 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11
12 Itanium (JSSC, Jan. 2006) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12
13 Binary Counter Present state Next state a b A B A = a b + ab 2MOSt transistors t 6MOSt transistors t a A b B CK B = a b + ab CLR ~20 MOS transistors Source: Prof. V. D. Agrawal Advanced Reliable Systems (ARES) Lab Jin-Fu Li, EE, NCU 13
14 Moore s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months UMBER OF GRATED FUNCT TION OG 2 OF THE NU NTS PER INTEG LO COMPONE Source: J. Rabaey, Electronics, April 19, Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14
15 Evolution in Complexity Source: J. Rabaey, 2004 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15
16 Transistor Counts 1,000,000 K 1 Billion Transistors 100,000 Pentium III 10,000 Pentium II Pentium Pro 1,000 i486 Pentium 100 i Source: Intel Projected Source: J. Rabaey, 2004 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16
17 Moore s law in Microprocessors Source: Intel Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17
18 Die Size Growth 100 Die size (m mm) P6 Pentium proc ~7% growth per year ~2X growth in 10 years Year Die size grows by 14% to satisfy Moore s Law Source: J. Rabaey, 2004 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18
19 Frequency Mhz) Freq quency ( Doubles every 2 years 286 P6 Pentium proc Year Lead Microprocessors frequency doubles every 2 years Source: J. Rabaey, 2004 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19
20 Power Dissipation 100 Po ower (Wa atts) P6 Pentium proc Year Lead Microprocessors power continues to increase Source: J. Rabaey, 2004 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20
21 Power Will Be a Major Problem ower (W Watts) P Pentium proc 5KW 18KW 1.5KW 500W Year Power delivery and dissipation will be prohibitive Source: J. Rabaey, 2004 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21
22 Power Density ) (W/cm2 Density Power Rocket Nozzle Nuclear Reactor Hot Plate P6 Pentium proc Year Power density too high to keep junctions at low temp Source: J. Rabaey, 2004 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22
23 Not Only Microprocessors Digital Cellular Market (Phones Shipped) Units 48M 86M 162M 260M 435M (data from Texas Instruments) Source: J. Rabaey, 2004 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23
24 Not Only Microprocessors Automotive Electronics Source: Time-Triggered Technology Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24
25 Productivity Trends 10,000,000 10,000 hip (M) 1,000,000 1,000 Com plexity Lo ogic Transi istor per C 100, , , Logic Tr./Chip Tr./Staff Month. x x x x x x x x 58%/Yr. compounded Complexity growth rate 21%/Yr. compound Productivity it growth rate 100,000,000 10,000, ctivity Staff - Mo. 1,000, ,000 10,000 1, Produc K) Trans./S ( Source: Sematech Complexity outpaces design productivity Courtesy, ITRS Roadmap Source: J. Rabaey, 2004 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25
26 Why Scaling? Technology shrinks by 0.7/generation With every ygeneration can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x But How to design chips with more and more functions? Design engineering population does not double every two years Hence, a need for more efficient i design methods Exploit different levels of abstraction Source: J. Rabaey, 2004 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26
27 Design Abstraction Levels SYSTEM + MODULE GATE CIRCUIT S n+ G DEVICE n+ D Source: J. Rabaey, 2004 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27
28 New Trends on Complex VLSI Designs Regular structures with network-connected communication communcaton mechanism chansm Multicore processor chips Network-on-chips Multicore processor chips can cope with the following challenges in nano-scale technology High power Low reliability Low yield Network-on-chips can cope with the following challenge in nano-scale technology Long interconnection delay Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28
29 SPARC V9 (JSSC, Jan. 2006) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29
30 Cell Processor (JSSC, Jan. 2006) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30
31 Example SPARC Server (Sun, JSSC, Jan. 2008) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31
32 Example POWER6 (IBM, JSSC, Jan. 2008) Advanced Reliable Systems (ARES) Lab Jin-Fu Li, EE, NCU 32
33 Network-on-Chip [Source: IEEE Micro, 2007] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33
34 Network-on-Chip [Source: IEEE Micro, 2007] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34
35 Ambric Am2045 Chip Item Technology Specification 0.13um Standard Cell # of Transistors 180 million # of Processors (32-bit) Size of SRAMs Power Energy Efficiency M bits 300MHz 12.6MIPS/mW [Source: IEEE Micro, 2007] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35
36 TRIPS Chip TRIPS: Tera-ops, Reliable, Intelligently-adaptive Processing System [Source: IEEE Micro, 2007] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 36
37 Intel-Teraflops Processor [Source: IEEE Micro, 2007] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37
38 3D-SiP: Next Technology/Architecture Transition? Technology evolution Bipolar CMOS Multicore 3D integration + System-in-package (3D-SiP) System-in-package stacking dies using bonding wires Source: ISQED, Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 38
39 3D-SiP: Next Technology/Architecture Transition? 3D integration Stacking dies using through silicon via (TSV) Source: IBM, Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 39
40 A New Paradigm for Future Technologies A vision of future 3-D hyperintegration of InfoTech, NanoTech, and BioTech systems Source: Proceedings of IEEE, Jan Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 40
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