Low Power Cache Design. Angel Chen Joe Gambino

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Transcription:

Low Power Cache Design Angel Chen Joe Gambino

Agenda Why is low power important? How does cache contribute to the power consumption of a processor? What are some design challenges for low power caches? Existing solutions for low power cache design Researched ultra-low-voltage cache design solution for many-core systems Detailed architectural overview of the design performance comparison with existing solutions

Background The cost/performance ratio of computing systems have seen a steady decline due to advances in: Integrated circuit technology Architectural improvements in CPU design At the same time, more and more emphasis is given to the minimization of environmental footprint of computing systems. In particular, energy efficiency is a key concern in future many-core (1000+ processors) system design.

Background (cont.) Among all processor components, the cache consumes about 40% of the total area and 20% of power. Supply voltage scaling can reduce system energy consumption at the cost of performance and reliability. (Especially with the current trend toward many-core processors and deep nanometer designs)

Existing Solutions Cache designs that intrinsically consume less energy. Employ advanced fault tolerance techniques to maintain reliability under low supply voltage.

Existing Solutions (cont.) Redundant Memory Excessive area and power overheads when cell-failure probability increases Cache Line Disabling This is only effective if the cell-failure probability is low ECC (error correcting codes) E.g. extended hamming codes, multi-bit clustered ECC

Cache Fault Analysis Soft cache fault is generally caused by random noises or particle strikes. It occurs transiently and is recoverable through error-detecting/correcting codes. Hard cache fault is persistent memory cell fault that occurs as a result of chip manufacturing defects or device aging. Error correction codes can also be used to correct this failure but can only correct single-bit errors.

Cache Fault Analysis (cont.)

Cache Fault Analysis (cont.)

Researched Solution Cache Line Disabling + Double Error Correcting Triple Error Detecting Codes (1-bit error correction for hard errors and 1-bit error correction for soft errors)

Researched Solution (cont.)

Cache Line Disabling On ROM software called Built In Self Test checks for errors during initialization of processor Detects Hard Cache faults Disables Cache lines with more than one fault Only works if the number of faulty lines is low Requires no additional hardware overhead

Cache Line Disabling (cont.) SRAM - Modeled as 3 blocks Memory Cell Array, Address Decoder, and Read/Write Circuit All faults can be detected by checking memory cells Two general types of cache errors Single-Cell and Multi-Cell Stuck-At 1/0, Stuck Open, State Transition, Data Retention Cell State Coupling, Multiple Address

Cache Line Disabling (cont.) Any BIST with 100% correctness can be used Most efficient is 9N with an added Data Retention test 9N utilizes Marching For Word-Oriented SRAM, each march element is a word Introduces Multi-Cell errors Writes one march element at a time to each word address, reads it, compares them After marching, data retention test runs This method performs all checks with the best speed/rom space ratio

ECC Overview Error Detection with Parity Codes can detect all odd number faults, cannot correct error Single-Error Correction Codes - product codes (2-D parity check), parity check matrices - such coding scheme is commonly referred to as hamming codes - cannot simultaneously detect double-bit errors

ECC Overview (cont.)

ECC Overview (cont.) Single-Error Correct Double-Error Detect Codes - widely used to protect memory cells - extend SEC by adding an extra bit that represents the parity over the seven bits of the SEC code word

DECTED Double-Error Correcting Triple-Error Detecting Codes

DECTED (cont.)

Simulation Comparison

Simulation Comparison (cont.)

Simulation Comparison (cont.)

Simulation Comparison (cont.)

Simulation Comparison (cont.)

Simulation Comparison (cont.)

References [1] M. Zhang, V. Stojanovic and P. Ampadu, "Reliable ultra-low-voltage cache design for many-core systems," IEEE Trans. Circuits Syst. II: Regular Papers,, vol. 59, no. 12, pp. 858-862, Dec. 2012. [2] A. Aladmeldeen, I. Wagner, Z. Chishti, W. Wu, C. Wilkerson, and S.-L. Lu, Energy-efficient cache design using variable-strength errorcorrecting codes, in Proc. 38th Int. Symp. Comput. Architecture, 2011, pp. 461 472. [3] Mukherjee, Shubu. Architecture Design for Soft Errors. Amsterdam: Morgan Kaufmann/Elsevier, 2008. Print. [4]A.Agarwal,B.C.Paul,H.Mahmoodi,A.Datta,and K.Roy, A processtolerant cache architecture for improved yield in nanoscale technologies, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 1, pp. 27 38, Jan. 2005. [5] M. H. Tehranipour, Z. Navabi, and S. M. Falkhrai, An efficient BIST method for testing of embedded SRAMs, in Proc. IEEE Int. Symp. Circuits and Systems, vol. 5, May 2001, pp. 73 76. [6] Kenyon, Samantha Rose, "Drowsy Cache Partitioning for Multithreaded Systems and High Level Caches" (2014). Thesis. Rochester Institute of Technology. Accessed from RIT Scholar Works Thesis/Dissertation Collections.

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