PL2303SA (SOP8 Package) USB t Serial Bridge Cntrller Prduct Datasheet Dcument Revisin: 1.2.0 Dcument Release: Prlific Technlgy Inc. 7F, N. 48, Sec. 3, Nan Kang Rd. Nan Kang, Taipei 115, Taiwan, R.O.C. Telephne: +886-2-2654-6363 Fax: +886-2-2654-6161 E-mail: sales@prlific.cm.tw Website: http://www.prlific.cm.tw
DS_PL2303SA_d20180327_v1.2.0.dc Disclaimer All the infrmatin in this dcument is subject t change withut prir ntice. Prlific Technlgy Inc. des nt make any representatins r any warranties (implied r therwise) regarding the accuracy and cmpleteness f this dcument and shall in n event be liable fr any lss f prfit r any ther cmmercial damage, including but nt limited t special, incidental, cnsequential, r ther damages. Trademarks The Prlific lg is a registered trademark f Prlific Technlgy Inc. All brand names and prduct names used in this dcument are trademarks r registered trademarks f their respective hlders. Cpyrights Cpyright 2011-2018 Prlific Technlgy Inc., All rights reserved. N part f this dcument may be reprduced r transmitted in any frm by any means withut the express written permissin f Prlific Technlgy Inc. PL2303SA Prduct Datasheet - 2 - Dcument ersin 1.2.0
DS_PL2303SA_d20180327_v1.2.0.dc Revisin Histry Revisin Descriptin Date 1.2.0 Remve Distributrs Cntact Infrmatin (refer t Prlific website instead) 1.1.1 Mdify Ordering Infrmatin May 4, 2012 1.1.0 Added Reference Schematic Remve USB Descriptrs Infrmatin Added Chip Marking Infrmatin March 30, 2012 1.0.0 Frmal Release PL2303SA Prduct Datasheet Octber 3, 2011 PL2303SA Prduct Datasheet - 3 - Dcument ersin 1.2.0
DS_PL2303SA_d20180327_v1.2.0.dc Table f Cntents 1.0 FEATURES... 6 2.0 FUNCTIONAL BLOCK DIAGRAM... 7 3.0 INTRODUCTION... 8 4.0 PIN ASSIGNMENT DIAGRAM... 9 5.0 PIN ASSIGNMENT DESCRIPTION... 9 6.0 DATA FORMATS & PROGRAMMABLE BAUD RATE GENERATOR... 10 7.0 APPLICATION REFERENCE CIRCUIT DIAGRAM... 11 8.0 DC & TEMPERATURE CHARACTERISTICS... 12 8.1 Abslute Maximum Ratings... 12 8.2 DC Characteristics... 12 8.3 Temperature Characteristics... 13 8.4 Leakage Current and Capacitance... 14 9.0 SOP8 OUTLINE DIAGRAM... 15 10.0 ORDERING INFORMATION... 16 PL2303SA Prduct Datasheet - 4 - Dcument ersin 1.2.0
DS_PL2303SA_d20180327_v1.2.0.dc List f Figures Figure 2-1 Blck Diagram f PL2303SA... 7 Figure 4-1 Pin Assignment Diagram f PL2303SA SOP8 Package... 9 Figure 7-1 PL2303SA Reference Schematic Diagram... 11 Figure 9-1 SOP8 Package Outline Diagram... 15 Figure 10-1 Chip Part Number Infrmatin... 16 List f Tables Table 5-1 Pin Assignment Descriptin (SOP8 Package)... 9 Table 6-1 Supprted Data Frmats... 10 Table 6-2 Driver Supprted Baud Rates... 10 Table 8-1 Abslute Maximum Ratings... 12 Table 8-2a Operating ltage and Suspend Current... 12 Table 8-2b 3.3 I/O Pins... 12 Table 8-2c DD_325@3.3 Serial I/O Pins... 13 Table 8-2d DD_325@2.5 Serial I/O Pins... 13 Table 8-2e DD_325@1.8 Serial I/O Pins... 13 Table 8-3 Temperature Characteristics... 13 Table 8-4 Leakage Current and Capacitance... 14 Table 10-1 Ordering Infrmatin... 16 Table 10-2 Chip Marking Infrmatin... 16 PL2303SA Prduct Datasheet - 5 - Dcument ersin 1.2.0
DS_PL2303SA_d20180327_v1.2.0.dc 1.0 Features Fully Cmpliant with USB Specificatin v2.0 (Full-Speed) UHCI/OHCI (USB1.1), EHCI (USB 2.0), xhci (USB 3.0) Hst Cntrller Cmpatible On Chip USB 1.1 transceiver, 5 3.3 regulatr On-chip 96MHz clck generatr Full-duplex transmitter and receiver (TXD and RXD) 5, 6, 7, r 8 data bits Odd, Even, Mark, Space, r Nne parity mde 1, 1.5, r 2 stp bits Parity errr, frame errr, and serial break detectin Prgrammable baud rate frm 75 bps t 115 kbps Independent pwer surce fr serial interface Wrks with existing PC COM Prt sftware applicatins (TXD and RXD) Cnfigurable 512-byte bi-directinal data buffer 256-byte utbund buffer and 256-byte inbund buffer; r 128-byte utbund buffer and 384-byte inbund buffer Prvides ryalty-free irtual COM Prt (CP) driver supprt fr: Windws 2000, XP, ista, and 7 (Micrsft Certified WHQL Lg Drivers) Windws Server 2003, 2008, 2008 R2 Windws 8 Windws CE 4.2, 5.0, 6.0, and Windws Embedded Cmpact 7 Windws XP Embedded (XPe), Pint-f-Service (WEPOS), and POSReady Mac OS 8/9, OS X Linux/Andrid kernel 2.4.31 and abve includes built-in PL2303 drivers Small ftprint 8-pin SOP IC package PL2303SA Prduct Datasheet - 6 - Dcument ersin 1.2.0
DS_PL2303SA_d20180327_v1.2.0.dc 2.0 Functinal Blck Diagram USB Hst 96MHz Clck Generatr USB 1.1 Transceiver 5 t 3.3 Regulatr Pwer Management USB Digital Lck Lp USB t Serial Interface Engine Cntrl Endpint Interrupt Endpint Bulk-in Endpint Bulk-Out Endpint 256/384Byte Inbund Data Buffer 256/128Byte Outbund Data Buffer Hardware ROM Default Descriptr RS232 Serial Interface Engine PL-2303SA Full-duplex transmitter and receiver (TXD and RXD) Figure 2-1 Blck Diagram f PL2303SA PL2303SA Prduct Datasheet - 7 - Dcument ersin 1.2.0
DS_PL2303SA_d20180327_v1.2.0.dc 3.0 Intrductin PL2303SA is a cnvenient small-factr slutin fr cnnecting an RS232-like full-duplex asynchrnus serial device (TX-RX nly) t any Universal Serial Bus (USB) capable hst. Prlific prvides highly cmpatible drivers that culd simulate the traditinal COM prt n mst perating systems allwing the existing applicatins based n COM prt (using TX-RX nly) t easily migrate and be made USB ready. By taking advantage f USB bulk transfer mde and large data buffers, PL2303SA is capable f achieving higher thrughput cmpared t traditinal UART (Universal Asynchrnus Receiver Transmitter) prts. The flexible baud rate generatr f PL2303SA als culd be prgrammed t generate any rate between 75 bps t 115 kbps by driver custmizatin. PL2303SA is exclusively designed fr mbile and embedded slutins in mind, prviding a very small ftprint that culd easily fit in t any cnnectrs and handheld devices. With very small pwer cnsumptin in either perating r suspend mde, PL2303SA is perfect fr bus pwered peratin with plenty f pwer left fr the attached devices. Flexible signal level requirement n the RS232-like serial prt side als allws PL2303SA t cnnect directly t any 3.3~1.8 range devices. PL2303SA Prduct Datasheet - 8 - Dcument ersin 1.2.0
DS_PL2303SA_d20180327_v1.2.0.dc 4.0 Pin Assignment Diagram 1 GND O_33 8 2 TXD DD_5 7 3 DD_325 DM 6 4 RXD PL-2303SA DP 5 Figure 4-1 Pin Assignment Diagram f PL2303SA SOP8 Package 5.0 Pin Assignment Descriptin Pin Type Abbreviatin: I: Input O: Output B: Bidirectinal I/O P: Pwer/Grund Table 5-1 Pin Assignment Descriptin (SOP8 Package) Pin # Name Type Descriptin 1 GND P Grund 2 TXD O (1) Serial Prt (Transmitted Data) 3 DD_325 P RS232 DD. The pwer pin fr the serial prt signals. When the serial prt is 3.3, this shuld be 3.3. When the serial prt is 2.5, this shuld be 2.5. The range can be frm 1.8~3.3. 4 RXD I (2) Serial Prt (Received Data) 5 DP B USB Prt D+ signal 6 DM B USB Prt D- signal 7 DD_5 P USB Prt BUS, 5 Pwer 8 O_33 P Regulatr Pwer Output, 3.3 Ntes: (1) Tri-State, Output Pad. Level and Driving Capability decided by DD_325. (2) Tri-State, CMOS Input/Output Pad with level shifter. Level and Driving Capability decided by DD_325. PL2303SA Prduct Datasheet - 9 - Dcument ersin 1.2.0
DS_PL2303SA_d20180327_v1.2.0.dc 6.0 Data Frmats & Prgrammable Baud Rate Generatr The PL2303SA cntrller supprts versatile data frmats and has a prgrammable baud rate generatr. The supprted data frmats are shwn n Table 6-1. The prgrammable baud rate generatr supprts baud rates frm 75 bps up t 115 kbps as shwn in Table 6-2. Table 6-1 Supprted Data Frmats Stp bits 1 1.5 2 Parity type Nne Odd Even Mark Space Data bits 5, 6, 7, 8 Descriptin Table 6-2 Driver Supprted Baud Rates Baud Rates (bps) Baud Rates (bps) Baud Rates (bps) Baud Rates (bps) 75 1200 7200 38400 110 1800 9600 56000 150 2400 14400 57600 300 3600 19200 115200 600 4800 28800 NOTE: Additinal baud rate supprt within the chip specificatin range can be added by driver custmizatin request. Cntact Prlific fr mre infrmatin. PL2303SA Prduct Datasheet - 10 - Dcument ersin 1.2.0
DS_PL2303SA_d20180327_v1.2.0.dc 7.0 Applicatin Reference Circuit Diagram Fllwing is an example f using the PL2303SA as a simple USB t TXD/RXD serial cnverter. Nte that Pin 3 (RS232 DD) is the pwer pin fr the serial prt signals. If Pin 3 is 3.3, the serial prt is 3.3. If Pin 3 is 2.5, the serial prt is 2.5. The range can be frm 1.8~3.3. Cntact Prlific FAE fr mre PCB design supprt. Figure 7-1 PL2303SA Reference Schematic Diagram PL2303SA Prduct Datasheet - 11 - Dcument ersin 1.2.0
DS_PL2303SA_d20180327_v1.2.0.dc 8.0 DC & Temperature Characteristics 8.1 Abslute Maximum Ratings Table 8-1 Abslute Maximum Ratings Items Pwer Supply ltage - DD_5 Input ltage f 3.3 I/O Input ltage f 3.3 I/O with 5 Tlerance I/O Output ltage f 3.3 I/O Strage Temperature Ratings -0.3 t 6.5-0.3 t O_33+0.3-0.3 t DD_5+0.3-0.3 t DD_5 +0.3-40 t 150 C 8.2 DC Characteristics 8.2.1 Operating ltage and Suspend Current Table 8-2a Operating ltage and Suspend Current Parameter Symbl Min Typ Max Unit Operating ltage Range DD_5 4.5 5 6.5 Output ltage f Regulatr O_33 2.97 3.3 3.63 Operating Current (1) (Pwer Cnsumptin) I DD - 20 25 ma Suspend Current I SUS - 260 450 A (1) N device cnnected. 8.2.2 3.3 I/O Pins Table 8-2b 3.3 I/O Pins Parameter Symbl Min Typ Max Unit Output Driving Capability I DD 4 ma Pwer Supply fr 3.3 I/O Pins O_33 2.97 3.3 3.63 Input ltage (CMOS) Lw Input ltage (LTTL) Lw Output ltage, 3.3 Lw IL IH IL IH OL OH 0.7* O_33 0.3* O_33 0.8 2.0 0.4 2.4 PL2303SA Prduct Datasheet - 12 - Dcument ersin 1.2.0
DS_PL2303SA_d20180327_v1.2.0.dc 8.2.3 Serial I/O Pins Table 8-2c DD_325@3.3 Serial I/O Pins Parameter Symbl Min Typ Max Unit Output Driving Capability I DD 8 ma Pwer Supply fr Serial I/O Pins DD_325 2.97 3.3 3.63 Input ltage Lw Output ltage Lw IL IH OL OH 0.7* DD_325 0.25* DD_325 0.4 2.4 Table 8-2d DD_325@2.5 Serial I/O Pins Parameter Symbl Min Typ Max Unit Output Driving Capability I DD 5.2 ma Pwer Supply fr Serial I/O Pins DD_325 2.25 2.5 2.75 Input ltage Lw Output ltage Lw IL IH OL OH 0.7* DD_325 0.25* DD_325 0.4 1.85 Table 8-2e DD_325@1.8 Serial I/O Pins Parameter Symbl Min Typ Max Unit Output Driving Capability I DD 4.4 ma Pwer Supply fr Serial I/O Pins DD_325 1.65 1.8 1.95 Input ltage Lw Output ltage Lw IL IH OL OH 0.7* DD_325 0.25* DD_325 0.4 1.25 8.3 Temperature Characteristics Table 8-3 Temperature Characteristics Parameter Symbl Min Typ Max Unit Operating Temperature 0 70 Junctin Operatin Temperature T J -40 25 80 C C PL2303SA Prduct Datasheet - 13 - Dcument ersin 1.2.0
DS_PL2303SA_d20180327_v1.2.0.dc 8.4 Leakage Current and Capacitance Table 8-4 Leakage Current and Capacitance Parameter Symbl Min Typ Max Unit Input Leakage Current (1) I L -10 1 10 A Tri-state Leakage Current I z -10 1 10 A Input Capacitance C IN 2.8 pf Output Capacitance C OUT 2.7 4.9 pf Bi-directinal Buffer Capacitance C BID 2.7 4.9 pf (1) N pull-up r pull-dwn resistr. PL2303SA Prduct Datasheet - 14 - Dcument ersin 1.2.0
DS_PL2303SA_d20180327_v1.2.0.dc 9.0 SOP8 Outline Diagram Figure 9-1 SOP8 Package Outline Diagram PL2303SA Prduct Datasheet - 15 - Dcument ersin 1.2.0
DS_PL2303SA_d20180327_v1.2.0.dc 10.0 Ordering Infrmatin Table 10-1 Ordering Infrmatin Part Number PL-2303SA LF Package Type 8-pin SOP Lead Free Figure 10-1 Chip Part Number Infrmatin Table 10-2 Chip Marking Infrmatin Line Marking Descriptin First Line PL2303SA Chip Prduct Name Secnd Line (GYYWWXXX) G YY WW XXX Green cmpund packing material (Pb-free) Last tw digits f the manufacturing year Week number f the manufacturing year Chip ersin (2D) Third Line TXXXXXXXX Manufacturing LOT cde Example: G11462D means Green packing + Year 2011 + Week n. 46 + 2D chip versin. PL2303SA Prduct Datasheet - 16 - Dcument ersin 1.2.0