3/3/5 CS 6C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU path & Control Part 2 ructors: Krste Asanovic & Vladimir Stojanovic hip://inst.eecs.berkeley.edu/~cs6c/ Review: Processor Design 5 steps Step : Analyze instrucron set to determine datapath Meaning of each instrucron is given by register transfers path must include storage element for ISA registers path must support each register transfer Step 2: Select set of datapath components & establish clock methodology Step 3: Assemble datapath components that meet the Step : Analyze implementaron of each instrucron to determine sewng of control points that realizes the register transfer Step 5: Assemble the control logic Processor Design: 5 steps Step : Analyze instrucron set to determine datapath Meaning of each instrucron is given by register transfers path must include storage element for ISA registers path must support each register transfer Step 2: Select set of datapath components & establish clock methodology Step 3: Assemble datapath components that meet the Step : Analyze implementaron of each instrucron to determine sewng of control points that realizes the register transfer Step 5: Assemble the control logic Rs,,, Op, Func ctr Register- Register Timing: One Complete Cycle (Add/Sub) rucron Access Time Delay through Control Logic RegWr Register File Access Time, B Delay RegWr Rs ctr Register Write Occurs Here Rs,,, Op, Func ctr Register- Register Timing: One Complete Cycle rucron Access Time Delay through Control Logic RegWr Register File Access Time, B Delay RegWr Rs ctr Register Write Occurs Here 3c: Logical Op (or) with Immediate R[rt] R[rs] ZeroEt[imm6] 3 26 2 6 3 6 bits 5 bits 5 bits 6 5 6 bits immediate 6 bits 6 bits Wri/ng to register (not )!! ctr What about Read? imm6 6 ZeroEt Src
3/3/5 3d: Load OperaRons R[rt] Mem[R[rs] + SignEt[imm6]] Eample: lw rt,rs,imm6 3 26 2 6 6 bits 5 bits 5 bits 6 bits imm6 6 ZeroEt Src ctr 3d: Load OperaRons R[rt] Mem[R[rs] + SignEt[imm6]] Eample: lw rt,rs,imm6 3 26 2 6 6 bits 5 bits 5 bits 6 bits ctr imm6 6 EtOp Etender Src 3e: Store OperaRons Mem[ R[rs] + SignEt[imm6] ] R[rt] E.: sw rt, rs, imm6 3 26 2 6 6 bits 5 bits 5 bits 6 bits ctr imm6 6 EtOp Etender Src In 3e: Store OperaRons Mem[ R[rs] + SignEt[imm6] ] R[rt] E.: sw rt, rs, imm6 3 26 2 6 6 bits 5 bits 5 bits 6 bits ctr imm6 6 EtOp Etender Src In 3f: The Branch rucron 3 26 2 6 6 bits 5 bits 5 bits 6 bits beq rs, rt, imm6! mem[] Fetch the instrucron from memory (R[rs] R[rt]) Calculate branch condiron if () Calculate the net instrucron s address + + ( SignEt(imm6) ) else + path for Branch OperaRons beq rs, rt, imm6 3 26 2 6 6 bits 5 bits 5 bits 6 bits path generates condiron () Et imm6 Address n_sel Already have mu, adder, need special sign etender for, need equal compare (sub?) ctr 2
3/3/5 ruc3on Fetch Unit including Branch 3 26 2 6 if (Zero ) then + + SignEt[imm6]* ; else + n_sel imm6 Et MUX n_sel ctrl rucron<3:> How to encode n_sel? Direct MUX select? Branch inst. / not branch inst. Let s pick 2nd Ron n_sel zero? MUX Q: What logic gate? PuWng it All Together:A Single Cycle path Et imm6 <2:25> <6:2> imm6 6 <:5> Rs n_sel Etender EtOp <:5> Imm6 ruction<3:> Src ctr In Clickers/Peer rucron What new (pseudo)instrucron would need no new datapath hardware? A: branch if regimmediate B: add two registers and branch if result zero C: store with auto- increment of base address: sw rt, rs, offset // rs incremented by offset ater store D: shit let logical by one bit Et imm6 n_sel RegWr <2:25> Rs imm6 <6:2> Rs 5 5 6 5 <:5> Etender EtOp <:5> Imm6 ruction<3:> Src ctr In Administrivia 6 path Control Signals EtOp: zero, sign src: regb; immed ctr: ADD, SUB, OR Et imm6 Address n_sel & imm6 6 EtOp : write memory : ; Mem : rt ; rd RegWr: write register Etender Src ctr In Given path: RTL à Control rucron<3:> <26:3> <:5> Op Fun <2:25> <6:2> <:5> <:5> Imm6 n_sel RegWr EtOp Src ctr Rs Control DATA PATH 3
3/3/5 RTL: The Add rucron 3 26 2 6 6 rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add rd, rs, rt MEM[] Fetch the instrucron from memory R[rd] R[rs] + R[rt] The actual eraron + Calculate the net instrucron s address rucron Fetch Unit at the Beginning of Add! Fetch the instrucron from rucron memory: rucron MEM[] same for all instrucrons Et n_sel Address rucron<3:> imm6 Single Cycle path during Add! 3 26 2 6 6 rs rt rd shamt funct R[rd] R[rs] + R[rt] RegWr Rs n_sel+ imm6 6 EtOp Etender instr fetch unit Rs Imm6 zero ctradd Src rucron<3:> <2:25> In <6:2> <:5> <:5> rucron Fetch Unit at End of Add + Same for all instrucrons ecept: Branch and Et imm6 n_sel+ Address 3 Single Cycle path during New { [3..28],, } n_sel RegWr Rs ctr - bit Registers imm6 6 EtOp Etender Src rucoon Fetch Unit In Rs Imm6 TA26 Zero rucron<3:> <2:25> <6:2> <:5> <:5> <:25> Single Cycle path during 3 rucron<3:> n_sel? rucoon Fetch Unit RegWr Rs ctr Rs Imm6 TA26 Zero - bit Registers imm6 6 Etender EtOp New { [3..28],, } Src In <2:25> <6:2> <:5> <:5> <:25>
3/3/5 ruc3on Fetch Unit at the End of 3 New { [3..28],, } n_sel Zero imm6 n_mux_sel rucron<3:> How do we modify this to account for s? ruc3on Fetch Unit at the End of 3 New { [3..28],, } n_sel Zero imm6 n_mux_sel TA 26 (MSBs) rucron<3:> Query Can Zero srll get asserted? Does n_sel need to be? If not, what? In The News: Tile- M 6- bit ARM cores on one chip P&H Figure.7 EZChip (bought Tilera) 6-bit ARM Corte A53 Dual-issue, in-order 27 Summary of the Control Signals (/2) inst!register Transfer! add!r[rd] R[rs] + R[rt]; +!!srcregb, ctr ADD, rd, RegWr, n_sel +!! sub!r[rd] R[rs] R[rt]; +!!srcregb, ctr SUB, rd, RegWr, n_sel +! ori!r[rt] R[rs] + zero_et(imm6); +!!srcim, Et Z, ctr OR, rt,regwr, n_sel +! lw!r[rt] MEM[ R[rs] + sign_et(imm6)]; +!!srcim, Et sn, ctr ADD,, rt, RegWr,!n_sel +! sw!mem[ R[rs] + sign_et(imm6)] R[rs]; +!!srcim, Et sn, ctr ADD,, n_sel +! beq!if (R[rs] R[rt]) then + sign_et(imm6)]!else +!!n_sel br, ctr SUB! Summary of the Control Signals (2/2) See func We Don t Care :- ) Appendi A add sub ori lw sw beq Src RegWrite ite nsel EtOp ctr<2:> Add Subtract Or Add Add Subtract 3 26 2 6 6 R- type rs rt rd shamt funct add, sub I- type? ori, lw, sw, beq 5
3/3/5 Boolean Epressions for Controller Controller ImplementaRon add + sub Src ori + lw + sw lw RegWrite add + sub + ori + lw ite sw nsel beq EtOp lw + sw ctr[] sub + beq (assume ctr is ADD, SUB, OR) ctr[] or! Where:! rtype ~ 5 ~ ~ 3 ~ 2 ~ ~, ori ~ 5 ~ 3 2 ~ lw 5 ~ ~ 3 ~ 2 sw 5 ~ 3 ~ 2 beq ~ 5 ~ ~ 3 2 ~ ~ ~ 5 ~ ~ 3 ~ 2 ~! How do we implement this in gates? code func AND logic add sub ori lw sw beq OR logic Src RegWrite ite nsel EtOp ctr[] ctr[] add rtype func 5 ~func ~func 3 ~func 2 ~func ~func sub rtype func 5 ~func ~func 3 ~func 2 func ~func! Summary: Single- cycle Processor Five steps to design a processor:. Analyze instrucron set à Processor datapath Control 2. Select set of datapath components & establish path clock methodology 3. Assemble datapath meerng the. Analyze implementaron of each instrucron to determine sewng of control points that effects the register transfer. 5. Assemble the control logic Formulate Logic EquaRons Design Circuits Input Output 6