AIM Photonics: Manufacturing Challenges for Photonic Integrated Circuits November 16, 2017 Michael Liehr
Industry Driving Force EXA FLOP SCALE SYSTEM Blades SiPh Interconnect Network Memory Stack HP HyperX dense WDM multi Tb/s low energy integrated transceivers high radix nanosecond scale photonic switch fabric CMPs high performance embedded computing data centers Copyright AIM Photonics 2015 2
With permission from John E. Bowers Silicon or InP? 300 mm Silicon - ~$0.2 cm -2 100 mm InP - ~$4.0 cm -2 (Photo courtesy of Dr. Jordan Lang, Yale) CMOS processing of photonics is already happening, yet high cost and small size of III-V wafers remains an issue. Goal: Grow III-V active components on larger and cheaper silicon substrates without sacrificing laser performance for lower cost and higher throughput. [1] Bowers, John E., et al. "A Path to 300 mm Hybrid Silicon Photonic Integrated Circuits. OFC 2014
Market Segments Market Forecast High performance computing earliest adapters Medical, consumer and chip-chip drive real volumes http://www.semiconductortoday.com/news_items/2012/sep/yole_270912.html 4
Photonic Circuit Manufacturing With permission from John E. Bowers Silicon photonics PIC using silicon foundries Package assembly using silicon Assembly and Test Infrastructure Low cost optical connector attach
Key Technology Manufacturing Areas Projects Datacom High Capacity Photonic Interconnected Systems: Scalable Datacenter Switching & Interposer Solutions Analog/RF Applications High Dynamic Range RF Photonics for Wideband Systems Integrated Photonic Analog Link and Processing on InP P-Contact N-Contact Photonic Integrated Circuit (PIC) Sensors Universal Transducer Components and Microfluidic Systems for Sensing Photonic Integrated Circuit (PIC) Array Technologies Free-Space Communications with PIC Array 7
Datacom Two significant challenges for the Datacenter and more broadly for Datacom System high-capacity communications high efficiency switching Cisco VNI Forecasts 194 EB per Month of IP Traffic by 2020 Optical Transmission market trend for Data Centers 8
DataCom Transceiver Roadmap - preliminary 2.56Tbs Strategic differentiation potentials 2020 ~0.5 $/Gbs* 400Gbs 100Gbs Long Term competitiveness Short Term performance proof 2019 < 2 $/Gbs* 2018 > 5 $/Gbs* Market Price Estimates ($/Gbs) Architecture 8x 320Gbs 8 wavelength 64 Lasers / 8 CMOS Architecture 4x 100Gbs 4 Lasers / 4 CMOS Customer Margin Licenses Capsulation CMOS Packaging Wafer/2.5D/3D Lasers * estimates 2020/21 <<0.5 $/Gbs*
Manufacturing Centers Electronic Photonic Design Automation (EPDA) Reference Design and System Co-sim Modeling EPDA Standards Development DFM Methods, PDK Extensions and Tools for Photonic Systems Multi-Project Wafer and Assembly (MPWA) Si Photonics MPWA: SUNY Poly 300 mm Si Photonics process moving to 3D integration Optical/Electrical WAC Testing & Automated probe development 2.5D Integration of Lasers/PICs on passive and active interposers InP MPW & EPDA Heteroepitaxy growth of Q-dot lasers on 300mm Si wafers 10
EPDA Effort
Silicon Photonics Multi Project Wafer (MPW) MPW Fab Runs SUNY Poly 300mm fab line 3 MPW offerings Full-Active- 3 runs in 2018 and 2019 Passive- 3 runs in 2018 and 2019 Interposer- 1 run in 2018 and 2019 MOSIS is the MPW Aggregator DRC clean designs (with Mentor Calibre) are submitted to MOSIS MOSIS also distributes the PDK MPW Pricing (minimum 20 unpackaged die) FULL (Active) 51mm 2 chips $100K AIM members $120K non-members 7.7mm 2 chips $25K AIM members $30K non-members PASSIVE 51mm2 chips $30K AIM members $36K non-members INTERPOSER 156mm2 $93.6K AIM members $112.3K non-members 13
With permission from John E. Bowers III-V Laser Growth on Silicon Polarity, lattice & thermal expansion mismatch between silicon and III-Vs result in high dislocation densities High thresholds (or no lasing), and poor reliability for QW lasers Approach: Quantum dots Dangling bond/ threading dislocation Bulk GaAs: a=0.565 nm GaAs Bulk Si: a=0.543 nm Si substrate Silicon substrate SCH QDs SCH
Epitaxial QD Approach First electrically pumped CW laser monolithically grown on foundry compatible (001) silicon, without Ge Thresholds down to 0.6 ma Output power up to 110 mw CW lasing up to 90 o C, T 0 100K from 20-40 o C Low cost monolithic light source for high volume silicon photonics 20 db reduced reflection sensitivity compared QWs Demonstrates potential for isolator-free integration 15
Manufacturing Center of Excellence Projects Test, Assembly and Optical Packaging (TAP) Chip Scale Packaging Rochester Packaging Facility Development Functional Testing Development for Automated Scaled Manufacturing High Density Fiber Connectivity OPCB & Polymer WG Connectivity AIM Photonics Manufacturing at ON Semiconductor in Rochester, NY 16
AIM Summer Academy 2017
Thank You