ECE 451 Introduction to Microprocessors Chapter 1 Dr. Bradley J. Bazuin Associate Professor Department of Electrical and Computer Engineering College of Engineering and Applied Sciences
Chapter 1 Serial Peripheral Interface (SPI) Extended serial string transmission ECE 451 2
What is Serial Peripheral Interface (SPI)? SPI is a synchronous serial protocol proposed by Motorola to be used as standard for interfacing peripheral chips to a microcontroller. Devices are classified into the master or slaves. The SPI protocol uses four wires to carry out the task of data communication: MOSI: master out slave in MISO: master in slave out SCK: serial clock SS: slave select An SPI data transfer is initiated by the master device. A master is responsible for generating the SCK signal to synchronize the data transfer. The SPI protocol is mainly used to interface with shift registers, LED/LCD drivers, phase locked loop chips, memory components with SPI interface, or A/D or D/A converter chips. ECE 451 3
Memory Addresses ECE 451 4
The HCS12 SPI Modules The MC9S12DP512 has three SPI modules: SPI, SPI1, and SPI2. By default, the SPI share the use of the upper 4 Port S pins: PS7 SS (can be rerouted to PM3) PS6 SCK (can be rerouted to PM5) PS5 MOSI (can be rerouted to PM4) PS4 MISO (can be rerouted to PM2) By default, the SPI1 shares the use of the lower 4 Port P pins: PP3 SS1 (can be rerouted to PH3) PP2 SCK1 (can be rerouted to PH2) PP1 MOSI1 (can be rerouted to PH1) PP MISO1 (can be rerouted to PH) By default, the SPI2 shares the use of the upper 4 Port P pins: PP6 SS2 (can be rerouted to PH7) PP7 SCK2 (can be rerouted to PH6) PP5 MOSI2 (can be rerouted to PH5) PP4 MISO2 (can be rerouted to PH4) It is important to make sure that there is no conflict in the use of signal pins when making rerouting decision. ECE 451 5
Adapt9S12DP512 I/O Pins ECE 451 6
SPI Related Registers (1 of 6) The operating parameters of each SPI module are controlled via two control registers: SPIxCR1: (x =, 1, or 2) SPIxCR2 The baud rate of SPI transfer is controlled by the SPIxBR register. The operation status of the SPI operation is recorded in the SPIxSR register. The contents of the SPIxCR1, SPIxCR2, SPIxBR, and SPIxSR registers are illustrated in Figure 1.1 to 1.4, respectively. The SS pin may be disconnected from SPI by clearing the SSOE bit in the SPIxCR1 register. After that, it can be used as a general I/O pin. If the SSOE bit in the SPIxCR1 register is set to 1, then the SS signal will be asserted to enable the slave device whenever a new SPI transfer is started. The equation for setting the SPI baud rate is given in Figure 1.3. ECE 451 7
SPI Related Registers (2 of 6) 7 6 5 4 3 2 1 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE reset: 1 SPIE: SPI interrupt enable bit = SPI interrupts are disabled 1 = SPI interrupts are enabled SPE: SPI system enable bit = SPI disabled 1 = SPI enabled and pins PS4-PS7 are dedicated to SPI function SPTIE: SPI transmit interrupt enable = SPTEF interrupt disabled 1 = SPTEF interrupt enabled MSTR: SPI master/slave mode select bit = slave mode 1 = master mode CPOL: SPI clock polarity bit = active high clocks selected; SCK idle low 1 = active low clocks selected, SCK idle high CPHA: SPI clock phase bit = The first SCK edge is issued one-half cycle into the 8-cycle transfer operation. 1 = The SCK edge is issued at the beginning of the 8-cycle transfer operation. SSOE: slave select output enable bit The SS output feature is enabled only in master mode by asserting the SSOE bit and the MODFEN bit of the SPIxCR2 register. LSBF: SPI least-significant-bit first enable bit = data is transferred most-significant bit first 1 = data is transferred least-significant bit first ECE 451 Figure 1.1 SPI control register 1 (SPIxCR1, x =, 1, or 2) 8
SPI Related Registers (3 of 6) 7 6 5 4 3 2 1 MODFEN BIDIROE SPSWAI SPC reset: 1 MODFEN: Mode fault enable bit = Disable the MODF error 1 = Enable settinig the MODF error BIDIROE: Output enable in the bidirectional mode of operation = Output buffer disabled 1 = Output buffer enabled SPSWAI: SPI stop in wait mode = SPI clock operates normally in stop mode 1 = Stop SPI clock generation in Wait mode SPC: Serial pin control bit With the MSTR bit in the SPIxCR1 register, this bit enables bidirectional pin configuration as shown in Table 1.1. Figure 1.2 SPI control register 2 (SPIxCR2, x =, 1, or 2) ECE 451 9
SPI Related Registers (4 of 6) Table 1.1 SS input/output selection MODFEN SSOE Master Mode Slave mode 1 1 1 1 SS not used by SPI SS not used by SPI SS input with MODF feature SS output SS input SS input SS input SS input ECE 451 1
SPI Related Registers (5 of 6) 7 6 5 4 3 2 1 SPPR2 SPPR1 SPPR SPR2 SPR1 SPR reset: SPPR2~SPPR: SPI baud rate preselection bits SPR2~SPR: SPI baud rate selection bits BaudRateDivisor = (SPPR + 1) 2 (SPR + 1) Baud Rate = Bus Clock BaudRateDivisor Figure 1.3 SPI baud rate register (SPIxBR, x =, 1, or 2) 7 6 5 4 3 2 1 SPIF SPTEF MODF reset: 1 SPIF: SPI interrupt request bit SPIF is set after the eight SCK cycles in a data transfer, and it is cleared by reading the SPSR register (with SPIF set) followed by a read access to the SPI data register. = transfer not yet complete 1 = new data copied to SPIxDR SPTEF: SPI data register empty interrupt flag = SPI data register not empty 1 = SPI data register empty MODF: mode error interrupt status flag = mode fault has not occurred ECE 451 1 = mode fault has occurred 11 Material from or based Figure on: The 1.4 HCS12/9S12: SPI status An register Introduction (SPIxSR) to Software & Hardware
SPI Related Registers (6 of 6) Example 1.1 Give a value to be loaded to the SPIxBR register to set the baud rate to 2 MHz for a 24 MHz bus clock. Solution: 24 MHz 2 MHz = 12. One possibility is to set SPPR2-SPPR and SPR2-SPR to 1 and 1, respectively. The value to be loaded into the SPIxBR register is $21. Example 1.2 What is the highest possible baud rate for the SPI with 24 MHz bus clock? Solution: The highest SPI baud rate occurs when both the SPPR2-SPPR and SPR2-SPR are. In this case the baud rate is 24 MH 2 = 12 MHz. ECE 451 12
SPI Transmission Format (1 of 3) The data bits can be shifted on the rising or the falling edge of the SCK clock. Since the SCK can be idle high or idle low, there are four possible combinations as shown in Figure 1.5 and 1.6. To shift data bits on the rising edge, set CPOL-CPHA to or 11. To shift data bits on the falling edge, set CPOL-CPHA to 1 or 1. Data byte can be shifted in and out most significant bit first or least significant bit first. ECE 451 13
SPI Transmission Format (2 of 3) Transfer SS (O) master only Begin End SS (I) SCK (CPOL = ) SCK (CPOL = 1) Sample I MOSI/MISO Change O MOSI Pin Change O MISO Pin MSB first (LSBF = ) LSB first (LSBF = 1) t L MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB t T t I t L Minimum 1/2 SCK for t T, t I, t L Figure 1.5 SPI Clock format (CPHA = ) ECE 451 14
SPI Transmission Format (3 of 3) Transfer SS (O) master only Begin End SS (I) SCK (CPOL = ) SCK (CPOL = 1) Sample I MOSI/MISO Change O MOSI Pin Change O MISO Pin MSB first (LSBF = ) LSB first (LSBF = 1) t L MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB t T t I t L Minimum 1/2 SCK for t T, t I, t L Figure 1.6 SPI Clock format 1 (CPHA = 1) ECE 451 15
Bidirectional Mode (MOMI or SISO) A mode that uses only one data pin to shift data in and out. This mode is provided to deal with peripheral devices with only one data pin. Either the MOSI pin or the MISO pin can be used as the bidirectional pin. When the SPI is configured to the master mode (MSTR bit = 1), the MOSI pin is used in data transmission and becomes the MOMI pin. When the SPI is configured to the slave mode (MSTR bit = ), the MISO pin is used in data transmission and becomes the SISO pin. The direction of each serial pin depends on the BIDIROE bit of the SPIxCR2 register. The pin configuration for MOSI and MISO are illustrated in Figure 1.7. To read data from the peripheral device, clear the BIDIROE bit to. To output data to the peripheral device, set the BIDIROE bit to 1. The use of the this mode is illustrated in exercise problem 1.8. ECE 451 16
Normal and Bidirectional Mode When SPE = 1 Master mode MSTR = 1 Slave Mode MSTR = Normal Mode SPC = Serial Out SPI Serial In MOSI MISO Serial In SPI Serial Out MOSI MISO SWOM enables open-drain output SWOM enables open-drain output Bi-directional mode SPC = 1 Serial Out SPI Serial In BIDIROE MOMI Serial In SPI Serial Out BIDIROE SISO Figure 1.7 Normal mode and bidirectional mode ECE 451 17
Mode Fault Error If the SSx signal goes low while the SPIx is configured as a master, it indicates a system error where more than one master may be trying to drive the MOSIx and SCKx pins simultaneously. The MODF bit in the SPIxSR register will be set to 1 when mode fault condition occurs. When mode fault occurs, the MSTR bit will be cleared to and the output enable for the MOSIx and SCKx pins will be deasserted. ECE 451 18
SPI Circuit Connection In an SPI system, one device is configured as a master. Other devices are configured as slaves. The circuit connection for a single-slave system is shown in Figure 1.8. A multi-slave system may have two different connection methods as illustrated in Figure 1.9 and 1.1. In Figure 1.9, the master can exchange data with each individual slave without affecting other slaves. In Figure 1.1, all the slaves are configured into a larger ring. A data transmission with certain slaves will go through other slaves. ECE 451 19
Single IC Interconnection Master SPI Shift register MISO MISO Slave SPI MOSI SCK MOSI SCK Shift register Baud Rate Generator SS V DD SS Figure 1.8 Master/slave transfer block diagram ECE 451 2
SS Multiple IC Interconnection +5V Slave Slave 1 Slave k SPI Master (HCS12) SS Shift register MOSI SCK MISO SS Shift register MOSI SCK MISO SS... Shift register MOSI SCK MISO SS SCKx MOSIx MISOx PP PP1...... PPk Figure 1.9 Single-master and multiple-slave device connection (method 1) ECE 451 21
Daisy Chained Multiple IC Interconnection Slave Slave 1 Slave k SPI Master (HCS12) +5V Shift register MOSI SCK MISO SS Shift register MOSI SCK MISO SS... Shift register MOSI SCK MISO SS SS SCKx... MOSIx MISOx Figure 1.1 Single-master and multiple-slave device connection (method 2) ECE 451 22
Example 1.3 Example 1.3 Configure the SPI to operate with the following setting assuming that Eclock is 24 MHz: 6 MHz baud rate Enable SPI to master mode SCK pin idle low with data shifted on the rising edge of SCK Transfer data most significant bit first and disable interrupt Disable SS function Stop SPI in Wait mode Normal SPI operation (not bidirectional mode) ECE 451 23
Example 1.3 Solution: f E / baud rate = 24 MHz/6 MHz = 4. We need to set SPPR2-SPPR and SPR2-SPR to 1 and, respectively. Write the value $1 into the SPIBR register. The following instruction sequence will configure the SPI as desired: movb #$1, SPIBR ; set baud rate to 6 MHz movb #$5, SPICR1 ; disable interrupt, enable SPI, SCK idle low, data ; latched on rising edge, data transferred msb first movb #$2, SPICR2 ; disable bidirectional mode, stop SPI in wait mode movb #, WOMS ; enable Port S pull-up ECE 451 24
SPI Desirable Utility Functions The following operations are common in many applications and should be made into library functions to be called by many SPI applications: Send a character to SPI putcspix (x =, 1, or 2) Send a string to SPI putsspix (x =, 1, or 2) Read a character from SPI getcspix (x =, 1, or 2) Read a string from SPI getsspix (x =, 1, or 2) ECE 451 25
Function putcspi putcspi: brclr SPISR,SPTEF, putcspi ; wait until write operation is permissible staa SPIDR ; output the character to SPI pcsp_lp: brclr SPISR,SPIF, pcsp_lp ; wait until the byte is shifted out ldaa SPIDR ; clear the SPIF flag rts void putcspi (char cx) { char temp; while(!(spisr & SPTEF)); /* wait until write is permissible */ SPIDR = cx; /* output the byte to the SPI */ while(!(spisr & SPIF)); /* wait until write operation is complete */ temp = SPIDR; /* clear the SPIF flag */ } ECE 451 26
Function putsspi ; the string to be output is pointed to by X putsspi: ldaa 1,x+ ; get one byte to be output to SPI port beq doneps ; reach the end of the string? jsr putcspi ; call subroutine to output the byte bra putsspi ; continue to output doneps: rts void putsspi(char *ptr) { while(*ptr) { /* continue until all characters have been output */ putcspi(*ptr); ptr++; } } ECE 451 27
Function getcspi ; This function reads a character from SPI and returns it in accumulator A getcspi: brclr SPISR,SPTEF, getcspi ; wait until write operation is permissible staa SPIDR ; trigger eight clock pulses for SPI transfer gcsp_lp: brclr SPISR,SPIF, gcsp_lp ; wait until a byte has been shifted in ldaa SPIDR ; return the byte in A and clear the SPIF flag rts char getcspi(void) { while(!(spisr & SPTEF)); /* wait until write is permissible */ SPIDR = x; /* trigger 8 SCK pulses to shift in data */ while(!(spisr & SPIF)); /* wait until a byte has been shifted in */ return SPIDR; /* return the character */ } ECE 451 28
Function getsspi ; This function reads a string from the SPI and store it in a buffer pointed to by X ; The number of bytes to be read in passed in accumulator B getsspi: tstb ; check the byte count beq donegs ; return when byte count is zero jsr getcspi ; call subroutine to read a byte staa 1,x+ ; save the returned byte in the buffer decb ; decrement the byte count bra getsspi donegs: clr,x ; terminate the string with a NULL character rts void getsspi(char *ptr, char count) { while(count) { /* continue while byte count is nonzero */ *ptr++ = getcspi(); /* get a byte and save it in buffer */ count--; } *ptr = ; /* terminate the string with a NULL */ } ECE 451 29
SPI ICs: The HC595 Shift Register The HC595 consists of an 8-bit shift register and a D-type latch with three-state parallel output. The shift register provides parallel data to the latch. The maximum data shift rate is 1 MHz (Philips part). DS 14 SC 11 Shift register Latch 15 1 2 3 4 5 6 7 Q A Q B Q C Q D Q E Q F Q G Q H Reset LC OE 1 12 13 VCC = Pin 16 GND = Pin 8 ECE 451 Figure 1.11 The 74HC595 block diagram and pin assignment 3 9 SQ H
Signal Pins of the HC595 DS: serial data input SC: shift clock. A low-to-high transition on this pin causes the data at the serial input pin to be shifted into the 8-bit shift register. Reset: A low on this pin resets the shift register portion of this device. LC: latch clock. A low-to-high transition on this pin loads the contents of the shift register into the output latch. OE: output enable. A low on this pin allows the data from the latches to be presented at the outputs. QA to QH: tri-state latch output SQH: the output of the eight stage of the shift register ECE 451 31
Applications of the HC595 (1 of 2) The HC595 is often used to add parallel ports to the microcontroller. Both the connection methods shown in Figure 1.9 and 1.1 can be used to add parallel ports to the MCU. ECE 451 32
Example 1.5 Example 1.5 Describe how to use two 74HC595s to drive eight common cathode seven-segment displays assuming that the E clock frequency of the HCS12 is 24 MHz. Solution: Use the circuit in figure 1.12 to connect two 74HC595s to the HCS12. MOSI OE 5V reset 74HC595 Q G Q F... Q A DS SC LC SQ H 5V reset DS Q H 3 3 R... a b g 2N2222 #7 #6 # a a b b......... SCK SC R Q 2N2222. G. PK7 LC... OE. R Q 2N2222 A HCS12 ECE 451 74HC595 33 Figure 1.12 Two Interfacing, 74HC595s Thomson together Delmar drive Learning, eight 26. seven-segment displays... common cathode g common cathode g common cathode I MAX = 7 ma
ASM Program to display 87654321 on display #7 to # (1 of 2) #include c:\miniide\hcs12.inc".org $1 disptab:.byte $8,$7F,$4,$7,$2,$5F,$1,$5B.byte $8,$33,$4,$79,$2,$6D,$1,$3 icnt:.blkb 1 ; loop count.text _main:: lds #$3C ; set up stack pointer bset DDRK,$8 ; configure the PK7 pin for output jsr openspi ; configure SPI forever: ldx #disptab ; use X as a pointer to the table movb #8,icnt ; set loop count to 8 loop: ldaa 1,x+ ; send the digit select byte to the 74HC595 jsr putcspi ; " ldaa 1,x+ ; send segment pattern to 74HC595 jsr putcspi ; " bclr PTK,BIT7 ; transfer data from shift register to output bset PTK,BIT7 ; latch ldy #1 ; display the digit for one ms jsr delayby1ms ; " dec icnt ; bne loop ; if not reach digit 1, then next bra forever ; start from the start of the table ECE 451 34
ASM Program to display 87654321 on display #7 to # (2 of 2) openspi: movb #,SPIBR ; set baud rate to 12 MHz movb #$5,SPICR1 ; disable interrupt, enable SPI, SCK idle low, ; latch data on rising edge, transfer data msb first movb #$2,SPICR2 ; disable bidirectional mode, stop SPI in wait mode movb #,WOMS ; enable Port S pull-up rts #include "c:\miniide\delay.asm" #include "c:\miniide\spiutil.asm" ECE 451 35
C Program #include c:\egnu91\include\hcs12.h #include c:\egnu91\include\spiutil.c #include c:\egnu91\include\delay.c void openspi(void); void main (void) { unsigned char disp_tab[8][2] = {{x8,x7f},{x4,x7},{x2,x5f},{x1,x5b}, {x8,x33},{x4,x79},{x2,x6d},{x1,x3}}; char i; openspi(); /* configure the SPI module */ DDRK = BIT7; /* configure pin PK7 as output */ while(1) { for (i = ; i < 8; i++) { putcspi(disp_tab[i][]); /* send out digit select value */ putcspi(disp_tab[i][1]); /* send out segment pattern */ PTK &= ~BIT7; /* transfer values to latches of 74HC595s */ PTK = BIT7; /* " */ delayby1ms(1); /* display a digit for 1 ms */ } } ECE 451 36 }
The TC72 Digital Thermometer 1-bit resolution and SPI interface Pin assignment and block diagram shown in Figure 1.13. Capable of reading temperature from -55oC to 125oC. Can be used in continuous temperature conversion or one-shot conversion mode. Has internal clock generator to control the automatic temperature conversion sequence V DD Internal diode temperature sensor TC72 NC CE SCK GND 1 2 TC72 3 8 7 6 4 5 V DD NC SDI SDO 1-bit sigma Delta A/D converter temperature register Manufacturer ID register Serial Port Interface CE SCK SDO SDI GND Control Register ECE 451 37 Material Figure from or 1.13 based TC72 on: The pin HCS12/9S12: assignment An and Introduction functional to Software block diagram & Hardware
Temperature Data Format Temperature is represented by a 1-bit two s complement word with a resolution of.25oc per least significant bit. The converter is scaled from -128oC to +127oC with oc represented as x. The temperature value is stored in two 8-bit registers. Whenever the most significant bit is 1, the temperature is negative. A sample of temperature reading is shown. Table 1.3 TC72 Temperature output data Binary high byte/low byte 1 1/1 1 11/1 1 11/11 1/1 / 1111 1111/1 1111 1/11 111 111/ 11 11/1 Hex 214 4A8 1AC 18 FF8 F2C E7 C9 Temperature 33.25 o C 74.5 o C 26.75 o C 1.5 o C o C -.5 o C -13.25 o C -24 o C -55 o C ECE 451 38
TC72 s Serial Interface The CE input to the TC72 must be asserted (high) to enable SPI transfer. Data can be shifted on the rising edge or the falling edge depending on the idle polarity of the SCK source. Data transfer to and from the TC72 consists of one address byte followed by one or multiple data (2 to 4) bytes. The TC72 registers and their addresses are shown in Table 1.4. The most significant bit of the address byte determines whether a read (A7 = ) or a write (A7 = 1) operation will occur. A multiple byte read operation will start from high address toward lower addresses. The user can send in the temperature result high byte address and read the temperature result high byte, low byte, and the control registers. Table 1.4 Register for TC72 Register Read address Write address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit Value on POR/BOR Control LSBtemperature MSBtemperature ManufacturerID x x1 x2 x3 Note. 1. OS is One-Shot 2. SHDN is Shutdown x8 N/A N/A N/A T1 T9 T T8 1 ECE 451 39 T7 OS T6 1 T5 T4 1 T3 SHDN T2 x5 x x x54
Procedure for Reading Temperature (1 of 2) Step 1 Pull the CE pin high to enable SPI transfer. Step 2 Send the temperature result high byte read address (x2) to the TC72. Wait until the SPI transfer is complete. Step 3 Read the temperature result high byte. The user needs to write a dummy byte into the SPI data register to trigger eight clock pulses. Step 4 Read the temperature result low byte. Again, the user needs to write a dummy byte into the SPI data register to trigger eight clock pulses. Step 5 Pull CE pin to low so that a new transfer can be started. ECE 451 4
Procedure for Reading Temperature (2 of 2) CE 1 2 3 4 5 6 7 8 9 1 11 12 13 14 15 16 SCK SDI A7 = A 7 A 6 A 5 A 4 A 3 A 2 A 1 A SDO High Z D 7 D 6 D 5 D 4 D 3 D 2 D 1 D high Z Figure 1.15b Single data byte read operation CE SCK Write operation SDI Read operation Address byte = x2 A 7 A SDO D 7 D D 7 D D 7 D Figure 1.15c SPI multiple data byte transfer ECE 451 41
Control Register The control register is used to select the shutdown, continuous, or one-shot conversion operating mode. The temperature conversion mode selection logic is shown in Table 1.5. At power up, the SHDN bit is 1. Thus the TC72 is in the shutdown mode. If the SHDN bit is, the TC72 will perform a temperature conversion approximately every 15 ms. A temperature conversion will be initiated by a write operation into the control register to select the continuous mode or one-shot mode. A typical circuit connection between the TC72 and the HCS12 is shown in Figure 1.16. Table 1.5 Control register temperature conversion mode selection Operationmode Continuoustemperatureconversion Shutdown Continuoustemperatureconversion One-shot One-Shot bit 1 1 Shutdown bit 1 1 ECE 451 42
Example 1.6: Reading Temp. Write a C program to read the temperature every 2 ms. Convert the temperature to a string so that it can be displayed in an appropriate output device. A pointer to hold the string will be passed to this function. The bus clock is 24 MHz. V DD.1 F TC72 VDD CE SCK SDO SDI GND HCS12 MCU PK7 SCK MISO MOSI Figure 1.16 Circuit connection between the TC72 and the HCS12 ECE 451 43
C Code (1 of 4) #include c:\egnu91\include\hcs12.h #include c:\egnu91\include\spiutil.c #include c:\egnu91\include\delay.c #include c:\egnu91\include\convert.c void read_temp (char *ptr); void openspi(void); char buf[1]; void main (void) { DDRM = BIT1; /* configure the PM1 pin for output */ openspi(); /* configure SPI module */ read_temp(&buf[]); } void openspi(void) { SPIBR = x1; /* set baud rate to 6 MHz */ SPICR1 = x5; /* enable SPI to master mode, select rising edge to shift data in and out */ SPICR2 = x2; /* select normal mode and stop SPI in wait mode */ WOMS = x; /* enable Port S pull-up */ ECE 451 } 44
C Code (2 of 4) void read_temp (char *ptr) { char hi_byte, lo_byte, temp, *bptr; unsigned int result; bptr = ptr; PTM = BIT1; /* enable TC72 data transfer */ putcspi(x8); /* send out TC72 control register write address */ putcspi(x11); /* perform one shot conversion */ PTM &= ~BIT1; /* disable TC72 data transfer */ delayby1ms(2); /* wait until temperature conversion is complete */ PTM = BIT1; /* enable TC72 data transfer */ putcspi(x2); /* send MSB temperature read address */ hi_byte = getcspi(); /* read the temperature high byte */ lo_byte = getcspi(); /* save temperature low byte and clear SPIF */ PTM &= ~BIT1; /* disable TC72 data transfer */ lo_byte &= xc; /* make sure the lower 6 bits are s */ result = (int) hi_byte * 256 + (int) lo_byte; if (hi_byte & x8) { /* temperature is negative */ result = ~result + 1; /* take the two' complement of result */ result >>= 6; ECE 451 45
temp = result & x3; /* place the lowest two bits in temp */ result >>= 2; /* get rid of fractional part */ *ptr++ = x2d; /* store the minus sign */ int2alpha(result, ptr); } else { /* temperature is positive */ result >>= 6; temp = result & x3; /* save fractional part */ result >>= 2; /* get rid of fractional part */ int2alpha(result, ptr); /* convert to ASCII string */ } while(*bptr){ /* search the end of the string */ bptr++; }; switch (temp){ /* add fractional digits to the temperature */ case : break; case 1: /* fractional part is.25 */ *bptr++ = x2e; /* add decimal point */ *bptr++ = x32; *bptr++ = x35; *bptr = '\'; C Code (3 of 4) ECE 451 46 Material break; from or based on: The HCS12/9S12: An Introduction to Software & Hardware
C Code (4 of 4) } } case 2: /* fractional part is.5 */ *bptr++ = x2e; /* add decimal point */ *bptr++ = x35; *bptr = '\'; break; case 3: /* fractional part is.75 */ *bptr++ = x2e; /* add decimal point */ *bptr++ = x37; *bptr++ = x35; *bptr = '\'; break; default: break; ECE 451 47