MMDSP Debugger TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents... ICD In-Circuit Debugger... Processor Architecture Manuals... MMDSP... MMDSP Debugger... 1 General Note... 3 Brief Overview of Documents for New Users... 3 Warning... 4 Quick Start... 5 Troubleshooting... 7 SYStem.Up Errors 7 FAQ... 7 Configuration... 8 System Overview 8 CPU specific Implementations... 9 Breakpoints 9 Software Breakpoints 9 On-chip Breakpoints 10 On-chip Breakpoints on instructions 10 Downloading Program Code to the Video Core 11 Changing the FLAG Register 11 Memory Classes 12 General SYStem Commands... 14 SYStem.BdmClock Define JTAG frequency 14 SYStem.CONFIG Configure debugger according to target topology 14 Daisy-chain Example 16 TapStates 17 SYStem.CONFIG.CORE Assign core to TRACE32 instance 18 SYStem.CPU Select the used CPU 19 SYStem.CpuAccess Run-time memory access (intrusive) 20 SYStem.DictionaryReset Reset dictionary memory STN8810V 20 MMDSP Debugger 1
SYStem.JtagClock Define JTAG frequency 21 SYStem.LOCK Lock and tristate the debug port 21 SYStem.MemAccess Real-time memory access (non-intrusive) 22 SYStem.Mode Establish the communication with the target 22 SYStem.Option 8810compatible Set the compatibility mode 8810 23 SYStem.Option.DCUMode Select the DCU mode 23 SYStem.Option DIAG System diagnosis command 23 SYStem.Option EnReset Control activation of the reset line 24 SYStem.Option IMASKASM Disable interrupts while single stepping 24 SYStem.Option IMASKHLL Disable interrupts while HLL single stepping 24 SYStem.Option ICFLUSH Flush instruction cache (ST8810A) 25 SYStem.Option NMF Retrieves the value of pthis 25 SYStem.Option OP9compatible Compatibility mode OP9 25 SYStem.RESet Reset the system settings 26 SYStem.Softreset Soft reset of the core 26 CPU specific Commands... 27 Data.LOAD.Elf Load ELF file 27 Register.RESet Soft reset 27 SNoop.PC Enable PC snooping 28 CPU specific TrOnchip Commands... 29 TrOnchip.CONVert Adjust range breakpoint in on-chip resource 29 TrOnchip.VarCONVert Adjust complex breakpoint in on-chip resource 29 TrOnchip.state Display on-chip trigger window 29 TrOnchip.RESet Set on-chip trigger to default state 30 JTAG Connection... 31 Mechanical Description of the 20-pin Debug Cable 31 Electrical Description of the 20-pin Debug Cable 32 Operation Voltage... 33 Support... 34 Available Tools 34 Compilers 34 Target Operating Systems 34 3rd-Party Tool Integrations 35 Products... 36 Product Information 36 Order Information 36 MMDSP Debugger 2
MMDSP Debugger Version 22-Mar-2018 General Note This documentation describes the processor specific settings and features for the TRACE32 debugger. Brief Overview of Documents for New Users Architecture-independent information: Debugger Basics - Training (training_debugger.pdf): Get familiar with the basic features of a TRACE32 debugger. T32Start (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances for different configurations of the debugger. T32Start is only available for Windows. General Commands (general_ref_<x>.pdf): Alphabetic list of debug commands. Architecture-specific information: Processor Architecture Manuals : These manuals describe commands that are specific for the processor architecture supported by your debug cable. To access the manual for your processor architecture, proceed as follows: - Choose Help menu > Processor Architecture Manual. RTOS Debuggers (rtos_<x>.pdf): TRACE32 PowerView can be extended for operating systemaware debugging. The appropriate RTOS manual informs you how to enable the OS-aware debugging. MMDSP Debugger 3
Warning NOTE: To prevent debugger and target from damage it is recommended to connect or disconnect the debug cable only while the target power is OFF. Recommendation for the software start: 1. Disconnect the debug cable from the target while the target power is off. 2. Connect the host system, the TRACE32 hardware and the debug cable. 3. Power ON the TRACE32 hardware. 4. Start the TRACE32 software to load the debugger firmware. 5. Connect the debug cable to the target. 6. Switch the target power ON. 7. Configure your debugger e.g. via a start-up script. Power down: 1. Switch off the target power. 2. Disconnect the debug cable from the target. 3. Close the TRACE32 software. 4. Power OFF the TRACE32 hardware. MMDSP Debugger 4
Quick Start 1. Start the ARM debugger (for details see Quick Start of the JTAG Debugger in ARM Debugger (debugger_arm.pdf)) of the Nomadik, and set local memory bus frequency to 10 MHz: ; set local memory bus frequency = 10 MHz d.s 0x10000014 %l 0x000a05f d.s 0x10000008 %l 0x090c12a d.s 0x10000014 %l 0x0 2. Only required for Tracing via NEXUS: Enable NEXUS via ARM debugger D.S 0xE0000024 %be %b 0x40 D.S 0xE0000024 %be %b 0x80 ; only Audio MMDSP (STN8810A) ; only Video MMDSP (STN8810V) 3. Start the MMDSP debugger, select the device prompt B:, if the device prompt is not active after the TRACE32-Software is started. B:: 4. Select the core on your target, if automatic detection is not possible: SYStem.CPU STN8810A 5. Configure the Debugger to use on-chip breakpoints in memory areas that are read-only (e.g. FLASH/ROM): MAP.BOnchip 0xC00000++0x1fffff If a program breakpoint is set within the specified address range, on-chip breakpoints are now used instead of software breakpoints. A list of all available on-chip breakpoints for your architecture can be found under On-chip Breakpoints. 6. Enter the debug mode. SYStem.Up This command resets the CPU and enters the debug mode. After SYStem.Up it is possible to access the registers and the memory. MMDSP Debugger 5
7. Audio DSP only: Set the base and top address of program and data memory using the CacheCtrl registers. Default values can be seen in the example below for COB-10 and MEK Evaluation Boards. Alternatively the values can be set via a script for the ARM core at system power up. Refer also to the PER command. COB-10 Evaluation Board: Data.Set DBG:0x1038 %quad 0x0000000000200000 Data.Set DBG:0x1050 %quad 0x0080000000400000 Data.Set DBG:0x1058 %quad 0x0000000000C00000 ; PROG_BASE_ADR ; DATA_AHB_BASE ; DATA_AHB_TOP MEK FPGA Evaluation Board: Data.Set DBG:0x1038 %QUAD 0x00000000800a0000 Data.Set DBG:0x1050 %QUAD 0x802A0000801A0000 Data.Set DBG:0x1058 %QUAD 0x80320000803A0000 ; PROG_BASE_ADR ; DATA_AHB_BASE ; DATA_AHB_TOP 8. Load your application. Data.LOAD.Elf cppdemo.elf The load command depends on the file format generated by your compiler. Be sure to load a file compiled for the correct core. A full description of the Data.Load command is given in the General Commands Reference. MMDSP Debugger 6
Troubleshooting SYStem.Up Errors No information available. FAQ No information available No information available MMDSP Debugger 7
TRIG POWER 7-9 V PODBUS IN POWER SELECT EMULATE RECORDING TRIGGER CON ERR TRANSMIT RECEIVE COLLISION PODBUS OUT C B A Configuration System Overview HUB 100 MBit Ethernet PC or Workstation Debug Cable Target POWER DEBUG / ETHERNET Ethernet Cable USB ETHERNET LAUTERBACH RESERVED FOR POWER TRACE DEBUG CABLE DEBUG CABLE LAUTERBACH JTAG Connector POWER DEBUG / ETHERNET AC/DC Adapter MMDSP Debugger 8
CPU specific Implementations Breakpoints There are two implementations for breakpoints: Software breakpoints On-chip breakpoints For MMDSP it is only possible to set breakpoints when the clock is stopped. This applies to both software and on-chip breakpoints. Software Breakpoints In order to stop the program execution at a selected instruction, the code at the break location is patched by a software break instruction. If the software break instruction comes to the execution stage of the pipeline, the program execution is stopped and the debug mode becomes active. Software breakpoints can be set to instructions in RAM and with some preparations also to instructions in FLASH (see FLASH.Create and FLASH.AUTO). Software breakpoints on instructions in FLASH should only be used, if the number of on-chip breakpoints is insufficient. The number of software breakpoints is unlimited. STN8810A (Audio): note that modifications to the program memory like setting and removing a SW breakpoint require to flush the instruction cache to guarantee that the CPU sees the updated data. This cache flush is executed before program execution is resumed. To avoid these cache flushes resort to onchip breakpoints. The STN8810V (Video) is not affected as it does not have an instruction cache. MMDSP Debugger 9
On-chip Breakpoints This implementation is called on-chip, because the debugger uses resources provided by the processor to set a breakpoint. The MMDSP core is equipped with 2 watchpoint/breakpoint units. The following list gives an overview of the usage of the on-chip breakpoints by TRACE32-ICD: On-chip breakpoints: Total amount of available on-chip breakpoints. Instruction breakpoints: Number of on-chip breakpoints that can be used for program breakpoints. Read/Write breakpoints: Number of on-chip breakpoints that can be used as Read or Write breakpoints. Data breakpoints: Number of on-chip data breakpoints that can be used to stop the program when a specific data value is written to an address or when a specific data value is read from an address. CPU Family On-chip Breakpoints Instruction Breakpoints Read/Write Breakpoints Data Breakpoints MMDSP 3 2 1 1 On-chip Breakpoints on instructions On-chip breakpoints are handled by the CPU internally and do not require to modify the program memory. Therefore they can be used to set a breakpoint on an instruction in FLASH or ROM. With the command MAP.BOnchip <range> it is possible to instruct the debugger to use On-chip breakpoints for the specified range as default (it is still possible to override this with parameters like /SOFT for the break.set command). Typically it is used for FLASH/ROM memories. If a breakpoint is set within the specified address range, the debugger uses automatically the available on-chip breakpoints. Use the command MAP.List to see for which address ranges the debugger uses on-chip breakpoints. MMDSP Debugger 10
Example for Breakpoints Assume you have a target with FLASH from 0 to 0xFFFFF and RAM from 0x100000 to 0x11FFFF. The command to configure TRACE32 correctly for this configuration is: Map.BOnchip 0x0--0x0FFFFF The following breakpoint combinations are possible. Software breakpoints: Break.Set 0x100000 /Program ; Software Breakpoint 1 Break.Set 0x101000 /Program ; Software Breakpoint 2 Break.Set 0xx /Program ; Software Breakpoint 3 On-chip breakpoints: Break.Set 0x100 /Program ; On-chip Breakpoint 1 Break.Set 0x0ff00 /Program ; son-chip Breakpoint 2 Downloading Program Code to the Video Core The STN8810A and STN8810V are not object code compatible. When loading a program that was compiled for the wrong core, the message file not compiled for this processor is displayed. The Video Core employs a compression algorithm based on a dictionary. The dictionary is dynamically created while downloading the object code to the target. The algorithm exploits the fact that some instructions do not use all fields of the opcode to obtain better compression. While the functionality of an instruction is not affected by compression/decompression, a reconstructed opcode will not be necessarily binary identical to the original opcode. Therefore the /verify option for the data.load command may produce false error message when used for download code to the video core. Changing the FLAG Register Changing the FLAG register through the debugger is not supported. MMDSP Debugger 11
Memory Classes The following DSP specific memory classes are available. Memory Class P X Y DBG Description Program Memory Data Memory (X-Bus) Data Memory (Y-Bus) Debug Memory The Video core STN8810V uses a dictionary for compressing its program memory. When writing code to the program memory (e.g. by downloading a program to the target via Data.LOAD.Elf or by writing to a P: memory location), the debugger automatically adds necessary dictionary entries derived from the written program data. This is hidden from the user, who accesses program memory always in 64bit words (one VLIW instruction). The compressed program and dictionary memories can be accessed via the DBG: memory class (see below). Downloading a program to the target via Data.LOAD.Elf deletes the old dictionary and therefore may invalidate instructions, even if their are not physically overwritten by the new program. The DBG memory class gives access to memory resources like host register, indirect host registers, and dictionary ram (Video core only). The mapping of these resources to addresses is arbitrary and does not relate to any MMDSP or system address mappings. The mapping is only valid in the context of the DBG memory class. Address Range DBG: 0x0000-- 0x007f DBG: 0x1000-- 0x1FFF DBG: 0x2000-- 0x5FFF DBG: 0x6000-- *: Mapped Resource host registers, 8 bit width indirect host registers, up to 64bit wide dictionary memory, 53bit wide (Video) compressed instructions, 24bit wide (Video) To access a memory class write the class specifier in front of the address: Data.dump p:0--3 MMDSP Debugger 12
For accessing indirect host registers (DBG: 0x1000--0x1FFF), the 64bit access width needs to be specified: d.in dbg:0x1015 /quad print data.quad(dbg:0x1015) d.out dbg:0x1015 %quad 0x1122334455667788 Note that for MMDSP it is not possible to access memory through the debugger while the core is executing code. For not CPU-specific keywords, see non-declarable input variables in ICE/FIRE Analyzer Trigger Unit Programming Guide (analyzer_prog.pdf). MMDSP Debugger 13
General SYStem Commands SYStem.BdmClock Define JTAG frequency Obsolete command syntax. It has the same effect as SYStem.JtagClock. Use SYStem.JtagClock instead. SYStem.CONFIG Configure debugger according to target topology SYStem.CONFIG <parameter> <number_or_address> SYStem.MultiCore <parameter> <number_or_address> (deprecated) <parameter>: CORE <core> <parameter>: (JTAG): DRPRE <bits> DRPOST <bits> IRPRE <bits> IRPOST <bits> TAPState <state> TCKLevel <level> TriState [ON OFF] Slave [ON OFF] The four parameters IRPRE, IRPOST, DRPRE, DRPOST are required to inform the debugger about the TAP controller position in the JTAG chain, if there is more than one core in the JTAG chain (e.g. ARM + DSP). The information is required before the debugger can be activated e.g. by a SYStem.Up. See Daisychain Example. For some CPU selections (SYStem.CPU) the above setting might be automatically included, since the required system configuration of these CPUs is known. TriState has to be used if several debuggers ( via separate cables ) are connected to a common JTAG port at the same time in order to ensure that always only one debugger drives the signal lines. TAPState and TCKLevel define the TAP state and TCK level which is selected when the debugger switches to tristate mode. Please note: ntrst must have a pull-up resistor on the target, TCK can have a pull-up or pull-down resistor, other trigger inputs need to be kept in inactive state. Multicore debugging is not supported for the DEBUG INTERFACE (LA-7701). MMDSP Debugger 14
CORE DRPRE DRPOST IRPRE IRPOST TAPState TCKLevel TriState Slave For multicore debugging one TRACE32 GUI has to be started per core. To bundle several cores in one processor as required by the system this command has to be used to define core and processor coordinates within the system topology. Further information can be found in SYStem.CONFIG.CORE. (default: 0) <number> of TAPs in the JTAG chain between the core of interest and the TDO signal of the debugger. If each core in the system contributes only one TAP to the JTAG chain, DRPRE is the number of cores between the core of interest and the TDO signal of the debugger. (default: 0) <number> of TAPs in the JTAG chain between the TDI signal of the debugger and the core of interest. If each core in the system contributes only one TAP to the JTAG chain, DRPOST is the number of cores between the TDI signal of the debugger and the core of interest. (default: 0) <number> of instruction register bits in the JTAG chain between the core of interest and the TDO signal of the debugger. This is the sum of the instruction register length of all TAPs between the core of interest and the TDO signal of the debugger. (default: 0) <number> of instruction register bits in the JTAG chain between the TDI signal and the core of interest. This is the sum of the instruction register lengths of all TAPs between the TDI signal of the debugger and the core of interest. (default: 7 = Select-DR-Scan) This is the state of the TAP controller when the debugger switches to tristate mode. All states of the JTAG TAP controller are selectable. (default: 0) Level of TCK signal when all debuggers are tristated. (default: OFF) If several debuggers share the same debug port, this option is required. The debugger switches to tristate mode after each debug port access. Then other debuggers can access the port. JTAG: This option must be used, if the JTAG line of multiple debug boxes are connected by a JTAG joiner adapter to access a single JTAG chain. (default: OFF) If more than one debugger share the same debug port, all except one must have this option active. JTAG: Only one debugger - the master - is allowed to control the signals ntrst and nsrst (nreset). MMDSP Debugger 15
Daisy-chain Example TDI Core A Core B Core C Core D TDO Chip 0 Chip 1 Below, configuration for core C. Instruction register length of Core A: 3 bit Core B: 5 bit Core D: 6 bit SYStem.CONFIG.IRPRE 6 SYStem.CONFIG.IRPOST 8 SYStem.CONFIG.DRPRE 1 SYStem.CONFIG.DRPOST 2 ; IR Core D ; IR Core A + B ; DR Core D ; DR Core A + B SYStem.CONFIG.CORE 0. 1. ; Target Core C is Core 0 in Chip 1 MMDSP Debugger 16
TapStates 0 Exit2-DR 1 Exit1-DR 2 Shift-DR 3 Pause-DR 4 Select-IR-Scan 5 Update-DR 6 Capture-DR 7 Select-DR-Scan 8 Exit2-IR 9 Exit1-IR 10 Shift-IR 11 Pause-IR 12 Run-Test/Idle 13 Update-IR 14 Capture-IR 15 Test-Logic-Reset MMDSP Debugger 17
SYStem.CONFIG.CORE Assign core to TRACE32 instance SYStem.CONFIG.CORE <coreindex> <chipindex> SYStem.MultiCore.CORE <coreindex> <chipindex> (deprecated) <chipindex>: 1 i <coreindex>: 1 k Default coreindex: depends on the CPU, usually 1. for generic chips Default chipindex: derived from CORE= parameter of the configuration file (config.t32). The CORE parameter is defined according to the start order of the GUI in T32Start with ascending values. To provide proper interaction between different parts of the debugger the systems topology must be mapped to the debuggers topology model. The debugger model abstracts chips and sub-cores of these chips. Every GUI must be connect to one unused core entry in the debugger topology model. Once the SYStem.CPU is selected a generic chip or none generic chip is created at the default chipindex. None Generic Chips None generic chips have a fixed amount of sub-cores with a fixed CPU type. First all cores have successive chip numbers at their GUIs. Therefore you have to assign the coreindex and the chipindex for every core. Usually the debugger does not need further information to access cores in none generic chips, once the setup is correct. Generic Chips Generic chips can accommodate an arbitrary amount of sub-cores. The debugger still needs information how to connect to the individual cores e.g. by setting the JTAG chain coordinates. Start-up Process The debug system must not have an invalid state where a GUI is connected to a wrong core type of a none generic chip, two GUI are connected to the same coordinate or a GUI is not connected to a core. The initial state of the system is value since every new GUI uses a new chipindex according to its CORE= parameter of the configuration file (config.t32). If the system contains fewer chips than initially assumed, the chips must be merged by calling SYStem.CONFIG.CORE. MMDSP Debugger 18
SYStem.CPU Select the used CPU SYStem.CPU <cpu> <cpu>: ST8810A ST8810V STN8815A STN8815V STN8820A STN8820V STN8820 I Selects the processor type. Default selection: STN8810A. STN881xA is the Audio DSP, STN881xV is the Video DSP. MMDSP Debugger 19
SYStem.CpuAccess Run-time memory access (intrusive) SYStem.CpuAccess <mode> <mode>: Enable Denied Nonstop The SYStem.CpuAccess command controls if the debugger may use the CPU to perform intrusive memory operations while the clock is running. If enabled, these memory operations are performed by briefly stopping the CPU, performing the access and activating the CPU again. Enable Denied For performing a memory access (r/w) while the CPU is executing, the debugger interrupts program execution briefly. Each interruption takes 1 100 ms depending on the speed of the debug interface and on the number of the read/write accesses required. Window updates e.g. for data.dump windows are on default performed 10 times/s. The debugger is not allowed to interrupt program execution for performing memory accesses. Default setting. Nonstop Nonstop ensures that the debugger will not affect the real-time behavior of the system in any way. This includes blocking of the break command and of other intrusive features like performance analysis via StopAndGo, conditional breakpoints etc. For MMDSP the option NonStop reduces the functionality to tracing the program flow as no memory access can be performed by the debugger while the clock is running. SYStem.DictionaryReset Reset dictionary memory STN8810V SYStem.DictionaryReset Logically resets the program dictionary memory. This command does not actually clear the dictionary memory in the target. It simply resets the buffer in the debugger. Therefore the dictionary will be overwritten if new instructions are written to program memory. Only relevant for STN8810V (Video core). MMDSP Debugger 20
SYStem.JtagClock Define JTAG frequency SYStem.JtagClock [<frequency> ARTCK <frequency>] <frequency>: 10000. 40000000. Default frequency: 10 MHz. Selects the JTAG port frequency (TCK) used by the debugger to communicate with the processor. The frequency affects e.g. the download speed. It could be required to reduce the JTAG frequency if there are buffers, additional loads or high capacities on the JTAG lines or if VTREF is very low. A very high frequency will not work on all systems and will result in an erroneous data transfer. Therefore we recommend to use the default setting if possible. <frequency> The debugger cannot select all frequencies accurately. It chooses the next possible frequency and displays the real value in the SYStem.state window. Besides a decimal number like 100000. also short forms like 10kHz or 15MHz can be used. The short forms imply a decimal value, although no. is used. SYStem.LOCK Lock and tristate the debug port SYStem.LOCK [ON OFF] Default: OFF. If the system is locked, no access to the debug port will be performed by the debugger. While locked, the debug connector of the debugger is tristated. The main intention of the lock command is to give debug access to another tool. MMDSP Debugger 21
SYStem.MemAccess Real-time memory access (non-intrusive) SYStem.MemAccess Denied <cpu_specific> SYStem.ACCESS (deprecated) Denied Real-time memory access during program execution to target is disabled. In general the SYStem.MemAccess command controls how the debugger accesses system memories while the clock is running. Due to the design of MMDSP there is no way for the debugger to access memory resources without stopping the clock. Therefore the only possible selection for this option is denied. SYStem.Mode Establish the communication with the target SYStem.Mode <mode> <mode>: Down NoDebug Go Attach Up Down NoDebug Go Attach Up (default) Disables the debugger. The state of the DSP remains unchanged. The JTAG port is tristated. No reset of the CPU. same as Down, but CPU is running. Same as Up, but CPU is running: Resets the CPU, enables the debug mode and starts the user program immediately. The program execution can be stopped manually or at a breakpoint. Onchip breakpoints can be used in Go mode. On-chip breakpoints have to be set before e.g. by using the SYStem.Mode Up command. The connection to the DSP is established without resetting the DSP. Select NoDebug before you connect the debugger cable or NEXUS adapter to the target and switch then to Attach. Resets the DSP and establishes the connection. After the execution of this command the DSP is stopped and all register are set to their default values. ST8810V: due to code compression, only with SYStem.Up the program memory is completely reset! MMDSP Debugger 22
SYStem.Option 8810compatible Set the compatibility mode 8810 SYStem.Option 8810compatible [ON OFF] Default: OFF The command sets the compatibility register at MMIO@0xf60a. It is relevant only for the STN8815 and STN8820 cores. Specifically it sets the following values: MMIO@0xf60a = 0x10f8 // native mode; for executing 8815 code = 0x1cf8 // compatibility mode; for excuting 8810 code SYStem.Option.DCUMode Select the DCU mode SYStem.Option DCUMode [AUTO 16 24] In the system window it is possible to select the DCU mode assumed by the debugger for displaying registers and variables. The mode can be set via the option sys.o.dcumode [auto 24 16 ]. In mode auto, the mode is detected from the FLAGS register or the deduced from the stack frame. In mode 16 or 24, all registers and variables are displayed in the chosen mode, independently from the actual DCU mode of the CPU. NOTE: The setting only changes the display in the debugger, it does not change the actual mode the DSP core is in. For changing the DCU mode in the target, the FLAGS register needs to be modified in the target. SYStem.Option DIAG System diagnosis command SYStem.DIAG [code [P1] [P2] [P3]] System diagnosis command. Execute only when demanded by LAUTERBACH support engineer. MMDSP Debugger 23
SYStem.Option EnReset Control activation of the reset line SYStem.Option EnReset [ON OFF] Default: OFF. The command controls whether the debugger will (ever) pull the reset line. As the MMDSP is normally used as "slave" in multi-core systems, the default setting for the option is OFF. Consequently the reset line will never be activated on default. Additionally you might want to use the option "SYStem.CONFIG SLAVE ON" in order to also disable the reset of the TAP controller when connecting to the target. SYStem.Option IMASKASM Disable interrupts while single stepping SYStem.Option IMASKASM [ON OFF] Default: OFF. If enabled, all interrupts will be masked during assembler single-step operations by use of the EMU_UNIT_MASKIT register (MMIO @ 0xF600). After the single step the register is restored to the original value. If the option is disabled, the EMU_UNIT_MASKIT register is not modified. SYStem.Option IMASKHLL Disable interrupts while HLL single stepping SYStem.Option IMASKHLL [ON OFF] Default: OFF. If enabled, all interrupts will be masked during HLL single-step operations by use of the EMU_UNIT_MASKIT register (MMIO @ 0xF600). After the single step the register is restored to the original value. If the option is disabled, the EMU_UNIT_MASKIT register is not modified. MMDSP Debugger 24
SYStem.Option ICFLUSH Flush instruction cache (ST8810A) SYStem.Option ICFLUSH [ON OFF] Default: ON. If enabled, the Echoic will be flushed before GO or Step operations. This is required to enforce consistency between cache and external program memory when the program memory was updated (e.g. for setting software breakpoints). Typically the option shall be left enabled except when debugging cache consistency problems in the target. The option is only relevant for ST8810A because it has a program cache. SYStem.Option NMF Retrieves the value of pthis SYStem.Option NMF [ON OFF] Default: OFF The command is only relevant when using the NMF (Nomadik Multiprocessing Framework). When the option is enabled, the debugger retrieves the value of pthis from the target memory everytime it uploads the registers values from the core. The value of pthis is used to detect the currently active NMF module. There is a pseudo register call pthis that is listed in the register window and can be accesses via the register function similar to actual core registers. A pseudo register is an artificial register that has no corresponding register in the CPU, but is used to conveniently handle data that is useful in the context of register manipulation. Register print register(pthis) ; open the Register window ; print the value of pthis SYStem.Option OP9compatible Compatibility mode OP9 SYStem.Option OP9compatible [ON OFF] This command enables the compatibility mode for the hcmos 9 MMDSP+ core by setting the register COMPATIBLE_REG @ MMIO(0xF60A). MMDSP Debugger 25
SYStem.RESet Reset the system settings SYStem.RESet Reset all settings of the T32 debugger to default values. NOTE: This does not reset the target system! SYStem.Softreset Soft reset of the core SYStem.Softreset Performs a soft reset of the DSP core. MMDSP Debugger 26
CPU specific Commands Data.LOAD.Elf Load ELF file Data.LOAD.Elf <filename> Downloads an ELF file to the target. Note that for MMDSP targets the debugger performs a soft reset for setting the program counter to the program entry point at P:0x0. Register.RESet Soft reset Register.RESet Sets all registers to their initial value after a reset. This is done via soft reset of the core which may have effects besides updating the contents of architectural registers. MMDSP Debugger 27
SNoop.PC Enable PC snooping SNoop.PC SNoop.PC [ON OFF] (from 8820) Reading the PC without stopping the target ( PC-snooping ) is available from 8820 and later. SNoop.PC SNoop.PC ON OFF Prints the current PC in the info line (only once) Enables or disables that the debugger permanently updates the PC in info line The PC-snooping hardware feature is most useful in the context of statistical runtime analysis. This is illustrated in the following script: perf perf.list perf.method snoop perf.mode function GO ; open perf config window ; open perf chart ; display info based on function usage The visible difference between PERF.METHOD Snoop and PERF.METHOD StopAndGo is that for "stopandgo" the debugger will indicate real-time violations (red "s" in the bottom status line). Also, snooping is much faster than StopAndGo and thus done more frequently which results in a more detailed statistical analysis. MMDSP Debugger 28
CPU specific TrOnchip Commands TrOnchip.CONVert Adjust range breakpoint in on-chip resource TrOnchip.CONVert [ON OFF] The on-chip breakpoints can only cover specific ranges. If a range cannot be programmed into the breakpoint, it will automatically be converted into a single address breakpoint when this option is active. This is the default. Otherwise an error message is generated. TrOnchip.CONVert ON Break.Set 0x1000--0x17ff /Write Break.Set 0x1001--0x17ff /Write TrOnchip.CONVert OFF Break.Set 0x1000--0x17ff /Write Break.Set 0x1001--0x17ff /Write ; sets breakpoint at range ; 1000--17ff sets single breakpoint ; at address 1001 ; sets breakpoint at range ; 1000--17ff ; gives an error message TrOnchip.VarCONVert Adjust complex breakpoint in on-chip resource TrOnchip.VarCONVert [ON OFF] The on-chip breakpoints can only cover specific ranges. If you want to set a marker or breakpoint to a complex variable, the on-chip break resources of the CPU may be not powerful enough to cover the whole structure. If the option TrOnchip.VarCONVert is ON the breakpoint will automatically be converted into a single address breakpoint. This is the default setting. Otherwise an error message is generated. TrOnchip.state Display on-chip trigger window TrOnchip.state Opens the TrOnchip.state window. MMDSP Debugger 29
TrOnchip.RESet Set on-chip trigger to default state TrOnchip.RESet Sets the TrOnchip settings and trigger module to the default settings. MMDSP Debugger 30
JTAG Connection Mechanical Description of the 20-pin Debug Cable Signal Pin Pin Signal VTREF 1 2 N/C TRST- 3 4 GND TDI 5 6 GND TMS 7 8 GND TCK 9 10 GND N/C 11 12 GND TDO 13 14 GND RSTIN- 15 16 GND N/C 17 18 GND N/C 19 20 GND This is a standard 20 pin double row connector (pin to pin spacing: 0.100 in.). We strongly recommend to use a connector on your target with housing and having a center polarisation (e.g. AMP: 2-827745-0). A connection the other way around indeed causes damage to the output driver of the debugger. MMDSP Debugger 31
Electrical Description of the 20-pin Debug Cable The input and output signals are connected to a supply translating transceiver (74ALVC164245). Therefore the ICD/AICD can work in an voltage range of (1.5 V) 1.8 3.3 V (3.6 V). Please note that a 5 V supply environment is not supported! This would cause damage on the ICD/AICD. Please contact us for alternate solutions if you need to work with 5 V. VTREF is used as a sense line for the target voltage. It is also used as supply voltage for the supply translating transceiver of the ICD/AICD interface to make an adaptation to the target voltage (1.5 V) 1.8 3.3 V (3.6 V). ntrst, TDI, TMS, TCK are driven by the supply translating transceiver. In normal operation mode this driver is enabled, but it can be disabled to give another tool access to the JTAG port. In environments where multiple tools can access the JTAG port, it is absolutely required that there is a pull down resistor at TCK. This is to ensure that TCK is low during a handover between different tools. TDO is an ICD/AICD input. It is connected to the supply translating transceiver. nrstin is used by the debugger to reset the target CPU or to detect a reset on the target. It is driven by an open collector buffer. A 47 k pull-up resistor is included in the ICD/AICD connector. The debugger will only assert a pulse on nsrst when the SYStem.UP, the SYStem.Mode Go or the SYStem.RESetOUT command is executed. If it is ensured that the DSP is able to enter debug mode every time (no hangup condition), the nsrst line is optional. N/C (= Vsupply) is not connected in the ICD/AICD. This pin is used by debuggers of other manufacturers for supply voltage input. The ICD/AICD is self-powered. There is an additional plug in the connector on the debug cable to the debug interface. This signal is tristated if the JTAG connector is tristated by the debugger and it is pulled low otherwise. This signal is normally not required, but can be used to detect the tristate state if more than one debug tools are connected to the same JTAG port. MMDSP Debugger 32
Operation Voltage Adapter OrderNo Voltage Range JTAG Debugger for MMDSP (ICD) LA-7836 1.8.. 3.6 V JTAG Debugger License for MMDSP LA-7836A 1.8.. 3.6 V MMDSP Debugger 33
Support Available Tools CPU ICE FIRE ICD DEBUG ICD MONITOR ICD TRACE POWER INTEGRATOR INSTRUCTION SIMULATOR A9500 YES YES YES A9540 YES YES YES DB8500 YES YES YES DB8540 YES YES YES STN8810 YES YES YES STN8815 YES YES YES STN8820 YES YES YES Compilers Language Compiler Company Option Comment C MMDSP+ ST Microelectronics N.V. ELF/DWARF Target Operating Systems Not supported yet. MMDSP Debugger 34
3rd-Party Tool Integrations CPU Tool Company Host WINDOWS CE PLATF. - Windows BUILDER CODE::BLOCKS - - C++TEST - Windows ADENEO - X-TOOLS / X32 blue river software GmbH Windows CODEWRIGHT Borland Software Windows Corporation CODE CONFIDENCE Code Confidence Ltd Windows TOOLS CODE CONFIDENCE Code Confidence Ltd Linux TOOLS EASYCODE EASYCODE GmbH Windows ECLIPSE Eclipse Foundation, Inc Windows CHRONVIEW Inchron GmbH Windows LDRA TOOL SUITE LDRA Technology, Inc. Windows UML DEBUGGER LieberLieber Software Windows GmbH SIMULINK The MathWorks Inc. Windows ATTOL TOOLS MicroMax Inc. Windows VISUAL BASIC Microsoft Corporation Windows INTERFACE LABVIEW NATIONAL Windows INSTRUMENTS Corporation RAPITIME Rapita Systems Ltd. Windows RHAPSODY IN MICROC IBM Corp. Windows RHAPSODY IN C++ IBM Corp. Windows DA-C RistanCASE Windows TRACEANALYZER Symtavision GmbH Windows ECU-TEST TraceTronic GmbH Windows UNDODB Undo Software Linux TA INSPECTOR Vector Windows VECTORCAST UNIT Vector Software Windows TESTING VECTORCAST CODE COVERAGE Vector Software Windows MMDSP Debugger 35
Products Product Information OrderNo Code LA-7836 JTAG-MMDSP LA-7836A JTAG-MMDSP-A LA-3722 CON-JTAG20-MICTOR Text JTAG Debugger for MMDSP (ICD) supports MMDSP includes software for Windows, Linux and MacOSX requires Power Debug Module JTAG Debugger License for MMDSP supports MMDSP additional license for all ARM dongles please add the base serial number of your debug cable to your order ARM Converter ARM-20 to Mictor-38 Converter to connect the ARM Debug Cable to a Mictor connector on the target providing both debug and trace signals. This is needed if you want to connect the Debug Cable without a Preprocessor and if there is only a Mictor on the target. Suitable for MMDSP and ARC as well. Order Information Order No. Code Text LA-7836 JTAG-MMDSP JTAG Debugger for MMDSP (ICD) LA-7836A JTAG-MMDSP-A JTAG Debugger License for MMDSP LA-3722 CON-JTAG20-MICTOR ARM Converter ARM-20 to Mictor-38 Additional Options LA-7744A JTAG-ARM10-A JTAG Debugger License for ARM10 Add. LA-7765A JTAG-ARM11-A JTAG Debugger License for ARM11 Add. LA-7746A JTAG-ARM7-A JTAG Debugger License for ARM7 Add. LA-7742A JTAG-ARM9-A JTAG Debugger License for ARM9 Add. LA-7843A JTAG-ARMV7-A/R-A JTAG Debugger Lic. Cortex-A/-R (32-bit) Add. LA-7844A JTAG-CORTEX_M-A JTAG Debugger License for Cortex-M Add. LA-7960X MULTICORE-LICENSE License for Multicore Debugging MMDSP Debugger 36