Understanding SPI with Precision Data Converters By: Tony Calabria Presented by: 1
Communication Comparison SPI - Serial Peripheral Interface Bus I2C - Inter- Integrated Circuit Parallel Bus Advantages Four wire interface Medium to fast data transfer speeds Full Duplex Communication Protocol flexibility Sharable Bus Two wire interface Sharable using inband address scheme Formal Standard Fast data transfer speeds Allows for fast Data converter sample rates Faster register loading Disadvantages No Formal Standard No in-band addressing No slave acknowledgement Supports one master Only short to medium distances Slower data transfer speeds Limited to 8 bit words Limited travel distance Requires pull up resistors Requires many pins Requires many traces Could cause complex layout 2
Agenda SPI Basics Timing Requirements Datasheet shown to Scale Conversion Interrupts 3
SPI History Name SPI was created by Motorola (now Freescale) There are 4 lines - 2 control lines and 2 data lines Speed of SPI bus (or clock rate) can go up to 70MHz. SPI transmits in full duplex simultaneously for both input and output data SPI requires one master and one or more slaves SPI bus is a very loose standard for control of almost any digital electronics There are also Queued SPI (QSPI), Microwire trade mark of National Semiconductor, and MicrowirePLUS, each of which is generally considered as an SPI too TI Precision Data converters SPI compatible Interface 4
High Level look Serial Peripheral Interface Bus (SPI) Master/Slave Controller/Receiver Full Duplex Send and receive simultaneously Four-wire serial bus SS Slave Select Serial Clock for the interface MOSI Master Out Slave In MISO Master In Slave Out 5
Typical SPI Bus MSP430 DSP FPGA SS MOSI MISO SPI Slave SS MOSI MISO SPI Slave SPI Master SS3 SS2 SS MOSI MISO SS MOSI MISO SPI Slave 6
SS Slave Select Slave transmit enable signal Commonly known as Chip Select or /CS Activates the SPI bus Commonly active low Sharing the SPI bus Each Slave requires own SS signal Specific SS signal active for communicating slave SS MOSI MISO 7
Clock signal for SPI transfer Transmitted from master Controls when data is transferred and latched Can be run at speeds in the tens of MHz Can Idle high or low (Clock Polarity) SS MOSI MISO 8
MOSI Data input signal DIN, DI, SDI Edge Triggered One edge used to change data Opposite edge used to latch data into slave Time between edges used for bit to transition and settle SS MOSI MISO 9
MISO Data output signal DOUT, DO, SDO Edge Triggered Slave pin becomes tri-state with SS inactive Allow to share the line across a SPI bus SS MOSI MISO 10
Clock Phasing/Polarity Clock Polarity (CPOL) Sets the base value for Clock Phase (CPHA) Determines edge data is captured on. CPHA = 0 Data captured on first clock edge CPHA = 1 Data captured on second clock edge CPOL = 0 CPHA = 0 CPHA = 1 DATA CPOL = 1 CPHA = 0 CPHA = 1 DATA 11
Critical Edge Determines clock edge when data is stable vs changing Used to set CPOL and CPHA Configure the SPI master When to latch in Data from MISO (DOUT) When to have data change on MOSI (DIN) Standard SPI uses same edge to send and receive MOSI (DIN) of converter sets critical edge 12
Critical Edge Example 1 Falling edge = Critical edge 13
Critical Edge Example 2 Timing specs related to rising edge of Rising Edge latches data in 14
Setting up the Interface Rising edge the Critical Edge in example can idle high or low in example CPOL = 0, CPHA = 0 DATA CPOL = 1, CPHA = 1 DATA 15
Agenda SPI Basics Timing Requirements Datasheet shown to Scale Conversion Interrupts 16
Timing Specs Clocking in the bits Setup times Hold times How/When MSB clocked out Propagation Delay Clocking out the bits Setup times Hold times Driving the bit change Speed Limitations Reasserting /CS 17
Clocking in the Bits Setup time Period data must be valid before critical edge Setup time DIN Hold time Required by converter Defined by controller Hold time Trans period Bit Don t Care Period data required to be valid after critical edge * Falling edge critical edge Required by converter 18
Clocking out the MSB Not driven by edge Propagation delay time until MSB out Busy/DRDY Interrupt Driven /CS /SS Enable Serial Interface /RD Signal Driven Data Unknown State MSB 19
MSB Propagation Delay Could miss MSB if clock edge appears too early Interrupt Prop delay * Falling edge critical edge MSB State Unknown DOUT MSB MSB - 1 MSB - 2 20
Clocking out the Bits DOUT Setup time Trans period * Falling edge critical edge MSB - 1 Don t Care Hold time Setup time Period data must be valid before critical edge Required by controller Set by converter Hold time Period data guaranteed to be valid after critical edge Required by controller Defined by converter 21
Driving the Bit Change The change is triggered off of Opposite edge Critical edge Opposite Edge Critical Edge MSB Transition period MSB - 1 MSB - 2 MSB Transition period MSB - 1 Fixed Hold Time 22
Speed limitation Edge driving bit change may limit speed Bit must be settled before latched into controller Bit transition time limits speed Opposite edges used to send/receive data Non-standard SPI interface FPGA Full control DOUT Transition period Bit * Falling edge critical edge 23
Possible Solutions DOUT Increased period Transition period Bit Increase Period Meet Setup/Hold timing of interface Limit throughput of converter. Use Opposite Edge Requires data changes after non-critical edge Verify valid hold time for processor Use opposite edges to read/write may require FPGA * Falling edge critical edge DOUT Read using opposite edge Transition period Bit 24
Reasserting /CS Occurs at End of Frame May latch the data word Not always required Final edge to /CS high 3-State Dout /CS Delay from Critical Edge DOUT LSB 25
ADS8332 Timing Example Reassert /CS MSB Propagation Delay Falling edge drives the bit change Falling edge is critical edge 26
Agenda SPI Basics Timing Requirements Datasheet shown to Scale Conversion Interrupts 27
Datasheet timing 28
Drawn to Scale 20MHz 25ns 50ns Read on falling edge 25ns 5ns DOUT MSB 33ns MSB-1 = 20MHz DVDD = 3.0V Transition Period Visually transition occurs on rising edge 29
Drawn to Scale 1MHz 500ns 1000ns Read on falling edge 500ns 5ns DOUT MSB 33ns MSB-1 = 1MHz DVDD = 3.0V Transition Period Visually transition occurs near falling edge 30
Agenda SPI Basics Timing Requirements Datasheet shown to Scale Conversion Interrupts 31
Interrupt Driven Alert user when conversion complete and new data is ready Signal from device used for an Interrupt Service Routine Frequency set by the data rate Signal types: /DRDY, DOUT/DRDY, EOC, BUSY I/O Alert pin Edge Driven Uses conversion clock for timing 32
Dedicated vs Shared Pin Dedicated Pin New data is ready with /DRDY falling edge /DRDY signal returns high with first falling edge Shared Pin /DRDY functionality shared with DOUT Signal will idle high and use falling edge to indicate data ready. Line will then shift data out 33
/DRDY Visual Interpretation /DRDY will appear differently depending on if the conversions are read back /DRDY will return high once MSB read back /DRDY will remain low until the interface sees an /DRDY /DRDY appears idle high DOUT /DRDY /DRDY appears idle low DOUT 34
Summary Understand the timing specs Make sure the timing specs can be met by the host processor Understand processor flexibility Ask about data rate planned to be used Will tell you required data transfer speed 35