This exam is open book and open notes. You have 50 minutes. Credit for problems requiring calculation will be given only if you show your work. 1. ALU Design / Logic Operations 20 Points The subset of the MIPS instruction set that is supported by the ALU design in Chapter 4 includes two bitwise Boolean operations: AND and OR. The full MIPS architecture specifies also the NOR, NOT, and Exclusive OR (XOR) operations. In this problem we will consider using a four-to-one multiplexer as a universal function unit, as shown here: Control Inputs 0 0 0 1 C0 C1 C2 C3 Data Inputs Ai Bi 0 1 2 3 Yi Data Output In this circuit the select inputs of the multiplexer are treated as data signals, where each possible value of A i and B i selects a control input value C0, C1, C2, or C3. By setting the control inputs to different values, we can make the function unit perform an arbitrary boolean function of the two inputs A i and B i. As shown in the example above, making the inputs C0=0, C1=0, C2=0, and C3=1 makes the output Y i =1 only when A i =1 and B i =1. This computers an AND function, as shown in the table below. Similarly, making the inputs C0=0, C1=1, C2=1, and C3=1 makes the output Y i =1 whenever either A i =1 or B i =1. This computes an OR function. (a) Fill in the rest of the table below to show how the function unit could be used to compute the logic functions A i NOR B i, NOT A i, and A i XOR B i. Function C0 C1 C2 C3 AND 0 0 0 1 OR 0 1 1 1 NOR NOT Ai XOR Page 1 of 6
(b) Redesign the 1-bit ALU slice shown in Figure 4.16 of the book (p. 236) using the function unit to replace the AND and OR gates that perform logic functions, allowing the ALU to perform the additional MIPS boolean instructions. Draw a diagram of your redesigned circuit in the space provided below. How many control inputs does the modified ALU have? 2. Floating Point / Logical & Shifting Instructions 20 Points A single-precision IEEE floating-point number is stored a memory location X. Write a sequence of MIPS assembly instructions that will calculate the absolute value of this number and store the result back in memory location X. Accomplish this without using any floating point instructions. Page 2 of 6
3. Floating Point Representation 20 Points (a) In the space provided below, show the largest positive number that can be represented in IEEE single-precision floating point. Also, write the power of two (i.e., 2 X ) that most closely represents the value of this number. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Closest power of two: (b) In the space provided below, show the smallest negative number (where smallest means closest to zero ) that can be represented in IEEE single-precision floating point. Also, write the power of two (i.e., 2 X ) that most closely represents the value of this number. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Closest power of two: (c) Translate the number shown below in IEEE single-precision floating point format into its decimal equivalent and writes its value in the space provided below. 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value of number: Page 3 of 6
4. Single-Cycle Processor Design 20 Points Modify the single-cycle datapath and control to implement the jr (jump register) instruction. The register transfer description for this instruction is as follows: PC <- Reg[rs] Mark the necessary changes to the datapath and control on the diagrams shown below. (See Book Figure 5.33, p. 383) Instruction RegDst ALUSrc MemtoReg Reg Write Control Table Mem Read Mem Write Branch ALUOp1 ALUOp0 jr Page 4 of 6
5. Multi-Cycle Processor Design 20 Points Modify the multi-cycle processor datapath and control to implement the jr (jump register) instruction. The register transfer description is the same as in the previous problem. Mark your changes on the attached schematic diagram and state diagram. How many clock cycles are required to execute the jump register instruction? (See Book Figure 5.33, p. 383) Page 5 of 6
Multicycle Design State Diagram (see Book Fig. 5.42, p. 396) Page 6 of 6