Serial Communication Spring, 2018 Prof. Jungkeun Park
Serial Communication Serial communication Transfer of data over a single wire for each direction (send / receive) Process of sending data one bit at a time, sequentially, over a communication channel or computer bus Convert parallel data to a serial bit stream, and vice versa Serial vs. parallel Lower cable cost Asynchronous communication is possible Higher clock rate 2
Examples of Serial Communication RS-232 / 422 / 423 / 485 I2C Inter-Integrated Circuit SPI Serial Peripheral Interface Bus Universal Serial Bus (USB) FireWire (IEEE1394) A/V component comm. Ethernet MIDI Electronic musical instruments Serial ATA (SATA) Mass storage devices PCI Express Computer expansion bus ARINC 818 Avionics Digital Video Bus (ADVB) SpaceWire Spacecraft communication network MIL-STD-1553 Military avionics, spacecraft on-board data handling 3
Synchronous vs. Asynchronous Synchronous sender and receiver share common clock data stream is synchronized with the common clock Asynchronous sender and receiver have local clock with the same frequency (baud rate) start / stop bit to indicate frame start / end phase lock receiver s clock to the phase of transmitted data Universal Asynchronous Receiver Transmitter (UART) 4
UART Universal Asynchronous Receiver/Transmitter translate data between parallel and serial forms in logic levels data format and transmission speeds are configurable commonly used with external line driver circuit logic level signals (3.3V, 5V) external signaling levels e.g.) RS-232 / RS-422 / RS-485 / irda (infrared) parallel data parallel data UART logic level serial data external driver external signaling level external driver logic level serial data UART Sender Receiver 5
UART Application UART application block diagram in AT91SAM9260 Driver SW External driver circuit 6
UART Structure UART usually contains the following components Clock generator Input and output shift registers Transmit/receive control Read/write logic Optional buffers Transmit/receive buffers Parallel data bus buffer FIFO buffer memory 7
UART Structure (Example) UART in AT91SAM9260 8
UART I/O Lines Data send/receive Flow control 9
Baud Rate Generator Baud rate is configurable 10
Shift Registers Serial-in / parallel-out Parallel out Serial in Parallel-in / serial-out Parallel in Serial out 11
Error Detection Error caused by noisy medium Parity bit to detect a single bit error more than two bits error cannot be detected Noisy Parity serial cable Parity OK 1 byte generation 1 byte check 01001011 0 01001011 01001011 Error Sender Data bits Parity bit Receiver 12
Error Detection (2) Even parity even number of 1 bits e.g.) 010010110 Odd parity odd number of 1 bits e.g.) 010010111 Sender and receiver must use the same parity type Parity check Check if the number of 1 bits is even / odd e..g) Single bit error in even parity 010110110 number of 1 is odd error! Single bit error 13
RS-232 Series of standards for serial binary single-ended data and control signals connecting between a DTE (Data Terminal Equipment) and a DCE (Data Circuit-terminating Equipment) The current version of the standard is TIA-232-F Interface between DTE and DCE employing serial binary data interchange, issued in 1997 The standard defines electrical characteristics and timing of signals meaning of signals physical size and pin out of connectors 14
RS-232 Example Usage Telex, UNIX workstation terminal, PC modem 15
RS-232 Signal Levels Unbalanced voltage level of a data bit is referenced to local ground Negative voltage levels logic high: -5 to -15V (typically -12V) logic low: +5 to +15V (typically +12V) sending character K = 0x4b = 01001011 16
Connector Types DE-9 1 2 3 4 5 5 4 3 2 1 6 7 8 9 Male connector 9 8 7 6 Female connector 1 13 8 14 25 1 DB-25 RJ-45 17
Pin Connection Signal function 25 pin 9 pin Direction from to Tx Transmitted Data 2 3 DTE DCE Rx Received Data 3 2 DCE DTE RTS Request To Send 4 7 DTE DCE CTS Clear To Send 5 8 DCE DTE DTR Data Terminal Ready 20 4 DTE DCE DSR Data Set Ready 6 6 DCE DTE DCD Data Carrier Detect 8 1 DCE DTE RI Ring Indicator 22 9 DCE DTE FG Frame Ground (chassis) 1 - Common Minimum connection SG Signal Ground 7 5 Common 18
Flow Control (Handshaking) Hardware flow control RTS (Request To Send) transmitter wish to send CTS (Clear To Send) receiver is ready Software flow control (XON / XOFF) Suspend transmission Ctrl-S (0x13) Clear to resume Ctrl-Q (0x11) No handshaking No flow control 3-wire (Tx, Rx, GND) 19
RS-232 Interface Chip (Example) 20
RS-422 Twisted pair / differential pair Use difference between two lines to represent a logic level c.f.) RS-232 is referenced to local ground Common-mode rejection Any noise or interference will affect both wires of the twisted pair but the difference between them will be less affected Termination resistor is required (100 ~ 200Ω) 21
RS-422 Voltage Levels Voltage levels -6V to +6V Voltage difference between an RS-422 twisted pair is between ±4 V and ±12 V between the transmission lines 22
Bidirectional RS-422 Interface 23
RS-485 Master-slave architecture Allows multiple systems (nodes) to exchange data over a single twisted pair 24
RS-485 Connection Receiver Out Receiver Enable Data Enable Data In 25
RS-232 / RS-422 / RS-485 RS-232 RS-422 RS-485 Network topology Point-to-point Multi-dropped Multi-point Maximum devices 1 10 32 ~ 256 Signal reference local ground differential pair differential pair Signal levels logic high -5V to -15V -2V to -6V -7V to +12V logic low +5V to +15V +2V to +6V Maximum distance (m) 25 1500 1200 Baud rate (bps) 75 ~ 115200 100K ~ 10M 100K ~ 10M 26
IrDA Infrared Data Association Optical wireless communication using infrared Device-to-device communication over short distances Characteristics Range: standard: 1 m low power to low power: 0.2 m standard to low power: 0.3 m 10 GigaIR: up to several meters Angle: minimum cone ±15 Speed: 2.4 kbit/s to 1 Gbit/s Modulation: baseband, no carrier Infrared window Wavelength: 850-900 nm 27
IrDA Protocol Stack 28
IrPHY Infrared Physical Layer Specification optical link definitions, modulation, coding, cyclic redundancy check (CRC) and the framer Modulation / coding scheme SIR: 9.6-115.2 kbit/s, asynchronous, RZI, UART-like, 3/16 pulse MIR: 0.576-1.152 Mbit/s, RZI, 1/4 pulse, HDLC bit stuffing FIR: 4 Mbit/s, 4PPM VFIR: 16 Mbit/s, NRZ, HHH(1,13) UFIR: 96 Mbit/s, NRZI, 8B10B GigaIR: 512 Mbit/s 1Gbit/s, NRZI, 2-ASK, 4-ASK, 8B10B 29
IrDA Encoding RZ (Return-to-zero) / RZI (Return-to-zero Inverted) NRZ (Non-return-to-zero) / NRZI (NRZ Inverted) 4PPM (Pulse Position Modulation) 30
Serial Peripheral Interface (SPI) Serial peripheral interface Synchronous serial communication Short distance communication Primarily in embedded system Developed by Motorola in the mid 1980s (de facto standard) Typical applications Secure digital card Liquid crystal displays 31
Master-Slave Architecture Full duplex mode using a master-slave architecture Single master Originates the frame for reading and writing https://en.wikipedia.org/wiki/serial_peripheral_interface_bus 32
Interface Four logic signals Logic signal Description Output from SCLK Serial Clock Master MOSI Master Out Slave In (Data) Master MISO Master In Slave Out (Data) Slave SS Slave Select (often active low) Master Other signal names SCK SDI, DI, DIN, SI SDO, DO, DOUT, SO SSEL, CS, CE, nss, /SS, SS# 33
Operation SS signal selects a slave Single slave SS pin may be fixed to logic low Some slave require of falling edge of SS Multiple slave Independent SS signal is required https://en.wikipedia.org/wiki/serial_peripheral_interface_bus 34
Data Transmission The bus master configures the clock The master selects the slave device with a logic level 0 Waiting period before issuing clock cycles Full duplex data transmission during each clock cycle Master sends a bit on MOSI and slave reads it Slave sends a bit on MISO and master reads it 35
Data Buffers Two shift registers in a virtually ring topology Data is usually sifted out with MSB first On the clock edge Both master and slave shift a bit and output it on transmission line On the next clock edge The bit is sampled from the transmission line The shift registers are reloaded if more data needs to be exchanged https://en.wikipedia.org/wiki/serial_peripheral_interface_bus 36
Clock Polarity and Phase Conventional names CPOL: clock polarity CPOL = 0: clock idles at 0 CPOL = 1: clock idles at 1 CPHA: clock phase CPHA = 0: in side captures data on the leading edge of the clock CPHA = 1: in side captures data on the trailing edge of the clock Mode numbers SPI Mode Clock Polarity (CPOL/CKP) Clock Phase (CPHA) Clock Edge (CKE/NCPHA) 0 0 0 1 1 0 1 0 2 1 0 1 3 1 1 0 37
Clock Polarity and Phase Timing diagram https://en.wikipedia.org/wiki/serial_peripheral_interface_bus 38
Bit-Banging Code example /* * Simultaneously transmit and receive a byte on the SPI. * * Polarity and phase are assumed to be both 0, i.e.: * - input data is captured on rising edge of SCLK. * - output data is propagated on falling edge of SCLK. * * Returns the received byte. */ uint8_t SPI_transfer_byte(uint8_t byte_out) { uint8_t byte_in = 0; uint8_t bit; for (bit = 0x80; bit; bit >>= 1) { /* Shift-out a bit to the MOSI line */ write_mosi((byte_out & bit)? HIGH : LOW); /* Delay for at least the peer's setup time */ delay(spi_sclk_low_time); 39
Bit-Banging Code example /* Pull the clock line high */ write_sclk(high); /* Shift-in a bit from the MISO line */ if (read_miso() == HIGH) byte_in = bit; /* Delay for at least the peer's hold time */ delay(spi_sclk_high_time); } /* Pull the clock line low */ write_sclk(low); } return byte_in; 40
Other Characteristics Interrupts are not covered by the SPI standard MISO pins of the slaves are required to be tri-state 41
Pros and Cons Advantages Full duplex Higher throughput than I2C or SMBus Arbitrary choice of message size Extremely simple hardware interfacing Lower power requirements than I2C or SMBus No arbitration Slaves use master s clock Slaves do not need unique address Transceivers are not needed Uses only four pins on IC packages At most one unique bus signal per device (SS) 42
Pros and Cons Disadvantages No in-band addressing No hardware flow control No hardware slave acknowledgement Only one master device No error checking Only handles short distances Interrupt is not supported 43