Fujitsu SOC 1
Overview Fujitsu SOC The Fujitsu Advantage Fujitsu Solution Platform IPWare Library Example of SOC Engagement Model Methodology and Tools 2
SDRAM Raptor AHB IP Controller Flas h DM A Controller ARC -4 RISC Processor ARC/AHB Bridge IRQ Controller text text text Et hernet MAC AHB BUS Timers AHB Bus AHB Bus ARM RISC Processor AHB Wra pper AHB/APB Br idge APB BUS AHB Bus AHB Ar bi ter Provided by Raptor or other sources SOC Appli cat ions UART SPI/I2C GPIO AHB Decoder The Fujitsu Advantage SOC Best Full-service Company 4. Application Support Design Customization Design Emulation 5. SoC Design implementation D S P E n g in e D S P E n g in e D S P E n g in e ARC/AHB BUS Inteface ARC/AHB BUS Inteface ARC/AHB BUS Inteface GPIO GPIO GPIO GPIO GPIO GPIO Debug Port Debug Port Debug Port Interrupt Interrupt Co-Processor Co-Processor Co-Processor Load XY Cache Store Load XY Cache Store Load XY Cache Store Aux Register Aux Register Aux Register Debug Port Debug Port Debug Port IR Q IR Q ARC-3 RISC ARC-3 Core RISC ARC-3 Core RISC Core SPORT SPORT SPORT BUS In terfac BUS e Unit In terfac BUS e Unit In terfac e Unit DMA PCM PCM PCM Host Bus Host Bus Host Bus Bus Bus Bus Interrupt IR Q DMA V O I P T e s t C h ip V O I P T e s t C h ip V O I P T e s t C h ip DMA JTAG JTAG JTAG JTAG JTAG JTAG Providing the 6 SoC Success Factors 6. Packaging sim 1. Technology synthesis 3. Solution Platform & IP Cores Library API STA DFT P&R 2.. Methodology & Tools 3
The Fujitsu Advantage SOC Key Success Factors for System On Silicon Strong systems development heritage Proving grounds for key IP cores Expertise and presence in growing vertical market segments Leading worldwide provider of standard products Well-equipped SOC LABs System application organization Dominance in key technology components System LSI packaging Semiconductor base technologies technologies Leadership in SOC ASIC IP core differentiation through digital and mixed-signal cores Industry standard I/Os: LVTTL, SSTL, HSTL, LVDS, PCML Gigabit and multi-gigabit serial I/Os Design methodology & tools Proven time to market success 4
Fujitsu Generic Solution Platform Provides efficient designspecific solutions for different products Solution platform is an integrated general sub-system that consists of a processor core, primary and possibly secondary bus architectures and peripherals that are interfaced to the bus IP feature customization Design and interface function blocks Size and power optimization IP core interface to a proprietary bus Solution platforms are designed to be flexible and with clear methodology on how to change, configure and expand them quickly Processor Processor Cores Cores Wrapper(s)/ Bridge(s) Peripheral Peripheral Cache Cache Peripheral Peripheral Primary Bus Secondary Bus Secondary Bridge(s) 5
Fujitsu Flexible Solution Platform CPU ARM7 / ARM9 / ARC 3/4 DMA Engine BUS Bridge AMBA / ARC / Generic Controller SDRAM / EDRAM / FCRAM Peripherals Interface PCI USB Host USB Device UART IEEE 1394 VOIP DSP Ethernet 10/100 MAC Voice Platform (i.e. appliance, gateway) Network IrDA MPEG A/V Decoder MPEG2 Audio/ Video Digital A/V Stream 6
ARM7 Solution Platform Example Unified I/D Cache ARM7 Processor Core Cache (SRAM) Controller ARC (DSP) Core controller s FCRAM EDRAM SDRAM SRAM FLASH DDR USB2.0 Link & PHY PCI BUS AHB bus Bridge AHB-APB Bridge VOIP APB BUS USB1.1 LINK 10/100MAC 802.11a/ b 1394 Link & PHY PCI BUS Bluetoot h ARC-AHB Bridge Advanced High - BUS Performance BUS Advanced High - Performance AHB to PCI Bridge AHB APB Peripheral s UART PCI Peripheral 7
IPWare Library Processors & DSP Networking & Communication Std. Bus Controllers ARM Peripherals Multimedia Access ARC tangent-a4 (+DSP) ARC3 (+ DSP extensions) ARM7TDMI ARM926J-E ARM 946 E-S 256-pt. FFT AMBA ( AHB ) ADK POS-PHY Level 3 POS-PHY Level 4 10/100 MAC 8b/10 Endec OC3 Sonet Framer OC12 Sonet Framer Utopia I/II 10G MAC 1GMAC XAUI ATM25 Framer Hyper Transport Controller USB2.0 Device Controller USB2.0 PHY USB1.1 Device Controller USB1.0 Host Controller PCI (2.1) Controller 33 MHZ PCI (2.1) Controller 66 MHZ PCIX 1394 Link Layer 400 Mbps 1394 PHY 400 Mbps PCI Host Controller Address decoder Bus Arbiter Data MUX (Master->Slave) Data MUX )Slave-> Master) External Bus Interface Internal Interface(4K) Default slave (for dummy fetch) AHB Master Dummy VoiP core (4-channel) AC97 controller JPEG MJPEG Video encoder Bluetooth 802.11a 802.11b Wireless Bus Bridges Controllers Other Peripherals PCI-AHB Bridge ARC-AHB Bridge ARM-AHB Bridge AHB-APB Bridge ARM7 Cache Controller ARM7 EDRAM Controller ARM9 Cache Controller FCRAM Controller SDRAM Controller ARM7 SRAM Controller stick controller DDR controller DMA Controller (8 Ch) UART Interrupt Controller Remap and Pause Controller I 2 C PCMCIA 8
SOC ASIC Engagement Model Development partnership Technology Partner (FMA) System Partner (customer) Libraries IP cores SIM models Technology Deliverables IP development & support SOC solution platform support Design application support Design implementation support (FE/BE) System LSI SOC IP-ASIC Final Product Requirement Specifications System integration Chip specifications System integration System S/W, F/W.. 9
Methodology and Tools Methodology enables the integration and transformation of technologies into products System architecture and application expertise, portable & reusable IP cores and methodologies are the key cornerstones of system LSI differentiation FMA puts the puzzle together! Technology Tools Methodology IP Cores System Expertise 10
System-centric Design Methodology Definition DFT Functionality Design Verification Timing Implementation HW/SW Partitioning IPWare Digital Custom Design Analog;, RF. IPWare Customer Specifications Arch. Anal. RTL Des. Behav. Des. RTL Syn. Behav. Syn.. Place & Route Parasitic Extraction IPWare IPWare Floor Planning BE, FAB & Sample Build Des. Data Verif. Fabrication Tape-out Layout Verif. 11
System-centric Design Methodology Top-down and integrated design methodology Ensures predictable design through close correlation between all levels of abstraction Achieves fast time to market by reducing the design cycle time 12