Adaptive Voltage Scaling (AVS) Alex Vainberg October 13, 2010

Transcription

1 Adaptive Voltage Scaling (AVS) Alex Vainberg October 13, 2010

2 Agenda AVS Introduction, Technology and Architecture Design Implementation Hardware Performance Monitors Overview AVS Design & Test Flow 2

3 Agenda AVS Introduction, Technology and Architecture Design Implementation Hardware Performance Monitors Overview AVS Design & Test Flow 3

4 Traditional Power Management Delivery Digital Processor/ASIC V FIXED Voltage Regulator V IN Digital Logic Fixed Voltage = Inefficient System!!! No temperature compensation No adjustment for lower voltages at lower frequencies No compensating for process variation 4

5 PowerWise Adaptive Voltage Scaling (AVS) Digital Processor/ASIC V AVS V IN Digital Logic Advanced Power Controller (APC) PWI Energy Management Unit (EMU) Hardware Performance Monitor () 2 E = ( α C f V + V I ) t CLK LEAK DYNAMIC LEAKAGE TASK Adaptive Voltage Scaling = Maximum power savings Process and Temperature Compensation No need for frequency-voltage lookup tables Real-time continuous closed-up PWI = PowerWise Interface 5

6 Operating Vdd Range Device Performance Distribution Process Variation Slow Typical Fast Published (Fixed) VDDV -All silicon guaranteed to function -Timing models for PTV corners at F 1.2V 1.32V 1.08V All units will work over full PTV range 6

7 Optimizing Power Efficiency Process Variation Slow Typical Fast Published (Fixed) VDDV -All silicon guaranteed to function -Timing models for PTV corners at F 1.2V 1.32V 1.08V 1.00V Most units expected to work over extended V range 7

8 Optimizing Power Efficiency Process Variation Slow Typical Fast Published (Fixed) VDDV -All silicon guaranteed to function -Timing models for PTV corners at F 1.2V 1.32V 1.08V _V Fast units expected to work over greatly extended V range 8

9 AVS Optimizing Power / Full Range 1.2V 1.32V 1.08V Published (Fixed) VDDV - All silicon guaranteed to function - Timing models for PTV corners at F 0.9V AVS_Vdd for Lowest Power -Power controller maintains Vdd to lowest level possible based on on-chip PTV performance measurement - Slow silicon possible lower Vdd based on slack timing 0.85V Clamp Minimum VDDV - Independent clamp level for minimum Vdd set with power controller - Overrides monitor request to go to a lower Vdd 9

10 Process Variability Comparison P T V 10

11 Agenda AVS Introduction, Technology and Architecture Design Implementation Hardware Performance Monitors Overview AVS Design & Test Flow 11

12 AVS Results on 130nm C u m u la t iv e E n e r g y ( u s in g IE M ) Fixed-Vdd Fixed-Vdd DVS AVS Relative Energy DVS AVS F IX E D D V S A V S Energy T im e (s e c o n d s ) ARM926EJ-S core Voltage and frequency scaling of CPU, Caches Four performance points: 60, 120, 180, 240 MHz 0.7V 1.2V Adaptive Voltage Range Dual ARM7 CPU cores Voltage and frequency scaling of ARM7 Performance points: 96, 84, 72, 60, 12 MHz 0.7V 1.2V Adaptive Voltage Range 12

13 Measured AVS Power Savings % Power (mw) % 38.0% 30.4% 27.3% 32.5% 35.7% 38.9% 32.9% 40.5% 40.0% 35.0% 30.0% 27.8% 25.0% 20.0% Energy Savings Fixed Power (mw) AVS Power (mw) AVS Energy Savings % 10.0% % Samples (Units) 0.0% TA=25C Custom ASIC/SoC SoC design process 65nm, freq. greater than 750Mhz AVS reduced core power by 27 to 40% at maximum frequency 13

14 Power Saving and Thermal Performance, 65nm process With AVS Without AVS MTBF doubles with reduction of 10 C 14

15 TN2020 & NSC power solution 15

16 Measurements TN20xx Board 29 Temp AVS OFF AVS ON Measured Power Savings deg C mv mv (c. sns.) A Power W mv mv (c. sns.) A Power W % % % % Board 30 Temp AVS OFF AVS ON Measured Power Savings deg C mv mv (c. sns.) A Power W mv mv (c. sns.) A Power W % % % % 16

17 AVS System Impact System Performance Once enabled AVS runs in background No processing overhead Energy Savings Scaled Voltage Domain Savings vary depending on process geometry, design implementation, and frequency scaling profile Expected energy savings for typical silicon will be 20-50% based on process and temperature variations System Risk Mitigation AVS is an additional function in the ASIC/Processor and the power conversion device AVS compliant ASIC/Processor and power conversion devices can still operate at fixed voltage or DVS without any design changes 17

18 Agenda AVS Introduction, Technology and Architecture Design Implementation Hardware Performance Monitors Overview AVS Design & Test Flow 18

19 Overview is Embedded in the voltage domain that is AVS controlled translates the voltage level into silicon performance information generated silicon performance information is a function of voltage level and clock APC makes use of silicon performance information to determine the optimum voltage level for the required target performance Structurally coded synthesizable RTL to facilitate ease of layout P&R for optimizing silicon performance tracking accuracy 19

20 and Critical Path Monitoring D Q Critical Path D Q Critical path timing is correlated to performance monitoring by setting the Reference Performance Code (RCC) Application Clock Period (Critical Path Delay < this) 0 31 Performance Code Passing Performance Failure Point RCC (selectable) Control Margin 20

21 Performance Code and APC Voltage Control Reference Calibration Code delay line propagation delay line propagation delay line propagation Pre-delay 0 15 Main-delay 31 PC > RCC performance > requirement adjust voltage level lower PC = RCC performance = requirement no voltage adjustment RCC settings reside in APC PC is compared to RCC in APC Voltage adjustment initiated by APC PC < RCC performance < requirement adjust voltage level higher 21

22 Agenda AVS Introduction, Technology and Architecture Design Implementation Hardware Performance Monitors Overview AVS Design & Test Flow 22

23 APC2 IP SoC View Clock Domain 1 (1-4) AVS Power Domain 1 Clock Domain 2 (1-4) MUX Control loop Registers Clock Domain 3 (1-4) Clock Domain 4 (1-4) (1-4) Up to 4 AVS domains 1-4 per scalable clocks per AVS domain 1-4 per clock domain APC2 PWI2.0 interface master Up to 4 AVS domains Enhanced control-system Adaptive Voltage Scaling closed-loop control based on performance measurement data sampled by Open-loop voltage scaling via voltage register table 8 performance levels + retention level Control registers programmed via AMBA-APB interface Auto PL0 back-bias Trace port for debug _CLKS Clock Management APB I/F AMBA-APB DPRAM Arbiter PWI 2.0 master (dual master) PWI 2.0 SoC 23

24 AVS Design Flow Power-aware ASIC Design Flow Adding the AVS Architecture Specification Functional specification Power management strategy Power domain partitioning IP selection No. of independent AVS power domains Frequency scaling no. of performance levels No. of clock domains in each AVS power domain No. of for performance tracking PowerWise Interface pins IP selection low voltage std cells and memories APC/ Configurations RTL Design RTL implementation Power domains Clock management with performance level interface Integrate APC and s Synchronizers at power domain boundary Functional Simulation Functional verification Power domains APC/ connectivity APC programming AVS modeling Logic Synthesis and DFT Gate implementation Timing/power/area optimization SCAN chains Power domains synthesis SCAN chain stitching Physical Design Power domains Power gating Level shifters and isolation cells Timing/power/area optimization layout placement in ASIC Sign-off Verification Equivalency Timing Power AVS timing verification timing verification 24

25 AVS Production Flow Typical ASIC Production Flow AVS ASIC Production Flow DC/AC Characterization One time effort Over process and temperature corners DC/AC + AVS Characterization Determine AVS minimum VDD Correlate ASIC performance/voltage requirements to SCAN and Functional Test Manufacturing test SCAN and Functional Test Include APC and in the testing + Low voltage SCAN and Functional Test Repeat regular testing at low voltage and low speed Check performance code and / or and Emulated AVS Test Check performance code vs. voltage scaling trend Identify AVS voltage level and test functional at speed 25

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