Stratix. High-Density, High-Performance FPGAs. Available in Production Quantities

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1 Stratix High-Density, High-Performance FPGAs Available in Production Quantities February 2004

2 High-Density, High-Performance FPGAs Altera s award-winning Stratix FPGA family delivers the most comprehensive set of capabilities available from any FPGA vendor. Stratix FPGAs share common, leading-edge architecture elements with the Stratix II, Stratix GX, and HardCopy Stratix device families and enable customers to build for a wide variety of highdensity, high-performance applications. The density of Stratix devices ranges from 10,570 to 79,040 logic elements (LEs) with up to 7 Mbits of embedded RAM and x 18 multipliers. Stratix devices have up to 12 phase-locked loops (PLLs), 40 system clocks, and support for many single-ended and differential I/O electrical standards. The new Stratix II FPGAs extend all of these capabilities for even greater capacity and performance. The Stratix family, like all Altera device families, is supported by an incredibly powerful suite of software tools, intellectual property (IP) libraries, and development systems. The Altera Quartus II software tools provide integrated design capture, simulation, logic synthesis, and place-and-route capabilities. With the Quartus II software, Altera customers can work in one integrated tool environment and target all the Altera devices from MAX CPLDs through Stratix II FPGAs. Altera IP cores are parameterized and optimized for a variety of applications ranging from memory interfaces to the Nios embedded processor. The Nios embedded processor is the fastest growing processor architecture for use in FPGAs and is supported by development tools that are tightly integrated into the Quartus II software and Altera s development kits. Altera s inexpensive development kits include development boards, a full suite of tools, and trial IP so users can be up and running in minutes. Shipping in volume now, the Stratix family is the first programmable logic device (PLD) family designed to enable a comprehensive block-based design methodology. For the first time, in conjunction with the Quartus II design software, designers can optimize and lock the performance of individual design blocks even when blocks are moved or integrated with other optimized functions. By eliminating the time-consuming process of performance re-optimization during system integration, Stratix FPGAs significantly enhance the time-to-market advantages of high-density programmable logic. In fact, Stratix devices deliver on average a 50% and as high as 100% improvement in push-button performance over previous architectures. Stratix FPGAs are based on a 1.5-V, 0.13-µm, all-layer-copper SRAM process. The Stratix TriMatrix memory structure, with three sizes of memory blocks, is optimized for highmemory bandwidth and large memory storage requirements. For digital signal processing (DSP) applications, Stratix devices include up to x 18 multiplier blocks that eliminate performance bottlenecks in arithmetic applications. The multipliers are implemented as part of Altera s DSP block, an optimized silicon core comprised of multiply and accumulate circuitry that provides predictable performance and significant resource savings for complex applications requiring high data throughput. Table 1 highlights features and benefits of the Stratix devices, and Table 2 shows the wide range of features and packages available. Table 1. Stratix Highlights Feature High-Performance Architecture TriMatrix Memory DSP Blocks High-Bandwidth I/O Standards and High-Speed Interfaces Clock Management Circuitry Remote System Upgrades Cost Reduction Migration Path Benefit Routing structure provides the basis for block-based design methodology for maximum system performance with minimum development time Three sizes of embedded memory blocks with up to 7 Mbits of RAM, up to 8 terabits per second of memory bandwidth, and data transfer rates of over 250 MHz Predictable 333-MHz performance for data throughput of up to 2.7 GMACS per DSP block Support for high-speed I/O standards and high-speed interfaces such as 10-Gigabit Ethernet (XSBI), SFI-4, POS-PHY Level 4, HyperTransport, RapidIO, and UTOPIA Level 4 interfaces at up to 840 Mbps, as well as support for advanced external memory device interfaces Up to 12 PLLs and up to 40 system clocks with features such as clock switchover, PLL reconfiguration, spreadspectrum clocking, frequency synthesis, and programmable phase and delay shift Real-time updates to PLDs from remote locations Cost-reduction migration path to HardCopy devices supported for high-density Stratix devices 2 Altera Corporation

3 Table 2. Stratix Family Overview Feature EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S0 EP1S80 LEs 10,570 18,40 25,0 32,470 41,250 57,120 79,040 M512 RAM Blocks (512 bits + parity) M4K RAM Blocks (4 Kbits + parity) M-RAM Blocks (512 Kbits + parity) Total RAM Bits 920,448 1,9,248 1,944,57 3,317,184 3,423,744 5,215,104 7,427,520 DSP Blocks Embedded Multipliers (1) PLLs Maximum User I/O Pins ,022 1,238 Available Packages 72-Pin Ball- Grid Array (BGA) 484-Pin 72-Pin 780-Pin 72-Pin BGA 484-Pin 72-Pin 780-Pin 72-Pin BGA 72-Pin 780-Pin 1,020-Pin 95-Pin BGA 780-Pin 1,020-Pin 95-Pin BGA 1,020-Pin 1,508-Pin 95-Pin BGA 1,020-Pin 1,508-Pin 95-Pin BGA 1,508-Pin Note: (1) Total number of embedded 9x9 multipliers. To obtain the total number of 18x18 multipliers per device, divide the total number of 9x9 multipliers by 2. To obtain the total number of 3x3 multipliers per device, divide the total number of 9x9 multipliers by 8. High-Bandwidth Solution The Stratix device family was specifically designed to address the increasing bandwidth requirements of highspeed systems. All aspects of bandwidth are increased: overall memory bandwidth, arithmetic bandwidth for DSP applications, I/O bandwidth, and core performance. Built on the performance-optimized and highly flexible MultiTrack continuous routing structure, Stratix devices offer dramatically higher core performance than any previous architecture. Combined with embedded features such as TriMatrix memory, DSP blocks, and dedicated high-speed I/O interfaces, Stratix devices deliver the best possible system integration to meet the requirements of high-bandwidth systems. TriMatrix Memory Stratix devices feature the TriMatrix memory structure, made up of three sizes of embedded RAM blocks. TriMatrix memory includes the 512-bit M512 blocks, the 4-Kbit M4K blocks, and the 512-Kbit M-RAM blocks, each of which can be configured to support a wide range of features. Each embedded RAM block in the TriMatrix memory structure targets a different class of applications: the M512 blocks can Figure 1. TriMatrix Memory Structure M512 Blocks 512 bits per block Up to 1,118 blocks More Bits for Larger Memory Buffering More Data Ports for Greater Memory Bandwidth Rake receiver correlator Shift register Small FIFO buffers Finite impulse response (FIR) filter delay line M4K Blocks 4 Kbits per block Up to 520 blocks Applications ATM cell packet processing Header/cell storage Channelized functions Program memory for processors M-RAM Blocks 512 Kbits per block Up to 12 blocks IP packet buffering System cache Video frame buffers Echo canceller data storage Processor code storage Altera Corporation 3

4 be used for small functions such as first-in first-out (FIFO) applications; the M4K blocks can be used to store incoming data from multi-channel I/O protocols, and the M-RAM blocks can be used for storage-intensive applications such as Internet protocol packet buffering or as program/data memory for an on-chip Nios embedded processor. All memory blocks include extra parity bits for error control, embedded shift register functionality, mixed-width mode, and mixed-clock mode support. Additionally, the M4K and M-RAM blocks support true dual-port mode and byte masking for advanced write operations. With up to 7 Mbits of RAM and up to 8 terabits per second of device memory bandwidth, the TriMatrix memory structure, shown in Figure 1, makes the Stratix family an ideal choice for memory-intensive applications. Figure 2. DSP Block Architecture Optional Input Registers Optional Pipeline Registers Summation Unit Optional Output Registers DSP Blocks The programmable DSP blocks in Stratix devices are highperformance embedded arithmetic units optimized for applications such as rake receivers, voice over Internet protocol (VoIP) gateways, orthogonal frequency division multiplexing (OFDM) transceivers, image processing applications, and multimedia entertainment systems. Flexible, efficient, and valuable for a variety of applications that require high data throughput, Stratix DSP blocks can implement a variety of typical DSP functions, such as finite impulse response (FIR) filters, fast Fourier transform (FFT) functions, correlators, and encryption/decryption functions, and are ideal for the wireless communication, telecommunication, video, and image processing markets. The DSP blocks eliminate performance bottlenecks in complex arithmetic applications, provide predictable and reliable performance, and save resources without compromising performance. This makes Stratix DSP blocks ideal for implementing computationally complex systems while providing high data throughput at the same time. Stratix DSP blocks consist of hardware multipliers, adders, subtractors, accumulators, and pipeline registers. Because the Stratix DSP blocks are implemented with dedicated circuitry, as shown in Figure 2, they offer designers optimal performance. DSP blocks in Stratix devices can run at 333 MHz to provide data throughput performance of up to 2.7 GMACS per DSP block. With up to 22 DSP blocks, Stratix devices can provide a combined throughput that is more than 10 times the data throughput available from leading digital signal processors today. Table 3 highlights the features of Stratix DSP blocks. Multiplier Table 3. DSP Block Features Programmable Element Multiplier Adder/Subtractor/ Accumulator Summation Unit Complex Shift Function Adder/Subtractor/ Accumulator Benefit 9x9, 18x18, and 3x3 multiplication Floating-point arithmetic Signed and unsigned operation Full precision in all modes Optional shift register chain on inputs Dynamic switching between adder and subtractor 9-bit, 18-bit, or 3-bit operation for adder and subtractor 52-bit accumulator Signed and unsigned operation Summation of up to four products in one clock cycle Barrel shifter, cross-bar switch, and encryption High-Bandwidth I/O Standards & High-Speed Interfaces Stratix devices support a variety of single-ended and differential I/O standards to interface easily with backplanes, host processors, buses, memory devices, and 3D graphics controllers. Stratix devices offer designers access to up to 4 Altera Corporation

5 Table 4. Stratix I/O Standard & Interface Support Feature Electrical Standards Dedicated Circuitry Related Altera Intellectual Property (IP) Cores & Reference Designs Single-Ended I/O Standards LVTTL, LVCMOS, SSTL, HSTL, PCI-X, CTT, AGP, GTL+ On-chip termination PCI compliant PCI-X 32-/4-Bit PCI CSIX Direct memory access (DMA) controller Universal serial bus (USB) controller Differential I/O Standards LVDS, LVPECL, HyperTransport, PCML True-LVDS circuitry Dedicated SERDES circuitry Differential I/O buffers Data realignment POS-PHY Level 4 UTOPIA Level 4 Flexbus Level 4 HyperTransport RapidIO External Memory Interfaces SSTL-2, SSTL-3, SSTL-18, HSTL Class I & II, Differential SSTL, Differential HSTL Dedicated DDR circuitry Dedicated DQS circuit DDR timing circuit Dedicated I/O registers DDR SDRAM controller Single data rate (SDR) SDRAM controller DDR FCRAM controller Quad data rate (QDR) SRAM controller ZBT RAM controller 152 high-speed differential I/O channels. Each of these I/O channels includes dedicated serializer/deserializer (SERDES) circuitry for high-speed interface standards as shown in Table 4. This support for high-speed I/O interfaces and highbandwidth protocols makes Stratix devices an ideal solution for complete system integration. Differential I/O Standard Support Stratix devices offer the True-LVDS circuitry to support the LVDS, LVPECL, PCML, and HyperTransport differential I/O standards as well as differential HSTL and SSTL. The Stratix device family has up to 13 high-speed input and 152 output differential I/O channels with up to 80 channels optimized for 840-Mbps operation. Single-Ended I/O Standard Support To interface with other devices on a board, Stratix devices support single-ended I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, GTL, GTL+, PCI-X, AGP, and CTT. Devices using single-ended I/O standards provide more current drive capacity than differential I/O standards, and they are necessary when working with advanced memory devices such as double data rate (DDR) SDRAM and zero-bus turnaround (ZBT) SRAM devices. High-Speed Interface Support Altera continues its industry-leading high-speed differential I/O interface support with Stratix devices. Stratix devices support a wide array of high-speed interface standards, including the 10-Gigabit Ethernet (XSBI), SFI-4, POS-PHY Level 4 (SPI-4 Phase 2), HyperTransport, RapidIO, and Figure 3. Stratix On-Board High-Speed Interface Support ASSP Network Processing XSBI, SFI-4, UTOPIA IV POS-PHY L4 To Host Processor RapidIO, HyperTransport Backplane Table 5. Stratix External Memory Interface Sup port External Memory Device SDR SDRAM DDR SDRAM DDR FCRAM ZBT SRAM QDR SRAM QDRII SRAM Maximum Data Transfer Rate 200 Mbps 400 Mbps 400 Mbps 200 Mbps 8 Mbps 8 Mbps To Backplane UTOPIA IV standards. Designers can use Altera intellectual property (IP) cores to bridge between high-speed interfaces through the Atlantic interface. In addition, Stratix devices can support up to four high-bandwidth interfaces in one device for an ideal bridging solution, as shown in Figure 3. Memory Clock Spe ed 200 MHz 200 MHz 200 MHz 200 MHz 17 MHz 17 MHz Altera Corporation 5

High-Speed External Memory Interface Support In addition to the on-chip TriMatrix memory, Stratix devices address increasing memory bandwidth requirements by providing customers the capability to

6 High-Speed External Memory Interface Support In addition to the on-chip TriMatrix memory, Stratix devices address increasing memory bandwidth requirements by providing customers the capability to interface with additional off-chip data storage that supports external memory interfaces. Designers can easily connect Stratix devices to a wide range of the latest SRAM and DRAM memory devices from leading vendors. Using Stratix device features and customizable IP, designers can integrate high-density memory devices into complex system designs without reducing data access performance or increasing development time. Stratix devices address a wide variety of cutting-edge memory interfaces, as summarized in Table 5. Figure 4. Stratix Clock Management Circuitry High-Performance Architecture Built on an innovative architecture, the Stratix devices allow designers to take advantage of the performance capabilities of dedicated silicon blocks while preserving overall design flexibility. This architecture gives designers the solution they need to reach design performance and bandwidth targets. Stratix Architectural Advances The Stratix device family is based on an architecture that was built from the ground up to power complex designs to new levels of system integration. In concert with the LogicLock design methodology, Stratix devices simplify the difficult process of design integration, providing the basis upon which block-based designs can be developed and optimized for maximum performance. This high-performance architecture is based on the MultiTrack interconnect with DirectDrive technology. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths used for inter- and intra-design block connectivity. DirectDrive technology is a proprietary, deterministic routing technology that ensures identical routing resource usage for any function, regardless of its placement within the device. These two architectural advances simplify the system integration stage of block-based design by eliminating the time-consuming system re-optimization cycles that typically follow design changes and additions. for system-level clocking management previously found only in high-end discrete PLL devices. Stratix devices offer two types of PLLs: enhanced PLLs that support advanced features such as external feedback, clock switchover, PLL reconfiguration, spread-spectrum clocking, and programmable bandwidth; and fast PLLs that are optimized for high-speed differential I/O interfaces and can be used for general-purpose clocking. Figure 4 illustrates the features of Stratix PLLs. On-Chip Termination Technology Stratix devices include on-chip termination resistor technology that supports on-chip serial and differential termination and driver impedance matching. Driver impedance matching is essential for reducing reflections and improving signal integrity (as shown in Figure 5) for maximum system performance. Stratix on-chip termination also reduces board space usage and simplifies board layout by minimizing the Figure 5. Termination Clock Management Circuitry With up to 12 PLLs and up to 40 system clocks per device, Stratix devices are built to function as the central clock manager to meet your system timing challenges. These devices are the first PLDs to offer the on-chip PLL features Signal Reflection Without Termination Improved Signal Integrity On-Chip Termination Altera Corporation

7 number of external resistors required on the PCB when compared to other termination techniques, as Figure illustrates. To provide constant calibration of the internal resistor values, Altera termination technology utilizes two external precision resistors per I/O bank and monitors the value of these resistors. The termination resistors can then compensate for process, temperature, and voltage variations. Remote System Upgrades While using PLDs gets your designs to market faster, using the remote system upgrade capability in Stratix devices can keep your products on technology s cutting edge. Remote system upgrades can be transmitted through any communications network to keep your designs ahead of the competition. Stratix devices provide both enhanced design flexibility and an extended life cycle, as shown in Figure. Figure. Remote System Upgrade Benefits Revenue Get to Market Faster PLD-Based System Remote-Upgrade-Enabled System ASIC-Based System Time Altera SOPC Solutions Stay in Market Longer Expanded Life Cycle Stratix devices bring high levels of system integration for system-on-a-programmable-chip (SOPC) designs. Altera offers a set of solutions for creating complete systems on Stratix devices, including the Quartus II design software, optimized IP, the Nios embedded processor, and customer training. Design Software Technology Leadership Altera s powerful yet easy-to-use Quartus II software now features unique advantages in design flow methodology support, system design, IP integration and evaluation, placeand-route technology, timing closure methodology, in-system verification technology, and third-party EDA support. The Quartus II software provides the most comprehensive environment available for FPGA, CPLD, and HardCopy structured ASIC designs. The Quartus II software technology leadership delivers designers unmatched performance, efficiency, and ease-of-use for high-density FPGA designs. For more details on Quartus II software, please refer to Intellectual Property Altera and Altera Megafunction Partners Program (AMPP SM ) partners offer over 0 off-the-shelf IP megafunctions optimized for Altera Stratix devices. Designers can easily implement these parameterized blocks of IP, reducing design and test time. Megafunctions provide total solutions by targeting specific application areas, providing optimized performance and system reusability, and significantly reducing a product s time-to-market. Nios Embedded Processor Solutions Nios embedded processors allow designers to integrate embedded processors on Stratix devices for complete SOPC designs. The Nios soft embedded processor has been optimized for the advanced architectural features of the Stratix device family to deliver increased performance and capabilities. With the Altera SOPC Builder, designers can select from the wide array of IP components, customize them for the particular application, and connect them automatically generating hardware, software, and simulation models for their custom implementation. Stratix devices and the Nios embedded processor solutions simplify the design process and accelerate time-to-market. Customer Training For customers interested in learning more about designing quickly and efficiently with Stratix devices, Altera has launched a unique instructor-led modular training series. This Stratix device-specific series consists of individual training modules that can be arranged to create custom courses tailored to customer needs and based on their existing experience. Altera also offers three one-day courses that cover all modules. Contact Altera Today The Stratix device family provides the ideal solution for your high-bandwidth, high-performance design needs. Visit the Altera web site today to learn more about the Stratix device family and its high bandwidth solutions at Altera Corporation 7

8 The Programmable Solutions Company Altera Offices Altera Corporation 101 Innovation Drive San Jose, CA USA Telephone: (408) Altera European Headquarters Holmers Farm Way High Wycombe Buckinghamshire HP12 4XF United Kingdom Telephone: (44) Altera Japan Ltd. Shinjuku i-land Tower 32F -5-1, Nishi-Shinjuku Shinjuku-ku, Tokyo Japan Telephone: (81) Altera International Ltd Tower The Gateway, Harbour City 9 Canton Road Tsimshatsui Kowloon Hong Kong Telephone: (852) Copyright 2004 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other trademarks are the property of their respective owners and may be registered in certain jurisdictions. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights. GB-STRATIX-3.0

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