ZSPM4121. Under-Voltage Load Switch for Smart Battery Management. Datasheet. Brief Description. Features. Related IDT Smart Power Products

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Under-Voltage Load Switch for Smart Battery Management ZSPM4121 Datasheet Brief Description The ZSPM4121 battery management load switch can be used to protect a battery from excessive discharge. It actively monitors the battery voltage and disconnects the battery from the load if the battery drops below a set voltage threshold. When the input battery voltage reaches 500mV above the set voltage threshold, the load switch turns on and connects the battery to the load. The 500mV hysteresis between the Off Mode and the On Mode prevents intermittent operation. The voltage threshold (V THRESH ) can be programmed at manufacturing to a customer-selected set point in the voltage range of 1.2V to 4.2V in 100mV increments to support a wide range of applications in consumer, medical, portable, and industrial applications. This device has ultra-low quiescent current, which makes it ideal for battery-powered applications. Typical quiescent current is 100pA in the Off Mode and 70nA in the On Mode. The ZSPM4121 includes a slew rate control P-channel load switch, over-current protection, and an open-drain power indicator pin (NPG). The slew-rate controlled turn-on characteristic prevents inrush current and voltage droop on the voltage. The overcurrent limit protects the device in case of an overload, short-circuit, or ground fault event. Features Threshold voltage options of 1.2V to 4.2V in 100mV steps (factory programmed) Wide input voltage range: 1.2V to 5.5V Supervisory over-current limit shutdown: (3A) Low drop-out disconnect from VCC to loads Controlled turn-on slew rate 500mV Off Mode to On Mode hysteresis Related IDT Smart Power Products ZSPM4141 Ultra-Low-Power Linear Regulator Available Support Evaluation Kit Support Documentation Physical Characteristics Package: 8-pin DFN (2mm x 2mm) ZSPM4121 Block Diagram Benefits Best-in-class ultra-low quiescent current in Off Mode: 100pA (typical) Ultra-low quiescent current in On Mode: 70nA (typical) Accurate on/off voltage threshold Low Rds(on): 175mΩ (typical) @ 5V VCC ZSPM4121 Regulated V THRESH VOUT NPG GND 2016 Integrated Device Technology, Inc. 1 January 29, 2016

Under-Voltage Load Switch for Smart Battery Management ZSPM4121 Datasheet Typical Application Circuit Charger ZSPM4121 VCC VOUT Load Typical Applications GND NPG Portable batteries Industrial Medical Smart cards RFID Ordering Information Ordering Code* Description Package ZSPM4121AI1W17 ZSPM4121 Under-Voltage Load Switch V THRESH factory set to 1.7V 8-pin DFN / 7 Reel (2500) ZSPM4121AI1W21 ZSPM4121 Under-Voltage Load Switch V THRESH factory set to 2.1V 8-pin DFN / 7 Reel (2500) ZSPM4121AI1W23 ZSPM4121 Under-Voltage Load Switch V THRESH factory set to 2.3V 8-pin DFN / 7 Reel (2500) ZSPM4121AI1W24 ZSPM4121 Under-Voltage Load Switch V THRESH factory set to 2.4V 8-pin DFN / 7 Reel (2500) ZSPM4121AI1W25 ZSPM4121 Under-Voltage Load Switch V THRESH factory set to 2.5V 8-pin DFN / 7 Reel (2500) ZSPM4121AI1W26 ZSPM4121 Under-Voltage Load Switch V THRESH factory set to 2.6V 8-pin DFN / 7 Reel (2500) ZSPM4121AI1W28 ZSPM4121 Under-Voltage Load Switch V THRESH factory set to 2.8V 8-pin DFN / 7 Reel (2500) ZSPM4121AI1W30 ZSPM4121 Under-Voltage Load Switch V THRESH factory set to 3.0V 8-pin DFN / 7 Reel (2500) ZSPM4121KIT ZSPM4121 Evaluation Kit * For a 13 reel (3300 parts), replace the W in the ordering code with an R. Custom V THRESH values are also available: 1.2V to 4.2V (typical) in 100mV increments. Corporate Headquarters 6024 Silver Creek Valley Road San Jose, CA 95138 www.idt.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.idt.com/go/sales Tech Support www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of Integrated Device Technology, Inc. All rights reserved. 2016 Integrated Device Technology, Inc. 2 January 29, 2016

Contents 1 ZSPM4121 Characteristics... 5 1.1. Absolute Maximum Ratings... 5 1.2. Thermal Characteristics... 5 1.3. Recommended Operating Conditions... 5 1.4. Electrical Characteristics... 6 2 Typical Performance Characteristics... 7 3 Description of Circuit... 8 4 Application Circuit... 9 4.1. Typical Application Circuit... 9 5 Pin Configuration and Package... 10 5.1. Package Dimensions and Marking Diagram... 10 5.2. Pin Description for 8-Pin DFN (2x2 mm)... 11 6 Layout and Soldering Requirements... 12 6.1. Recommended Landing Pattern for PCBs... 12 6.2. Multi-Layer PCB Layout... 13 6.3. Single-Layer PCB Layout... 14 7 Ordering Information... 15 8 Related Documents... 15 9 Glossary... 16 10 Document Revision History... 16 List of Figures Figure 2.1 On Mode / Off Mode Characteristics... 7 Figure 2.2 On Mode Switching Behavior... 7 Figure 2.3 On Mode / Off Mode Quiescent Current I q... 7 Figure 2.4 Off Mode V THRESH Temperature Performance... 7 Figure 2.5 On Mode / Off Mode Transition Delay... 8 Figure 2.6 Over-Current Retry Performance... 8 Figure 3.1 ZSPM4121 Block Diagram... 8 Figure 4.1 Application Circuit for Disconnecting the Load... 9 Figure 5.1 ZSPM4121 Package Drawing... 10 Figure 5.2 ZSPM4121 Pin Assignments (top view)... 11 Figure 6.1 Recommended Landing Pattern for 8-Pin DFN... 12 Figure 6.2 Package and PCB Land Configuration for Multi-Layer PCB... 13 Figure 6.3 JEDEC Standard FR4 Multi-Layer Board Cross-Sectional View... 13 Figure 6.4 Conducting Heat Away from the Die using an Exposed Pad Package... 14 Figure 6.5 Application Using a Single-Layer PCB... 14 2016 Integrated Device Technology, Inc. 3 January 29, 2016

List of Tables Table 1.1 Absolute Maximum Ratings... 5 Table 1.2 Thermal Characteristics for 8-Pin DFN (2mm x 2mm) Package... 5 Table 1.3 Recommended Operating Conditions... 5 Table 1.4 Electrical Characteristics... 6 Table 5.1 Pin Description, 8-Pin DFN (2x2)... 11 2016 Integrated Device Technology, Inc. 4 January 29, 2016

1 ZSPM4121 Characteristics Stresses beyond those listed under Absolute Maximum Ratings (section 1.1) may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those recommended under Recommended Operating Conditions (section 1.3) is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability. 1.1. Absolute Maximum Ratings Over operating free air temperature range unless otherwise noted. All voltage values are with respect to network ground terminal. Table 1.1 Absolute Maximum Ratings Parameter Symbol Value Unit Maximum voltage applied to the VCC, VOUT,and NPG pins -0.3 to 6.0 V Electrostatic Discharge Human Body Model, according to the respective JESD22 JEDEC standard Electrostatic Discharge Charged Device Model, according to the respective JESD22-C101 JEDEC standard 2 kv 500 V Operating Junction Temperature Range T J -20 to 85 C Storage Temperature Range T stg -65 to 150 C Lead Temperature (soldering, 10 seconds) 260 C 1.2. Thermal Characteristics Table 1.2 Thermal Characteristics for 8-Pin DFN (2mm x 2mm) Package θ JA ( C/W) 1) θ JC ( C/W) 2) 73.1 10.7 1) This rating assumes a FR4 board only. 2) This rating assumes a 1oz. copper JEDEC standard board with thermal vias. See section 6.1 for more information. 1.3. Recommended Operating Conditions Table 1.3 Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Unregulated Supply Input at VCC Pin V CC 1.2 5.5 V Operating Ambient Temperature 1) T A -20 55 C Operating Junction Temperature T J -20 85 C 1) Operating ambient temperature is only intended as a guideline. The operating junction temperature requirements must not be exceeded. 2016 Integrated Device Technology, Inc. 5 January 29, 2016

1.4. Electrical Characteristics Electrical characteristics for V CC = 1.2V to 5.5V (unless otherwise noted). Minimum and maximum characteristics are tested at T J = 25 C. Table 1.4 Electrical Characteristics Parameter Symbol Condition Min Typ Max Unit Input Supply Input Supply Voltage at VCC pin V CC 1.2 5.5 V Quiescent Current: On Mode I q-on V CC = 5V, no load 70 150 na Quiescent Current: Off Mode I q-off V CC < V THRESH, no load 100 pa Load Switch Over-Current Shutdown I OC V CC = 5.0V 3 A Over-Current Retry Period t OC V CC = 5.0V 1.7 ms Output Switch Leakage Current I LEAK-SW V CC < V THRESH; V OUT grounded 100 pa Switch ON-Resistance Rds-on V CC = 5.0V 175 mω V CC = 3.3V 200 mω V CC = 1.8V 350 mω Transition Times Transition Delay: On Mode to Off Mode Transition Delay: Off Mode to On Mode t d1 V OFF = 2.0V, V CC = 3.0V 1.5V 650 µs t d2 V OFF = 2.0V, V CC = 1.5V 3.0V 1.7 ms Output Turn-on Rise Time t ON V CC = 2.5V, R LOAD = 50Ω 200 µs NPG Output Output Leakage I LEAK-NPG V CC = 5.0V, V NPG = 5.5V 100 na Low-Level Output Voltage V OL-NPG I NPG = 5 ma 0.4 V Off Thresholds Off Threshold V OFF V THRESH = customer-selected threshold voltage in the range of 1.2V to 4.2V with 100mV steps between options programmed at manufacturing 0.95 V THRESH V THRESH 1.05 V THRESH V Off Mode to On Mode Hysteresis V Hys Rising Transition: Off Mode to On Mode 500 mv 2016 Integrated Device Technology, Inc. 6 January 29, 2016

2 Typical Performance Characteristics T = 25 C (unless otherwise noted) Figure 2.1 On Mode / Off Mode Characteristics Figure 2.2 On Mode Switching Behavior Figure 2.3 On Mode / Off Mode Quiescent Current I q Figure 2.4 Off Mode V THRESH Temperature Performance 2016 Integrated Device Technology, Inc. 7 January 29, 2016

Figure 2.5 On Mode / Off Mode Transition Delay Figure 2.6 Over-Current Retry Performance 3 Description of Circuit The ZSPM4121 battery management load switch includes an internally generated threshold voltage, comparator with hysteresis, slew rate control for the load switch, a P-channel load switch, and an open-drain indicator pin. When the input battery voltage rises to 500mV above the threshold, the load switch turns on (the On Mode). When the input battery voltage falls to the threshold voltage or below, the load switch is off (the Off Mode), and the quiescent current draw on the battery is in the order of 100pA (typical). The ZSPM4121 threshold voltage is programmed at manufacturing to an option in the range of 1.2V to 4.2V with 100mV steps between options. The 500mV hysteresis between the Off Mode and the On Mode prevents intermittent operation. The ZSPM4121 also provides over-current protection. Figure 3.1 ZSPM4121 Block Diagram ZSPM4121 VCC VOUT Regulated* V THRESH NPG GND * At manufacturing, VTHRESH is programmed to a customer-selected threshold voltage in the range of 1.2V to 4.2V with 100mV steps between options. 2016 Integrated Device Technology, Inc. 8 January 29, 2016

4 Application Circuit 4.1. Typical Application Circuit Figure 4.1 Application Circuit for Disconnecting the Load Charger ZSPM4121 VCC VOUT Load NPG GND 2016 Integrated Device Technology, Inc. 9 January 29, 2016

5 Pin Configuration and Package 5.1. Package Dimensions and Marking Diagram Figure 5.1 ZSPM4121 Package Drawing MARKING CODES: Z: ZMDI P: Product Code: 0 = ZSPM4121 V: Voltage levels: 0 = 1.2V, 1 = 1.3V, 2 = 1.4V, 3 = 1.5V, 4 = 1.6V, 5 = 1.7V, 6 = 1.8V, 7 = 1.9V, 8 = 2.0V, 9 = 2.1V, A = 2.2V, B = 2.3V, C = 2.4V, D to U = 2.5V to 4.2V YM: Date Code (Year, Month) 2016 Integrated Device Technology, Inc. 10 January 29, 2016

5.2. Pin Description for 8-Pin DFN (2x2 mm) Figure 5.2 ZSPM4121 Pin Assignments (top view) 1 GND NPG 8 2 VOUT VCC 7 3 NC VCC 6 4 NC NC 5 Table 5.1 Pin Description, 8-Pin DFN (2x2) Pin # Name Function Description 1 GND Ground GND 2 VOUT Output Output to system load 3 NC No connection (connect to GND or float) 4 NC No connection (connect to GND or float) 5 NC No connection (connect to GND or float) 6 VCC Supply Supply input (connect to pin 7 and VCC supply rail) 7 VCC Supply Supply input (connect to pin 6 and VCC supply rail) 8 NPG Output Open-drain N-channel output (low indicates Power Good ) 2016 Integrated Device Technology, Inc. 11 January 29, 2016

6 Layout and Soldering Requirements To maximize the efficiency of this package for applications on a single layer or multi-layer printed circuit board (PCB), certain guidelines must be followed when laying out this part on the PCB. 6.1. Recommended Landing Pattern for PCBs Figure 6.1 Recommended Landing Pattern for 8-Pin DFN 2016 Integrated Device Technology, Inc. 12 January 29, 2016

6.2. Multi-Layer PCB Layout The following are guidelines for mounting the exposed pad ZSPM4121 on a multi-layer PCB with ground a plane. In a multi-layer board application, the thermal vias are the primary method of heat transfer from the package thermal pad to the internal ground plane. The efficiency of this method depends on several factors, including die area, number of thermal vias, and thickness of copper, etc. Figure 6.2 Package and PCB Land Configuration for Multi-Layer PCB Solder Pad (Land Pattern) Package Thermal Pad Thermal Vias Package Outline Figure 6.3 JEDEC Standard FR4 Multi-Layer Board Cross-Sectional View (square) Package Solder Pad Component Traces 4 Plane 2 Plane 1.5748mm Thermal Via 1.5038-1.5748 mm Component Trace (2oz Cu) 1.0142-1.0502 mm Ground Plane (1oz Cu) Thermal Isolation Power plane only Package Solder Pad (bottom trace) 0.5246-0.5606 mm Power Plane (1oz Cu) 0.0-0.071 mm Board Base & Bottom Pad Figure 6.4 is a representation of how the heat can be conducted away from the die using an exposed pad package. Each application will have different requirements and limitations, and therefore the user should use sufficient copper to dissipate the power in the system. The output current rating of the linear regulators might need to be de-rated for higher ambient temperatures. The de-rated value will depend on the calculated worstcase power dissipation and the thermal management implementation in the application. 2016 Integrated Device Technology, Inc. 13 January 29, 2016

Figure 6.4 Conducting Heat Away from the Die using an Exposed Pad Package Mold compound Die Epoxy Die attach Exposed pad Solder Single Layer, 2oz Cu 5% - 10% Cu coverage Ground Layer, 1oz Cu Signal Layer, 1oz Cu Thermal Vias with Cu plating 90% Cu coverage 20% Cu coverage Bottom Layer, 2oz Cu Note: NOT to scale. 6.3. Single-Layer PCB Layout Layout recommendations for a single-layer PCB: Utilize as much copper area for power management as possible. In a single-layer board application, the thermal pad is attached to a heat spreader (copper areas) by using a low thermal impedance attachment method (solder paste or thermal conductive epoxy). In both of the methods mentioned above, it is advisable to use as much copper trace as possible to dissipate the heat. Important: If the attachment method is NOT implemented correctly, the functionality of the product is NOT guaranteed. Power dissipation capability will be adversely affected if the device is incorrectly mounted onto the circuit board. Figure 6.5 Application Using a Single-Layer PCB Use as much copper area as possible for heat spread Package Thermal Pad Package Outline 2016 Integrated Device Technology, Inc. 14 January 29, 2016

7 Ordering Information Ordering Code* Description Package ZSPM4121AI1W17 ZSPM4121 Under-Voltage Load Switch V THRESH factory set to 1.7V 8-pin DFN / 7 Reel (2500) ZSPM4121AI1W21 ZSPM4121 Under-Voltage Load Switch V THRESH factory set to 2.1V 8-pin DFN / 7 Reel (2500) ZSPM4121AI1W23 ZSPM4121 Under-Voltage Load Switch V THRESH factory set to 2.3V 8-pin DFN / 7 Reel (2500) ZSPM4121AI1W24 ZSPM4121 Under-Voltage Load Switch V THRESH factory set to 2.4V 8-pin DFN / 7 Reel (2500) ZSPM4121AI1W25 ZSPM4121 Under-Voltage Load Switch V THRESH factory set to 2.5V 8-pin DFN / 7 Reel (2500) ZSPM4121AI1W26 ZSPM4121 Under-Voltage Load Switch V THRESH factory set to 2.6V 8-pin DFN / 7 Reel (2500) ZSPM4121AI1W28 ZSPM4121 Under-Voltage Load Switch V THRESH factory set to 2.8V 8-pin DFN / 7 Reel (2500) ZSPM4121AI1W30 ZSPM4121 Under-Voltage Load Switch V THRESH factory set to 3.0V 8-pin DFN / 7 Reel (2500) ZSPM4121KIT ZSPM4121 Evaluation Kit * For a 13 reel (3300 parts), replace the W in the ordering code with an R. Custom V THRESH values are also available: 1.2V to 4.2V (typical) in 100mV increments. 8 Related Documents Document ZSPM4121 Feature Sheet ZSPM4121 Evaluation Kit Description ZSPM4121 Application Note Low Power Battery Control and Voltage Regulator Solutions for Remote Sensor Networks. Visit IDT s website www.idt.com or contact your nearest sales office for the latest version of these documents. 2016 Integrated Device Technology, Inc. 15 January 29, 2016

9 Glossary Term PG RFID SPM Description Power Good (NPG = Power Good, active low) Radio Frequency Identification Smart Power Management 10 Document Revision History Revision Date Description 1.00 April 30, 2012 First release 1.01 February 7, 2013 Addition of Electrostatic Discharge Charged Device Model specification in section 1.1. Update for block diagram. Updates for V designation in marking codes in section 5. Edits for clarity. Update to IDT contact information. January 29, 2016 Changed to IDT branding. Corporate Headquarters 6024 Silver Creek Valley Road San Jose, CA 95138 www.idt.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.idt.com/go/sales Tech Support www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of Integrated Device Technology, Inc. All rights reserved. 2016 Integrated Device Technology, Inc. 16 January 29, 2016