Software Driven Verification at SoC Level. Perspec System Verifier Overview

Software Driven Verification at SoC Level Perspec System Verifier Overview June 2015

IP to SoC hardware/software integration and verification flows Cadence methodology and focus Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS and Drivers (Linux, Android) Bare-Metal SW SoC Sub-System IP Spec Silicon

Metric-Driven Verification Planning and Management IP to SoC hardware/software integration and verification flows Cadence methodology and focus Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS and Drivers (Linux, Android) Hybrid Hardware/Software SoC Hardware/Software Integration Verification and Architecture Analysis Integration Bare-Metal SW SoC Gate-Level Verification Software- SoC Hardware/SW Use Case VerificationDriven Verification SoC IP Integration Verification Sub-System IP Spec SoC Interconnect UVM e/sv Metric-Driven Verification & Performance Analysis UVM e/sv Coverage- Subsystem UVM e/sv Metric-Driven Verification Driven Verification IP UVM e/sv Metric-Driven Verification Silicon

Metric-Driven Verification Planning and Management IP to SoC hardware/software integration and verification flows Cadence methodology and focus Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS and Drivers (Linux, Android) Hybrid Hardware/Software SoC Hardware/Software Integration Verification and Architecture Analysis Integration Bare-Metal SW SoC Gate-Level Verification Software- SoC Hardware/SW Use Case VerificationDriven Verification SoC IP Integration Verification Sub-System IP Spec SoC Interconnect UVM e/sv Metric-Driven Verification & Performance Analysis TLM Design UVM e/sv and Verification Coverage- Subsystem UVM e/sv Metric-Driven Verification Driven Verification IP UVM e/sv Metric-Driven Verification Silicon

Metric-Driven Verification Planning and Management IP to SoC hardware/software integration and verification flows Cadence methodology and focus Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS and Drivers (Linux, Android) Hybrid Hardware/Software SoC Hardware/Software Integration Verification and Architecture Analysis Integration Bare-Metal SW SoC Sub-System IP Spec Gate-Level Verification Formal-Assisted Software- SoC Hardware/SW Debug Use Case VerificationDriven Formal Coverage Closure Verification Applications SoC IP Integration Connectivity Verification SoC Interconnect UVM e/sv Metric-Driven Security Path Verification & Performance Analysis TLM Design Register Verification UVM e/sv and Verification Coverage- Subsystem Power-Aware UVM e/sv Verification Metric-Driven Verification Driven Functional Verification Verification IP UVM e/sv Metric-Driven Verification Design Bring-Up Sequential Equiv. Silicon

IP to SoC pre-silicon verification platforms SoC Hardware/Software Integration Verification and Architecture Analysis Gate-Level Verification SoC Hardware/Software Use-Case Verification SoC IP Integration Verification SoC Interconnect UVM e/sv Metric-Driven Verification and Performance Analysis Subsystem UVM e/sv Metric-Driven Verification IP UVM e/sv Metric-Driven Verification Spec Silicon

IP to SoC pre-silicon verification platforms SoC Hardware/Software Integration Verification and Architecture Analysis Gate-Level Verification SoC Hardware/Software Use-Case Verification SoC IP Integration Verification SoC Interconnect UVM e/sv Metric-Driven Verification and Performance Analysis Simulation and Formal Subsystem UVM e/sv Metric-Driven Verification IP UVM e/sv Metric-Driven Verification Spec Silicon

IP to SoC pre-silicon verification platforms SoC Hardware/Software Integration Verification and Architecture Analysis Gate-Level Verification SoC Hardware/Software Use-Case Verification Hardware Acceleration and Emulation Simulation and Formal Spec SoC IP Integration Verification SoC Interconnect UVM e/sv Metric-Driven Verification and Performance Analysis Subsystem UVM e/sv Metric-Driven Verification IP UVM e/sv Metric-Driven Verification Silicon

IP to SoC pre-silicon verification platforms Hardware Emulation or FPGA Prototype SoC Hardware/Software Integration Verification and Architecture Analysis Gate-Level Verification SoC Hardware/Software Use-Case Verification Hardware Acceleration and Emulation Simulation and Formal Spec SoC IP Integration Verification SoC Interconnect UVM e/sv Metric-Driven Verification and Performance Analysis Subsystem UVM e/sv Metric-Driven Verification IP UVM e/sv Metric-Driven Verification Silicon

IP to SoC pre-silicon verification platforms Virtual Platform and Hybrid Hardware Emulation or FPGA Prototype SoC Hardware/Software Integration Verification and Architecture Analysis Gate-Level Verification SoC Hardware/Software Use-Case Verification Hardware Acceleration and Emulation Simulation and Formal Spec SoC IP Integration Verification SoC Interconnect UVM e/sv Metric-Driven Verification and Performance Analysis Subsystem UVM e/sv Metric-Driven Verification IP UVM e/sv Metric-Driven Verification Silicon

P H Y P H Y A system-centric look at a modern SoC Many IPs Standard I/O Wifi, USB, PCI Express (PCIe ), etc. System infrastructure Interconnect, interrupt control, uart, timers Differentiators custom accelerators, modem ARM V8 CPUSubsystem Application Specific Components Cortex Cortex -A53 -A53 L2 cache Cortex Cortex -A57 A57 L2 cache 3D GFX DSP A/V Boot processor ARM M0 Modem Cache coherent fabric SoC interconnect fabric DDR 3 USB3.0 PCIe Gen 2,3 Eth er net HDMI SATA GPIO Display UART INTC MIPI PMU I2C PHY 3. 0 2. 0 PHY PHY WLAN LTE MIPI SPI JTAG Low-speed peripheral Timer subsystem High speed, wired interface peripherals Other peripherals Low speed peripherals SoC

P H Y P H Y A system-centric look at a modern SoC Many IPs Standard I/O Wifi, USB, PCI Express (PCIe ), etc. System infrastructure Interconnect, interrupt control, uart, timers Differentiators custom accelerators, modem Many cores Both symmetric and asymmetric Both homogeneous and heterogeneous ARM V8 CPUSubsystem Cortex Cortex Cortex Cortex -A53 -A53 -A57 A57 L2 cache L2 cache Cache coherent fabric DDR 3 USB3.0 PCIe Gen 2,3 Application Specific Components Boot 3D DSP processor GFX A/V ARM M0 SoC interconnect fabric HDMI Eth er SATA net GPIO Display Modem UART INTC MIPI PMU I2C PHY 3. 0 2. 0 PHY PHY WLAN LTE MIPI SPI JTAG Low-speed peripheral Timer subsystem High speed, wired interface peripherals Other peripherals Low speed peripherals SoC

P H Y P H Y Bare metal software DSP software Init Software for boot, power, security A system-centric look at a modern SoC Many IPs Standard I/O Wifi, USB, PCI Express (PCIe ), etc. System infrastructure Interconnect, interrupt control, uart, timers Differentiators custom accelerators, modem Many cores Both symmetric and asymmetric Both homogeneous and heterogeneous Lots of software Part of core functionality Communication stack, DSP software, GPU microcode User application software infrastructure Android, Linux Operating Systems (OS) Application software stack Applications Middleware Drivers Firmware / HAL ARM V8 CPUSubsystem Cortex Cortex Cortex Cortex -A53 -A53 -A57 A57 Compute L2 Sub cachesystem L2 DDR 3 PHY Cache coherent fabric USB3.0 PCIe Gen 2,3 High Speed, Wired Interface 3 2.. 0 0 PHY Peripherals High speed, wired interface peripherals Application Specific Components Boot Modem 3D DSP processor Application-Specific GFX A/V Components ARM M0 Eth er net PHY Software SoC interconnect fabric HDMI SATA General- MIPI WLAN Peripherals LTE SoC Customer s Purpose Other peripherals Bare-metal software GPIO Display PMU I2C Low-Speed MIPI SPI JTAG Low-speed peripheral subsystem Low speed peripherals UART INTC Peripherals Timer Communications L3 Communications L2 Communications L1 RTOS Drivers Firmware / HAL Mobile communications software stack

SoC-level verification and validation requirements

SoC-level verification and validation requirements Use-Case Reuse Architect Hardware Developer Software Developer User Verification Engineer Software Test Engineer Post-Silicon Validation Engineer How to communicate/share use cases between users

Vertical Reuse SoC-level verification and validation requirements Use-Case Reuse Scope (Integration) Middleware (Graphics, Audio, etc..) OS and Drivers Bare Metal Software SoC (Hardware + Software) Sub-System IP Architect Hardware Developer Software Developer User Verification Engineer How to communicate/share use cases between users How to create and reuse use cases from IP to SoC Software Test Engineer Post-Silicon Validation Engineer How to use C code to execute natively on many cores and communicate between cores How to run use cases across platforms and run more constrained random variants on faster platforms Virtual Platform Simulation Emulation FPGA Prototype Silicon Board Platform Horizontal Reuse

Vertical Reuse The solution: Perspec System Verifier Use-Case Reuse Scope (Integration) Middleware (Graphics, Audio, etc..) Architect Hardware Developer Software Developer User Verification Engineer Software Test Engineer Post-Silicon Validation Engineer OS and Drivers Bare-Metal Software Abstract Model with Reusable Use Cases Powerful Solvers SoC (Hardware + Software) Software Sub-System IP Perspec System Verifier c test c test c test c test Multi-Core Verification OS Firmware/HAL Scheduling, inter-processor communication, runtime randomization Many cores Multi-Cluster Apps Processors 3D GFX DSP A/V Boot Proc Comm Procs Virtual Platform Simulation Emulation FPGA Prototype Silicon Board Platform Horizontal Reuse

Automated use case verification SLN Models Desired Scenario: Decode video from the DDR and show on the display SoC SRAM CPU CPU CPU CPU DDR Controller DMA MODEM Interconnect USB controller GPX Audio Camera controller Display controller TB USB VIP Speaker Microphone

Automated use case verification SLN Models Desired Scenario: Decode video from the DDR and show on the display SoC SRAM CPU CPU CPU CPU DDR Controller DMA MODEM C test C test C test Abstract Tests Interconnect USB controller GPX Audio Camera controller Display controller TB USB VIP Speaker Microphone Perspec System Verifier automatically and exhaustively completes the goals in to full legal scenarios

Automated use case verification SLN Models Desired Scenario: Decode video from the DDR and show on the display Correct-by-construction generation for multiple targets SoC SRAM CPU CPU CPU CPU DDR Controller DMA MODEM C test C test C test Abstract Tests C test C test C test Target C test Interconnect USB controller GPX Audio Camera controller Display controller TB USB VIP Speaker Microphone Perspec System Verifier automatically and exhaustively completes the goals in to full legal scenarios

Automated use case verification SLN Models Desired Scenario: Decode video from the DDR and show on the display Re-generate the code for derivatives, spec changes, etc SoC SRAM CPU CPU CPU CPU DDR Controller DMA MODEM C test C test C test Abstract Tests C test C test C test Target C test Interconnect USB controller GPX Audio Camera controller Display controller TB USB VIP Speaker Microphone Perspec System Verifier automatically and exhaustively completes the goals in to full legal scenarios

Automated use case verification SLN Models Desired Scenario: Decode video from the DDR and show on the display SoC SRAM CPU CPU CPU CPU DDR Controller DMA MODEM C test C test C test Abstract Tests C test C test C test Target C test Interconnect USB controller GPX Audio Camera controller Display controller TB USB VIP Speaker Microphone Coverage model is autocreated and pruned for reachable scenarios Perspec System Verifier automatically and exhaustively completes the goals in to full legal scenarios

Automated use case verification SLN Models Desired Scenario: Decode video from the DDR and show on the display SoC SRAM CPU CPU CPU CPU DDR Controller DMA MODEM C test C test C test Abstract Tests C test C test C test Target C test Interconnect USB controller GPX Audio Camera controller Display controller TB USB VIP Speaker Microphone Perspec System Verifier automatically and exhaustively completes the goals in to full legal scenarios

Example use case Translating end-user use case to system-level bare-metal actions End-user use case: Mobile phone requirement: view a video while uploading it (6 words)

Example use case Translating end-user use case to system-level bare-metal actions End-user use case: Mobile phone requirement: view a video while uploading it (6 words) Solver schedules show and transmit in parallel as required by use case and adds decode to display Solver: Constrained random data and control flow UML Activity Diagram

Example use case Translating end-user use case to system-level bare-metal actions End-user use case: Mobile phone requirement: view a video while uploading it (6 words) Solver: Constrained random data and control flow UML Activity Diagram System-level bare-metal actions: Capture a video with camera using graphics processor and save it to a memory buffer in DDR0 in AVI format with medium resolution and MPEG3 audio with 4x3 aspect ratio then transmit the video using the modem and processor 3 while processor 2 shows the video on the built in display being streamed by the graphics processor of the video already saved in DDR0 memory buffer (66 words)

June 2015 Flow

Use-case verification flow with Perspec engine._..........._...._. SLN Model Resources, actions, C code templates Perspec Library C Test Abstract Debug Environment C Test Use Case Composer Debuggers (C/Design debuggers, etc.) Perspec Engine C Test C Test

Step #1: Capture topology and system SLN Model Resources, actions, C code templates Perspec Library actions Use Case Composer Perspec Engine

Step #2: Capture abstract use case >> solve for concrete use case(s) >> analyze gentime coverage SLN Model Resources, actions, C code templates Perspec Library Use Case Composer Perspec Engine

Step #2: Capture abstract use case >> solve for concrete use case(s) >> analyze gentime coverage SLN Model Resources, actions, C code templates Perspec Library Use Case Desired Composer Scenario: Decode video from the DDR and show on the display Perspec Engine Abstract Use Case

Step #3: Generate tests for specific platform(s) SLN Model Resources, actions, C code templates Perspec Library C Test C Test Use Case Composer C Test Perspec Engine Concrete Use Case C Test C Test

Step #3: Generate tests for specific platform(s) SLN Model Resources, actions, C code templates Perspec Library C Test C Test Use Case Composer C Test Perspec Engine Concrete Use Case C Test C Test Generated C Code

Step #4: Run tests and debug SLN Model Resources, actions, C code templates Perspec Library C Test C Test Use Case Composer C Test Perspec Engine Concrete Use Case C Test C Test Generated C Code

Step #4: Run tests and debug SLN Model Resources, actions, C code templates Perspec Library C Test C Test Use Case Composer C Test Perspec Engine Concrete Use Case C Test C Test Generated C Code Debug from UML activity diagram synchronized with source, waveform and log messages

Perspec Modeling Accellera Systems Initiative 15

Modeling elements Component: Functional unit groups actions and resources Action: Abstract operation of function Token: Include information for preconditions and outcomes Place: Defines interaction of tokens and actions (memory, channel, lock) Extend: Extending functionality of actions, components, and tokens

Modeling with Perspec System Verifier System language notation (SLN)

Constraints

C-code generation

Code generation

Public Success Stories Accellera Systems Initiative 21

ST TRD: Verify GPU modified for SoC power management

Texas Instruments: SoC verification flow

ST CPD: Complex SoC scenarios

PSWG Breaking News On September 8, Cadence, Mentor, and Breker issued a joint press release Three companies providing joint contribution to PSWG Contributing proven technology and leveraging expertise Why this combined effort? Avoids a long effort to evaluate multiple contributions Accelerates development of an Accellera standard Accelerates adoption of portable stimulus in the industry What s next? Joint contribution to PSWG by September 16 deadline BoF breakfast tomorrow 0800-0845 share your thoughts! Accellera Systems Initiative 25

June 2015 Demo

June 2015 Summary

Connecting it together Coherency use case User1

Connecting it together Coherency use case User1 User2 Power shutdown use case

Connecting it together Coherency use case User1 Coherency User3 User2 Power shutdown Power shutdown use case

Connecting it together Coherency use case User1 Coherency Mixed Scenario User3 User2 Power shutdown Power shutdown use case

Connecting it together Coherency use case 1. Cache transactions User1 Coherency Mixed Scenario User3 User2 Power shutdown Power shutdown use case

Connecting it together Coherency use case 1. Cache transactions User1 Coherency 2. Power down User2 User3 Mixed Scenario Power shutdown Power shutdown use case

Connecting it together Coherency use case 1. Cache transactions User1 Coherency 2. Power down User3 Mixed Scenario 3. Cache transactions User2 Power shutdown Power shutdown use case

Connecting it together Coherency use case 1. Cache transactions User1 Coherency 2. Power down User2 User3 Mixed Scenario Power shutdown 3. Cache transactions 4. Power up Power shutdown use case

Connecting it together Coherency use case 1. Cache transactions User1 Coherency 2. Power down User2 User3 Mixed Scenario Power shutdown 3. Cache transactions 4. Power up Power shutdown use case 5. Cache transactions

Connecting it together Coherency use case 1. Cache transactions User1 Coherency 2. Power down C Test C Test Mixed Scenario 3. Cache transactions User2 User3 Power shutdown 4. Power up C Test C Test Power shutdown use case 5. Cache transactions

Perspec System Verifier Productivity 10X improvement for complex SoC test creation Abstraction UML-style use-case diagrams Automation System use-case test generation Portability Reuse across all execution platforms Measurement SoC-level hardware/software coverage metrics

June 2015 Thank You