Using Formalized Programming Sequences for Higher Quality Virtual Prototypes
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1 Using Formalized Programming Sequences for Higher Quality Virtual Prototypes Sean Boylan Duolog Technologies
2 Outline Motivation - VSP Quality Programming Sequences Applying Sequences Tools for Sequences Conclusions
3 SoC Design The New Reality Architecture RTL Verification Virtual SW Time New Reality SoC design is becoming highly concurrent and requires precise synchronization between teams
4 ESL Motivation Virtual Prototypes are now main stream - No Longer just used by early adopters - Part of Project Plan Main Stream Main Stream -> need for higher quality - Debug software not Virtual Prototype integration issues - Busted Virtual Prototypes can block whole departments of SW engineers Virtual Prototypes are more complex s of IP s - Power sub-system, clocks sub-system, SoC modes
5 Outline Motivation - VSP Quality Programming Sequences Applying Sequences Tool Requirements for Sequences Conclusions
6 HW/SW Interface Processor Sub-Systems IP Blocks Registers 0x Memory Sub-system 0x3000 USB PROCESSOR M MEMORY_MAP 0x x x xF Peripheral Sub-system Graphics Sub-system MEMORY_MAP 0x4000 0x5000 UART SPI MEMORY_MAP PROCESSOR M
7 UART - Programming Sequences ARM UART PL011 HW/SW spec defines how to program, verify and integrate IP Block Set the Baud Rate Set up FIFO Enable Transmit Write Data
8 Constraints ARM UART PL011 Global Constraints Reserved bits must not be used - locations at offsets 0x008 through 0x014, 0x01C are reserved and must not be - accessed - locations at offsets 0x04C through 0x07C are reserved for possible future extensions - locations at offsets 0x080 through 0x08C are reserved for test purposes - locations at offsets 0x90 through 0xFCC are reserved for future test purposes - location at offsets 0xFD0 through 0xFDC are used for future identification registers - location at offsets 0xFE0 through 0xFFC are used for identification registers
9 Hierarchical Sequence : Test UART Test UART ARM UART PL011 Reset UART Set Baud Rate Enable Loopback Write Hello World Read Hello World
10 Outline Motivation - VSP Quality Programming Sequences Applying Sequences Tool Requirements for Sequences Conclusions
11 Virtual Prototype Qualification Goal: Qualify/Assure that basic functionality is working after incrementally adding functionality In reality this is complex - Power Control - Clock Control - Mode Control IO Mux ing - Functional Modes Requires multi-block/function sequences
12 Unit Test Wrapped C-code TLM 2.0 Init Interrupt TLM 2.0 Target M0 M1 UART Socket Communication >Hello World
13 Virtual Proto Incremental Changes Code M0 ARM A9 (Codelink) M1 INTC JPEG cfg dma Code Sourcery clk reset Main.x (ELF) TLM 2.0 FABRIC UART >Hello World ROM Model DRAM Model
14 RTL/TLM Unit Test UVM Environment UVM Environment Register Model Sequences reg.read reg.write Shadow Verification Component Monitor DUV/DUT Registers Built-in tests reset Bit_bash Access Adapter Sequencer Driver S Programming Sequences
15 Outline Motivation - VSP Quality Programming Sequences Applying Sequences Tool Requirements for Sequences Conclusions
16 Sequence Capture Captured via a Dedicated Editor - Support for auto-completion, syntax checking, code templates and a range of markers Sequence Language Easy to Learn and Understand - A subset of C with some sequence specific extensions - Constraint syntax closely aligned to SystemVerilog Leverages Existing Formats for Register Descriptions - Compatible with Bitwise format, IEEE1685 (IP-XACT), others Coherency Checking - Assures compatibility of the sequence and the Register Descriptions for all blocks in the sequence
17 Language and an Editor
18 Coherency Checker
19
20
21
22 Outline Motivation - VSP Quality Programming Sequences Applying Sequences Tools Requirements for Sequences Conclusions
23 Conclusions A Need for Higher Quality Virtual Prototypes Out of the Box - Main Stream implies a need for a higher quality level Programming Sequences can be used to assure higher Quality - baseline of tests that can be applied across the development spectrum - TLM unit test - Virtual Prototype Integration - - RTL Unit Test - SoC RTL Integration - - Lab Bring up -. - Device Driver Development??
24 Conclusion Faster IP integration Faster Testbench development Faster Software bring up Faster debug.. faster Time-to-Market Better Products
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