Micro computer Organization I Base Basic Components CPU SYSTEM BUSES VDD CLK RESET 1
MPU vs MCU Microprocessor Unit (MPU) CPU (called Microprocessor) is a die All components external to die Basically on one or several boards CPU is optimized Microcontroller Unit (MCU) All components in a die Less complex MCU: Generic structur 2
Practical examples: MSP430G2x01 MSP430G2x53 (Launchpad) 3
Practical Examples: MSP430F5437 Other characteristics RISC vs CISC architectures Hardware Model Vs Programmers Model Hardware model focuses on hardware characteristics that supports instructions, timing, etc. Programmer s model focuses on Instructions and addressing mode syntax Memory and IO map Transfers, etc. Program models of IO Registers In Embedded Systems, both models are needed at least at system level. 4
RISC Architecture RISC vs CISC (1/2) (Reduced Instruction Set Computer) Small set of instructions (optimized) Emphasis on simpler hardware Many instructions take one system clock cycle More Lines of code More CUP registers to minimize interaction with memory CISC Architecture RISC vs CISC (2/2) (Complex Instruction Set Computer) Larger set of instructions Instructions have different system clock cycles Emphasis on simpler software Less lines of codes RISC has become more popular, but final decision depends on needs and other considerations 5
Microcomputer Organization II CPU CPU Components Hardware components Control Unit (CU) Registers Arithmetic Logic Unit (ALU) Bus Interface Logic unit (BIL) Software Components Instruction Set Addressing modes 6
CPU Data Path and Control Path Data Path: HW components used to perform operations ALU Registers and Internal Buses Specialized units Control Path: HW components controlling system operation CU BIL Timing and synchronization units ALU ALU (Arithmetic Logic Unit): Combinatorial circuit which realizes the arithmetic and logic operations. The width of ALU operands gives name to the classification in bits of the MCU: 4-bit microcontrollers, 16-bit microcontrollers, etc. ALU controls several flags in Status Register 7
CU (Control Unit): CU Sequential circuit finite state machine that controls the activity of the system Controls to retrieve instructions from memory Coordinates the instruction cycle Coordinates transfers and so on. CPU: Registers Special Purpose Registers used for specific operation. Common ones are Instruction Register () not available to programmer - Program Counter (PC) Stack Pointer (SP) Status Register (SR) General Purpose registers Invisible registers, for internal operation, not available to programmer 8
Instruction Cycle or CPU Cycle: Fetch-Decode Execute Fetch: The CU brings a new instruction from memory through BIL Register PC provides the address of instruction to be fetched Instruction is stored in Decode: instruction meaning is deciphered Execute: CU commands the corresponding units to perform the actions. Reset: A defined state after power up or after a reset occurs Important Note: Instruction Address in PC A. Register PC always has the address of the following instruction after the execution phase. B. If the execution phase does not change contents of PC, then the address of the following instruction is in PC after the decoding phase. 9
Example: Initial State Address Contents 0F812 0F810 0F80E 4809 2C07 XXXX XXXX XXXX Just after a previous cycle: 0F80C 0F80A 0F808 0F806 0F804 5292 403A 5A06 R10 F804 9A4F PC a) Contents of is irrelevant. b) PC points to next instruction 2036 D54A 6D45 5FA8 R6 C3D0 C = 1 Z = 0 N = 0 V = 1 FETCH Address Contents 0F812 0F810 0F80E 0F80C 0F80A 0F808 0F806 0F804 4809 2C07 5292 403A 5A06 R10 5A06 XXXX XXXX 9A4F F806 PC CU puts PC contents in Address Bus (using BIL unit) and reads (using Data Bus and Control Bus) memory contents and puts result into Instruction Register PC increases its value pointing to next address. 2036 D54A 6D45 5FA8 R6 C3D0 C = 1 Z = 0 N = 0 V = 1 (Fetched word in this first movement is the Instruction Word) 10
DECODE Address 0F812 0F810 Contents 4809 2C07 5A06 XXXX XXXX CU decodes: Add contents of R10 to contents of R6 0F80E 0F80C F806 PC The information is complete. so decoding is finished. 0F80A 0F808 0F806 0F804 2036 5292 403A 5A06 D54A 6D45 5FA8 R10 R6 9A4F C3D0 C = 1 Z = 0 N = 0 V = 1 a) In Register Transfer Notation (RTN): R6 R6 + R10 b) Decoding is finished and PC is pointing to address following this instruction EXECUTE Address Contents 0F812 0F810 4809 2C07 5A06 XXXX XXXX 0F80E 0F80C 0F80A 0F808 0F806 0F804 2036 5292 403A 5A06 D54A 6D45 5FA8 R10 R6 9A4F 5E1F F806 C = 1 Z = 0 N = 0 V = 1 PC The processor executes what decoding indicated: a) Old contents of destination is lost and has been replaced with new result b) Flags have been affected by this instruction c) contents is the same, but it is irrelevant 11
FETCH Address Contents 0F812 0F810 4809 2C07 403A XXXX XXXX 0F80E 0F80C 0F80A 0F808 0F806 0F804 5292 403A 5A06 R10 F808 9A4F PC CU fetches Instruction word and increments PC which is now pointing to next address. 2036 D54A 6D45 5FA8 R6 5E1F C = 1 Z = 0 N = 0 V = 1 Address Contents DECODE (1) 0F812 0F810 4809 2C07 403A XXXX XXXX 0F80E 0F80C 0F80A 0F808 0F806 0F804 2036 5292 403A 5A06 D54A 6D45 5FA8 R10 R6 9A4F 5E1F F808 C = 1 Z = 0 N = 0 V = 1 PC CU determines that the instruction needs the data in memory after the instruction word, so it is necessary to fetch this word (Not an instruction word) to complete decoding. Therefore, it will fetch the word and place it on the before completing decoding. PC is incremented accordingly 12
DECODE (2) Address Contents 0F812 0F810 0F80E 4809 2C07 403A XXXX DECODED instruction: Copy (move) the word into R10 0F80C F80A PC 0F80A 0F808 0F806 0F804 5292 403A 5A06 R10 9A4F a) In RTN: R10 Also R10 # 2036 D54A 6D45 5FA8 R6 5E1F C = 1 Z = 0 N = 0 V = 1 b) Decoding is finished and PC is pointing to address following this instruction Execute Address Contents 0F812 0F810 4809 2C07 403A XXXX 0F80E 0F80C 0F80A 0F808 0F806 0F804 2036 5292 403A 5A06 D54A 6D45 5FA8 R10 R6 5E1F F80A C = 1 Z = 0 N = 0 V = 1 PC The processor executes what decoding indicated: a) Old contents of destination is lost and has been replaced with new result b) Flags are not affected by this instruction c) contents is the same, but it is irrelevant 13
Fetch Address Contents 0F812 0F810 4809 2C07 5292 XXXX 0F80E 0F80C 0F80A 0F808 0F806 0F804 5292 403A 5A06 R10 F80C PC CU fetches Instruction word and increments PC which is now pointing to next address. 2036 D54A 6D45 5FA8 R6 5E1F C = 1 Z = 0 N = 0 V = 0 Address Contents Decode (1) 0F812 0F810 4809 2C07 5292 XXXX 0F80E 0F80C 0F80A 0F808 0F806 0F804 5292 403A 5A06 R10 F80C PC CU determines that the instruction needs data in memory after the instruction word. This time, two words, to complete decoding. Therefore, it will fetch the words and place them on the 2036 D54A 6D45 5FA8 R6 5E1F C = 1 Z = 0 N = 0 V = 0 PC is incremented accordingly 14
Decode (2,3) Address 0F812 0F810 0F80E 0F80C Contents 4809 2C07 5292 F810 PC DECODED instruction: Add the word in memory with address to the word in memory with address 0F80A 0F808 0F806 0F804 5292 403A 5A06 R10 a) In RTN: () () + () Also & & + & 2036 D54A 6D45 5FA8 R6 5E1F C = 1 Z = 0 N = 0 V = 1 b) Decoding is finished and PC is pointing to address following this instruction Execute Address Contents 0F812 0F810 4809 2C07 5292 0F80E 0F80C 0F80A 0F808 0F806 0F804 2036 5292 403A 5A06 34F2 6D45 5FA8 R10 R6 5E1F F810 C = 1 Z = 0 N = 0 V = 0 PC The processor executes what decoding indicated: a) Old contents of destination is lost and has been replaced with new result b) Flags are affected by this instruction c) contents is the same, but it is irrelevant 15
Fetch Address Contents 0F812 0F810 4809 2C07 2C07 0F80E 0F80C 0F80A 0F808 0F806 0F804 5292 403A 5A06 R10 F812 PC CU fetches Instruction word and increments PC which is now pointing to next address. 2036 34F2 6D45 5FA8 R6 5E1F C = 1 Z = 0 N = 0 V = 0 Decode Address 0F812 0F810 0F80E Contents 4809 2C07 2C07 CU decodes: IF flag C is set (C=1) THEN go to instruction at address F820h 0F80C F812 PC Technically, if C is set then 0F80A 0F808 5292 PC PC + 2 (0007h) 0F806 0F804 2036 403A 5A06 34F2 6D45 5FA8 R10 R6 5E1F C = 1 Z = 0 N = 0 V = 0 a) In RTN, express objective; If C=1, GOTO to F820h or IF C=1, PC F820h b) Decoding is finished and PC is pointing to address following this instruction 16
Execute Address 0F820 0F81E Contents 4303 2C07 2C07 The execution in this case changes the contents of the PC. 0F81C 0F81A 8A0B 4004 Jump F820 PC This will cause a JUMP in the sequence of instructions. 0F818 0F816 0F814 F249 AF24 269F Normal flow The next instruction to be fetched is not the one after the current one. 0F812 4809 The instruction does not affect flags. 2036 34F2 6D45 5FA8 C = 1 Z = 0 N = 0 V = 0 Important facts to remember Instruction can have one or more words Instruction word: First word in the set. Instruction word: Op Code and Addressing modes After the decode state, the PC holds the memory address after the current instruction Execution of Program flow instructions may alter PC For other instructions, this is the address of next instruction After the execution state, the PC has the address of the next instruction 17
Status Register Contains flags related to result of execution for some instructions involving ALU and a control Interrupt Flag. All systems include Carry Flag (C) Zero Flag (Z) Negative Flag (N) Overflow Flag (V) Interrupt flag (IF) or General Interrupt flag (GIE) Interrupts blocked with IF are called maskable Contains group of bits related to system control 18
Carry flag: Special remarks In arithmetic operations, the Carry Flag may have dual function: Carry and Borrow Some MCU s have a separate borrow flag Depending on the MCU model (see user guide): C=1 if a borrow is not needed in subtraction or C=0 if a borrow is needed in subtraction MSP430 adheres to this convention Flags and Number comparison (Using A-B) Note: This table assumes that C=0 indicates need of borrow in subtraction 19
Stack Pointer (SP) Manages a particular memory segment called STACK STACK operations are PUSH (Store) and POP (Retrieve) The SP register contents indicates where data is stored in a push operation, and where data is retrieved from in a pop operation SP contents is usually named Top of Stack Details later. Stack features The Stack may be Defined by user (usual case) by initializing SP, or hardware defined (some MCU models) The stack serves the user to temporary store data, and temporary free a register for some use. The stack and the SP register also support in the background special activities that require saving data temporarily. Example: Program flow transfers to and from subroutines (function) Management of Interrupt service. 20
Microcomputer Organization III Hardware Characteristics of MSP430 CPU - CPUX Highlights MSP430 offers two architectures: Original MSP430 64K memory, with CPU Extended MSP430X with 1M memory capacity, CPUX MSP430X is 100% downward compatible with MSP430 ALU CPU: 16 bits CPUX: 20 bits 21
CPU CPUX 22
CPU and CPUX registers 16 registers. CPU has 16-bit registers CPUX has 20-bit registers that operate as CPU registers for all CPU instructions. Status Register has 16-bits in both cases. Register R0: Program Counter (PC) with bit0=0, hardwired Register R1: Stack Pointer (SP) with Bit0 = 0, hardwired Register R2: Status Register (SR), 16-bits only Also works as constant generator (CG1) Register R3: Constant Generator (CG2) (actually not a register) Registers R4 to R15: General Purpose generators. MSP430 Status Register (1/2) C: Carry Flag Z: Zero Flag N: Sign Flag GIE: Global Interrupt enable Flag V: Overflow Flag 23
MSP430 Status Register (2/2) CPU Off: Turns on and off the CPU CPU Off if CPUOFF=1 OSCOFF: Turns on and off the Crystal Oscillator Oscillator Off when OSCOFF=1 SCG1 and SCG0 are combined with CPUOFF and OSCOFF to define the modes of operation Modes of operation LPM: Low power mode 24
Micro Computer Organization: SYSTEM BUSES General Concepts (1/2) A bus: a group of lines (conductors) that perform a similar function. Each line carries a bit The lines of the bus may be interpreted as a word or bitwise, depending on use System buses are used by CPU to communicate with memory and IO devices. 25
General Concepts (2/2) Basically, the CPU communicates with registers The contents of the register constitute the data to be processed Each register is identified by an address We need signals to control the protocols to be followed with the transactions The System buses are: DATA BUS, ADDRESS BUS and CONTROL BUS Hardware considerations (1/3) Buses have direccionality Data bus is bidirectional Address bus is normally unidirectional Control bus lines are normally unidirectional but some may be bidirectional Bus states Some buses may have high impedance state (Z) in addition to high and low value states In some systems, bus lines may share CPU terminals 26
Hardware considerations (2/3): Unidirectionality CPU BUS 1. Buffered CPU BUS 2. Buffered Tri-state CPU (control bus bit) CPU CPU (control bus bit) D En Q BUS 3. Latched Hardware considerations (3/3): bidirectionality example - BE (bus enable) and Dir (direction) are control bus signals BE D Bus direction 0 X High state 1 0 CPU BUS 1 1 CPU BUS 27
Example: A fully buffered 8086 microprocessor. Notes: 1 244: Octal three state buffers, used as buffers because OE grounded 2 373 Octal latches 3 245 Octal transceivers (hex version available) Source: Intel Microprocessors 8088/8086.. Barry Brey, eigth edition 245 and 373 examples NXP74AHC373 NXP75ABT2245 28
Data Bus (1/2) For carrying data and instructions to or from the CPU Read Operation: information is being transferred into the CPU Input: when an input device is read Write operation: information is being transferred out from the CPU Output: when writing is upon an output device Data Bus (2/2) Data bus bits are interpreted as a word, a data word Data bus bits: D(m-1) D(m-2). D1 D0 Data bus transaction: When a transfer of information using data bus occurs. Width of Data bus m: It determines the maximum data size that can be transferred in one transaction If m=8, 2 transactions are needed for a word size datum, 4 transactions for a double word datum 29
Address Bus (1/2) CPU interacts with one memory register or peripheral device register at a time. Each register is uniquely identified with an identifier called address The Address Bus has the address. Read as word Address bits A(n-1)A(n-2) A1 A0 Bus unidirectional The width of the Add. Bus determines the maximum addressable memory space. Control Bus Groups all the lines carrying the signals that regulate the system activity. Basically unidirectional Control bus bits are identified by function, separately We do not speak of Control Bus bits. 30