The Evolution of Microprocessors. Per Stenström

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Transcription:

The Evolution of Microprocessors Per Stenström

Processor (Core) Processor (Core) Processor (Core) L1 Cache L1 Cache L1 Cache L2 Cache Microprocessor Chip Memory

Evolution of Microprocessors Multicycle Pipelined Superscalar Multicore and beyond 1970 1980 1990 2000 2010 2020 Time

Multicycle Computers

Fetch next instruction Decode/Fetch data Execute Store result

Opcode Assembly code Meaning Comments ADD,SUB, ADD R1,R2,R3 R1=(R2) + (R3) Integer operations ADDI, SUBI ADDI R1,R2,#3 R1=(R2)+3 Immediate AND, OR, XOR AND R1,R2,R3 R1=(R2).AND.(R3) bit-wise logical AND,OR, XOR SLT SLT R1,R2,R3 If (R2)<(R3) then R1=1 else R1=0 ADD.D, SUB.D, MUL.D, DIV.D Test R2, R3 outcome in R1 ADD.D F1,F2,F3 F1=(F2)+(F3) Floatingpoint operations

Opcode Assembly code Meaning Comments LB,LH,LW,LD LW R1,#20(R2) R1=MEM[20+(R2)] For bytes, half-words, words and double words SB,SH,SW,SD SW R1,#20(R2) MEM[20+(R2)]=R1 L.S, L.D L.S F0,#20(R2) F0=MEM[20+(R2)] Single/double float load S.S, S.D S.S F0,#20(R2) MEM[20+(R2)]=F0 Single/double float store

Opcode Assembly code Meaning Comments BEQZ, BNEZ BEQZ R1,Label If (R1)=0 then PC=Label BEQ, BNE BEQ R1,R2,Label If (R1)=(R2) PC=Label Conditional branch-equal 0/not equal 0 Conditional branchequal/not equal J J Target PC=Target Target is an immediate field JR JR R1 PC=(R1) Target is in register JAL JAL Target R31 = PC + 4; PC = Target Jump to target and save return address in R31

PC Read Address [31..0] memory

ALU Memory transfer PC Control Read Address [31..0] memory [15..11] [25..21] [20..16] Rs addr Rs data Rt addr Rt data Registers [15..0]

ALU Memory transfer PC Control Read Address [31..0] memory [15..11] [25..21] [20..16] Rs addr Rs data Rt addr Rt data Registers ALU [15..0]

ALU Memory transfer PC Control Read Address [31..0] memory [15..11] [25..21] [20..16] Rs addr Rs data Rt addr Rt data Registers ALU [15..0]

ALU Memory transfer PC Control Read Address [31..0] memory [15..11] [25..21] [20..16] Rs addr Rt addr Registers Rs data Rt data ALU Effective addresss Displacement + (Rs) [15..0] Sign Extend

ALU Memory transfer PC Control Read Address [31..0] memory [15..11] [25..21] [20..16] Rs addr Rt addr Registers Rs data Rt data ALU Wr addr Rd data Data memory [15..0] Sign Extend

ALU Memory transfer PC Control Read Address [31..0] memory [15..11] [25..21] [20..16] Rs addr Rt addr Registers Rs data Rt data ALU Wr addr Rd data Data memory [15..0] Sign Extend

+4 ALU Memory transfer PC Read Address [31..0] memory ADD [15..11] [25..21] [20..16] Rs addr Rt addr Registers Rs data Rt data Control Fetching the next instruction ALU Wr addr Rd data Data memory [15..0] Sign Extend

+4 ALU Memory transfer PC Read Address [31..0] memory ADD BEQ R1,R2,offset [15..11] [25..21] [20..16] Rs addr Rs data Rt addr Rt data Registers Shift Left 2 ADD ALU ZERO Wr addr Rd data Data memory Control [15..0] Sign Extend

+4 PC Read Address [31..0] memory ADD [15..11] [25..21] [20..16] Rs addr Rt addr Registers Rs data Rt data Shift Left 2 ADD ALU Wr addr Rd data Data memory [15..0] Sign Extend

+4 PC Read Address [31..0] memory ADD [15..11] [25..21] [20..16] RegDst [15..0] Rs addr Rt addr RegWrite Registers Sign Extend Rs data Rt data Shift Left 2 ALUSrc ADD ALU ALUOp MemRead PCSrc Wr addr Rd data Data memory MemWrite MemToReg

INSTRUCTION FETCH +4 DECODE /OPERAND FETCH EXECUTE MEMORY ACCESS WRITE BACK PC Read Address [31..0] memory ADD [15..11] [25..21] [20..16] Rs addr Rt addr Registers Rs data Rt data Shift Left 2 ADD ALU Wr addr Rd data Data memory [15..0] Sign Extend

Pipelined Single-Cycle Computer

The Conveyor Belt

LABEL: LD R2, 0(R10) LD R3, 0(R11) +4 ADD R1,R2,R3 SD 0(R12), R1 SUBI R4,R4,#1 PC Read Address [31..0] memory ADD [15..11] [25..21] [20..16] Rs addr Rt addr Registers Rs data Rt data Shift Left 2 ADD ALU Wr addr Rd data Data memory ADDI R10,R10,#4 ADDI R11,R11,#4 ADDI R12,R12,#4 BNEZ R4, LABEL [15..0] Sign Extend SUBI R4,R4,#1 SD 0(R12),R1 ADD R1,R2,R3 LD R3,0(R11) LD R2,0(R10)

Structural hazards +4 Data hazards Control hazards PC Read Address [31..0] memory ADD [15..11] [25..21] [20..16] Rs addr Rt addr Registers Rs data Rt data Shift Left 2 ADD ALU Wr addr Rd data Data memory [15..0] Sign Extend SUBI R4,R4,#1 SD 0(R12),R1 ADD R1,R2,R3 LD R3,0(R11) LD R2,0(R10)

Structural hazards +4 Data hazards Control hazards PC Read Address [31..0] memory ADD [15..11] [25..21] [20..16] Rs addr Rt addr Registers Rs data Rt data Shift Left 2 ADD ALU Wr addr Rd data Data memory [15..0] Sign Extend SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3 LD R3,0(R11)

Structural hazards +4 Data hazards Control hazards PC Read Address [31..0] memory ADD [15..11] [25..21] [20..16] Rs addr Rt addr Registers Rs data Rt data Shift Left 2 ADD ALU Wr addr Rd data Data memory [15..0] Sign Extend SUBI R4,R4,#1 SD 0(R12),R1 UNUSED UNUSED ADD R1,R2,R3

Structural hazards +4 Data hazards Control hazards PC Read Address [31..0] memory ADD [15..11] [25..21] [20..16] Rs addr Rt addr Registers Rs data Rt data Shift Left 2 ADD ALU Wr addr Rd data Data memory [15..0] Sign Extend UNUSED BEQ R1,offset

Structural hazards +4 Data hazards Control hazards PC Read Address [31..0] memory ADD [15..11] [25..21] [20..16] Rs addr Rt addr Registers Rs data Rt data Shift Left 2 ADD ALU Wr addr Rd data Data memory [15..0] Sign Extend UNUSED UNUSED BEQ R1,offset

Structural hazards +4 Data hazards Control hazards PC Read Address [31..0] memory ADD [15..11] [25..21] [20..16] Rs addr Rt addr Registers Rs data Rt data Shift Left 2 ADD ALU Wr addr Rd data Data memory [15..0] Sign Extend NEXT INST. UNUSED UNUSED BEQ R1,offset

Superscalar Microprocessors

IF ID IS EX WB Fetch Decode/ Dispatch Issue/Read Operands Execute Write Back

IQ 1 EX 1 IF ID IQ 2 EX 2 WB IQ N EX N Fetch Decode/ Dispatch Read Operands Execute Write Back

I-Q INT IF ID FP-Q FP WB Cycle: 1 M-Q MEM L.S F0,0(R1) Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop

I-Q INT IF ID FP-Q FP WB Cycle: 2 M-Q MEM L.S F1,0(R2) L.S F0,0(R1) Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop

I-Q INT IF ID FP-Q FP WB Cycle: 3 M-Q L.S F0,0(R1) MEM ADD.S F2,F1,F0 L.S F1,0(R2) Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop

I-Q INT IF ID FP-Q FP WB Cycle: 4 M-Q L.S F1,0(R2) MEM L.S F0,0(R1) S.S F2,0(R1) ADD.S F2,F1,F0 Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop

I-Q INT IF ID ADD.S FP-Q F2,F1,F0 FP WB Cycle: 5 M-Q MEM L.S F1,0(R2) ADDI R1,R1,#4 S.S F2,0(R1) L.S F0,0(R1) Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop

I-Q INT IF ID FP-Q ADD.S FP F2,F1,F0 WB Cycle: 6 M-Q S.S F2,0(R1) MEM ADDI R2,R2,#4 ADDI R1,R1,#4 L.S F1,0(R2) Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop

I-Q ADDI R1,R1,#4 INT IF ID FP-Q ADD.S FP F2,F1,F0 WB Cycle: 7 M-Q S.S F2,0(R1) MEM SUBI R3,R3,#1 ADDI R2,R2,#4 Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop

I-Q INT ADDI R2,R2,#4 Cycle: 8 ADDI R1,R1,#4 IF ID FP-Q ADD.S FP F2,F1,F0 WB M-Q S.S F2,0(R1) MEM BNEZ R3,Loop SUBI R3,R3,#1 The ADDI R1,R1,#4 is being executed Out-of-program-order with respect to the S.S F2,0(R1)! Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop

I-Q SUBI R3,R3,#1 INT IF ID FP-Q ADD.S FP F2,F1,F0 WB ADDI R2,R2,#4 Cycle: 9 M-Q S.S F2,0(R1) MEM L.S F0,0(R2) BNEZ R3,Loop ADDI R1,R1,#4 Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop

I-Q BNEZ R3,Loop INT SUBI R3,R3,#1 IF ID FP-Q ADD.S FP F2,F1,F0 WB Cycle: 10 M-Q S.S F2,0(R1) MEM L.S F1,0(R1) L.S F0,0(R2) ADDI R2,R2,#4 Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop

I-Q INT BNEZ R3,Loop IF ID FP-Q ADD.S FP F2,F1,F0 WB Cycle: 11 M-Q S.S F2,0(R1) MEM L.S F1,0(R1) L.S F0,0(R2) SUBI R3,R3,#1 Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop

I-Q INT BNEZ R3,Loop IF ID FP-Q FP WB Cycle: 12 M-Q L.S F0,0(R2) MEM S.S F2,0(R1) ADD,S F2,F1,F0 L.S F1,0(R1) ADD.S F2,F1,F0 Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop

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