Demonstration of Technical & Economic Feasibility Results are presented which demonstrate the technical and economic feasibility of backplane signaling at 5+ and 1+ Gigabits/second Brian Seemann Xilinx
Goals of Technical Study Produce a representative set of backplanes that use currently available components and construction technology Characterize the backplanes performance capabilities Demonstrate transmission of signals using currently available, mainstream silicon product
Objectives of this Presentation Present a body of existing evidence, representative of the industry s knowledge of backplane technology Demonstrate technical feasibility of 1Gbps NRZ Physical Electrical layer backplane communication Demonstrate that the proposed Ethernet is feasible
Presentation flow s analyzed Matrix Pictures Descriptors Technical approach Characterization Signaling assumption NRZ least equalization Simulation Stat eye Silicon signal Results Picture Shots of sim/stat eye/silicon Conclusion for each Summary matrix green squares for good Conclusions
s Characterized BP-A XAUI Reference Design / Tyco HM-Zd / Nelco BP-D Xilinx-designed / Teradyne GBX / Rogers BP-DF Xilinx-designed / Teradyne GBX / FR4 BP-ER Xilinx-designed / ERNI XT / Rogers BP-E Xilinx-designed / ERNI XT / FR4 BP-F Winchester-designed / SIP 1 / Rogers BP-F2 Winchester-designed ATCA / SIP 1-I / Rogers BP-F4 Winchester-designed ATCA / SIP 1-I / Rogers BP-G Tier 1 Systems mfg / ERNI ERmet-Zd / Rogers
s Studied Designator Configuration Connector Designed by Routing BP-A XAUI Reference Design Tyco HM-zD Tyco Partial Route BP-C ATCA Platform Tyco HM-zD Kaparel PICMG Material, Layers Line Card Distances Traces 2+3+2.185", Nelco =34 inch 4-2, Nelco Nelco 8 pairs routed High Density, full route FR4 FR4 BP-D Full Mesh and Star Teradyne GBX Xilinx High Density, full route.22", Rogers Hybrid, 8 signal layers FR4 3+2+3 =26 inch W=8mil / S=8mil 55 pairs routed BP-DF Full Mesh and Star Teradyne GBX Xilinx BP-ER Full Mesh and Star ERNI xt Xilinx BP-E Full Mesh and Star ERNI xt Xilinx BP-F BP-F2 BP-F4 BP-G Full Mesh and Star ATCA Form Factor Selective Route ATCA Form Factor Selective Route Dual Star Winchester SIP 1 Wincester Winchester SIP 1 I-Platform Winchester Winchester SIP 1 I-Platform Winchester ERNI ERMET-zD Tier 1 Customer High Density, full route High Density, full route.22", FR4, 8 signal layers.265", Rogers Hybrid, 8 signal layers FR4 FR4 3+2+3 =26 inch 3+21+3 =27 inch High Density, full route.225", Rogers Hybrid, 8 signal layers FR4 3+21+3 =27 inch Partial Route, Representative adjacent 4+26+4 aggressors Rogers Hybrid, Probe =34 inch Partial Route, Representative adjacent aggressors Rogers Hybrid, Rogers 2 inch Partial Route, Representative adjacent aggressors Rogers Hybrid, Rogers 4 inch 3.5+15.5 Actual application.23" Rogers +3.5 route Hybrid Probe =22.5 Inch W=8mil / S=8mil 55 pairs routed W=8mil / S=8mil, 8 signal layers, 4 pair (star) 16 pair (mesh) routed W=8mil / S=8mil, 8 signal layers, 4 pair (star) 16 pair (mesh) routed
Analysis Procedure Physical Physical Silicon Measure Through and Crosstalk S-Parameters Generate Linear Eq Parameters Generate DFE Eq Parameters Utilize Signal specifications from OIF and UXPi Drive with silicon Simulate in Time Domain Plot Statistical Eye Monitor Channel Output with Scope 1 Eye1-1 5 1 15 2 HUI=.5 VUI=.4 time, psec
EXAMPLE - Characterization Erni Rogers Through Through Equalizer Fit to Through db -1-2 -3 26-75 -4 26-25 2-75 -5 2-25 1 8 1 9 1 1 1 11 1 Chmag j H all ( Freq j, B) 1 7.5 5 2.5 1. 1 8 1. 1 9 1. 1 1 Freq j -2 Frequency (Hz) Erni Rogers Xtalk Crosstalk Pulse Response Xilinx (ERNI) BP Response to Raised Cosine Pulse -4.3 sdd21(db) -6.25.2.15-8 vert.txt horiz.txt diag.txt -1 1 8 1 9 1 1 1 11.1.5 1 2 3 4 5 6 7 8 9 1 11 12 13 14 15 16 17 18 19 2 21 22 23 24 25 26 Freq, Hz
EXAMPLE Results Simulated Signal + X-Talk 1Gbps Signal from Xilinx Virtex-II Pro-X FPGA Measured Eye @ Channel Output, No Equalization 1 Eye1-1 5 1 15 2 time, psec - after DFE Equalizer
Comparison of Statistical Eye to Time Domain Eye Eye 1-1 5 1 15 2 time, psec H-UI=.55 V-UI=.3 Compare Simulated and Stat Eyes with no Equalization, no crosstalk. 8 bits random data. Sim hor. opening =.55 UI Sim vert. opening =.3 units. Compare Simulated and Stat Eyes with no Equalization, no crosstalk. Stat hor. opening (Q=8) =.51 UI Stat vert. opening =.35 units.
BP-A (XAUI / HM-Zd) Configuration Config Connector Material Lengths Inches Traces Vias BP-A XAUI Reference Design Tyco HM-Zd Nelco 4-2 2+3+2 =34 inch Low Density, Partial Route Thru vias, Not Backdrilled Through Crosstalk XAUI-HMZd Xtalk Transfer -2-2 diagonal.txt horizontal.txt vertical.txt db(sdd21) -4 db -4-6 -6-8 -8 1E8 1E9 1E1 1 8 1 9 1 1 1 11 Frequency (Hz) fre q, Hz
BP-A (XAUI) 6Gbps Results Simulated Signal + X-Talk 6.25Gbps Signal from Xilinx Virtex-II Pro-X FPGA Measured Eye @ Channel Output Eye1 1-1 H-UI=.55 V-UI=.35 333 3 25 2 15 1 5 time, psec - after DFE Equalizer
BP-C (PICMG ATCA) Configuration Config Connector Material Lengths Inches Traces Vias BP-C Standard Tyco HM-Zd FR4 Thru vias, Not Backdrilled Through Crosstalk PICMG Forward Transfer PICMG Crosstalk Transfer Magnitude (db) -1-2 -3-4 layer34 layer3 layer17-5 1 8 1 9 1 1 1 11 db -2-4 -6-8 vert79.txt horiz79.txt diag79.txt vert3234.txt horiz3234.txt diag3234.txt vert1517.txt horiz1517.txt diag1517.txt 1 8 1 9 1 1 1 11 Frequency (Hz) Frequency (Hz)
BP-C (PICMG ATCA) Results Layer 34 Simulated Signal + X-Talk 1 Signal from Xilinx Virtex-II Pro-X FPGA Measured Eye @ Channel Output Eye1-1 333 3 25 2 15 1 5 time, psec - after DFE Equalizer
BP-D (Xilinx/GbX) Configuration Config Connector Material Lengths Inches Traces Vias BP-D Xilinx Concept Full Mesh and Star Teradyne GBX Rogers Hybrid (Daughters are FR4) 3+2+3 =26 inch W=8mil / S=8mil, 8 signal layers, High Density, Full Route Thru vias, Backdrilled Through Crosstalk -2-2 db(sdd21) -4 db(sdd21) -4-6 -6-8 1E8 1E9 freq, Hz 1E1-8 1E8 1E9 fre q, Hz 1E1
BP-D (Xilinx/GBX) Results Eye1 1-1 Simulated Signal + X-Talk 5 1 15 2 time, psec H-UI=.45 V-UI=.35 1Gbps Signal from Xilinx Virtex-II Pro-X FPGA Measured Eye @ Channel Output, No Equalization (this is actually from FR4 version of board) Stat eye unavailable Stat eye unavailable - after DFE Equalizer
BP-ER (Xilinx/XT) Configuration Config Connector Material Lengths Inches Traces Vias BP-ER Xilinx Concept Full Mesh and Star ERNI XT Rogers BP FR4 Line 3+21+3 =27 inch W=8mil / S=8mil, 8 signal layers, High Density, Full Route Thru vias, Backdrilled Through Crosstalk Erni Rogers Through Erni Rogers Xtalk -2-1 -4 db -2-3 26-75 -4 26-25 2-75 -5 2-25 1 8 1 9 1 1 1 11 Frequency (Hz) sdd21(db) -6-8 vert.txt horiz.txt diag.txt -1 1 8 1 9 1 1 1 11 Freq, Hz
BP-ER (Xilinx/XT) Results Simulated Signal + X-Talk 1Gbps Signal from Xilinx Virtex-II Pro-X FPGA Measured Eye @ Channel Output, No Equalization Eye1 1-1 5 1 15 2 time, psec H-UI=.55 V-UI=.55 - after DFE Equalizer
BP-E (Xilinx/XT) Configuration Config Connector Material Lengths Inches Traces Vias BP-E Xilinx Concept Full Mesh and Star ERNI XT FR4 (Daughters are FR4) 3+21+3 =27 inch W=8mil / S=8mil, 8 signal layers, High Density, Full Route Thru vias, Backdrilled Through Crosstalk ERNI Xtalk -1 Erni Through -2 vert.txt horiz.txt diag.txt db -2-3 -4 e26-75 e26-25 e2-5 e2-25 db -4-6 -5 1 8 1 9 1 1 1 11 Frequency (Hz) -8 1 8 1 9 1 1 1 11 Frequency (Hz)
BP-E (Xilinx/XT) Results Eye1 Simulated Signal + X-Talk 1 HUI=.5 VUI=.4 1Gbps Signal from Xilinx Virtex-II Pro-X FPGA Measured Eye @ Channel Output, No Equalization -1 5 1 15 2 time, psec - after DFE Equalizer
BP-F (Winchester/SIP) Configuration Config Connector Material Lengths Inches Traces Vias BP-F Winchester Concept Selective Route Winchester SIP Rogers Hybrid (Daughters are FR4) 4+26+4 =34 inch Low Density, Partial Route Thru Vias, Backdrilled Through Winchester Forward Transfer Crosstalk Gated Crosstalk Magnitude (db) -1-2 -3-4 length 34 length 3 length 26 db -2-4 -6-5 1 8 1 9 1 1 1 11 Frequency (Hz) -8 1 8 1 9 1 1 1 11 Freq
BP-F (Winchester /SIP) Results Simulated Signal + X-Talk 1Gbps Signal from Xilinx Virtex-II Pro-X FPGA Measured Eye @ Channel Output Eye1 1-1 5 1 15 2 time, psec HUI=.55 VUI=.45 - after DFE Equalizer
BP-F2 & F4 (Winchester/SIP) Configuration Config Connector Material Lengths Inches Traces Vias BP-F2 & F4 Winchester Winchester SIP1-I Rogers Hybrid 2 inches And 4 inches Thru Vias, Backdrilled
BP-F2 (Winchester /SIP) Results Simulated Signal + X-Talk 1Gbps Signal from Xilinx Virtex-II Pro-X FPGA Measured Eye @ Channel Output, No Equalization 8 Crosstalk Aggressors - after DFE Equalizer
BP-F4 (Winchester /SIP) Results Simulated Signal + X-Talk 1Gbps Signal from Xilinx Virtex-II Pro-X FPGA Measured Eye @ Channel Output, No Equalization - after DFE Equalizer
BP-G (Tier 1 Syst/ERmetZd) Configuration Config Connector Material Lengths Inches Traces Vias BP-G A Tier 1 Syst Mfg Dual Star ERNI ERmet-Zd Rogers Hybrid (Daughters are cable) 3.5+15.5+3.5 =22.5" Thru Vias, Backdrilled Through Crosstalk db(sdd21) -2-4 Crosstalk (db) -2-4 vertical horizontal diagonal -6-8 1E8 1E9 fre q, H z 1E1-6 1 8 1 9 1 1 1 11 Frequency (Hz)
BP-G (Tier 1/ERmetZd) Results Simulated Signal + X-Talk 1Gbps Signal from Xilinx Virtex-II Pro-X FPGA Measured Eye @ Channel Output Eye1 1-1 5 1 15 2 time, psec HUI=.55 VUI=.45 - after DFE Equalizer
Conclusions The backplanes shown have been, and can be built using presently available technology 1Gbps serial communication is demonstrated over multiple connectors Channels are driven with actual production 1Gbps silicon Basic 1Gbps NRZ signaling works over the backplanes studied Both Linear and DFE equalization work over the backplanes studied