In-chip and Inter-chip Interconnections and data transportations for Future MPAR Digital Receiving System

Transcription

1 In-chip and Inter-chip Interconnections and data transportations for Future MPAR Digital Receiving System A presentation for LMCO-MPAR project 2007 briefing Dr. Yan Zhang School of Electrical and Computer Engineering University of Oklahoma 1

2 2007 Milestones Review and comparison of state-of-art interconnection scheme Proposed the Digital Radar End Node (DREN) concept Study the RapidIO standard Case study with Mercury Computer Systems Demonstrate and test P-P serial links on a single FPGA device Started the custom-protocol-design 2

3 The function and inter-connection of MPAR elements From antennas Analog beamformers Digital Transceiver Digital Transceiver Digital Transceiver Digital beamformer (function/frequency 1) Digital beamformer (function/frequency N) Backplane processors Level of complexity: 400 sub-arrays, 220 beams, tera-operations/sec, 1GB/s data bandwidth 3

4 MPAR data transaction types Source / end Potential requirements ADC to Digital Pre-filter high speed, low-latency, general point-to-point allow small # of packet dropping Digital pre-filter to digital beamformers high speed, low latency, multicast, and more strict (DBF) requirement on packet dropping DBF processing module median speed, low-median latency, point-to-point To DBF processing module median-high transportation reliability, possible on-chip DBF to backplane processors lower speed, higher latency, point to multi-point, highest transportation reliability Control and synchronization signals low speed, low latency messaging, strict timing requirement, high transportation reliability Overall system-level requirement Open architecture (scalability and survivability) Low-latency (e.g., P-to-P < 100 ns) High efficiency Signal integrity Immunity to noise and interference Lowest pin-count and cost 4

5 Serial interconnection and data transportation technology Point-to-Point Switching Fabric straightforward routing Packetized divide data stream into small packets Serial differential pairs on PCB low-power, reliable and low-cost Simple protocol no OS requirement different from Ethernet Protocol FSM SERDES Diff pairs Switch fabric Diff pairs Embedded transceiver FIFO management Clock correction Channel bonding 8B/10B codec Clock management Other switches/ endpoints SERDES Protocol FSM 5

6 Existing High-speed serial IO Standards Speed #of Diff Pairs application area cost and complexity RapidIO 1.25/2/5/3.125 Gbps 1, 4 or 16 lanes DSP farms, processor low and low power (per lane) ASIC and FPGA LVDS 500M-1.5 Gbps 1 telecommunications low and low power computer and high-speed point-to-point link RocketIO 622M-6.25 Gbps up to 24 transceiver Xilinx FPGA, chip and low (per lane) lanes backplane (Physical layer compatible) XAUI 3.125/3/75 Gbps 4 backplane, computer high and high power (10 networks consumption Gigabit Ethernet) RapidIO fits our needs better because it s scalable-modular, high-speed, robust, simple and lower cost Highest effective speed over minimum physical resource 6

7 Comparison to other high-speed standards Protocol Efficiency comparison (RapidIO, Gigabit-Ethernet and PCI Express) Effective Bandwidth comparison 7

8 Current Industrial Applications (Mercury Computers) Multi-channel digital receivers (e.g., Echotek ECV4-4) System-platforms (e.g., Ensemble) RapidIO is becoming one of the most important interconnection schemes for Mercury's future products 8

9 Data acquisition Digital filtering DBF DREN can be reconfigured or do self-reconfigure during operation On-chip controller Serial transceiver Data acquisition Digital filtering DBF On-chip parallel bus On-chip controller Serial transceiver Smaller, cheaper and faster because Operations are within chip-boundary chip boundary Serial IO Switch Serial IO Switch Local memory banks On-chip controller Serial transceiver DREN concept 9

10 Phased Array Radar as a DREN network DREN DREN DREN DREN Switch network Level I DREN DREN Switch network Level II DREN DREN Analog I/Q time-series Beam-data Performance issues: (1) Latency and variation (from analog to beamforming results) (2) Processing load deviation over time (3) Local memory requirement (4) Scheduling for radar functionalities (5) Fault detection and link self-reorganization Modeling/simulation work is needed for an in-depth study (FY 08 goals) 10

11 Technical Problem Formulation In-chip interconnection: The role of embedded micro-controller How to design the interface between on-chip bus and serial transceivers Memory requirements Control procedures Inter-chip interconnection: Channel optimization The signal integrity issues Serial-switch design and selections 11

12 Xilinx embodiment of DREN On-chip CPU PowerPC 405 (programmable) IPIF Xilinx on-chip PLB bus (32-bit or 64-bit) ADC-Data Data Interface (SRAM-type) UART (serial communication With PC) IPIF IPIF Digital FIR Filtering (Xilinx IP library) Internal Configuration Access Port On-chip Block-memory (BRAM) ICAP control MEM control IPIF External Memory Access IPIF Current Xilinx RocketIO XBERT High-speed Serial Transceiver 1x/4x 12

13 Xilinx RocketIO Transceiver Block Diagram and high-speed techniques Clock correction Channel bonding 13

14 Xilinx RocketIO Transceiver Block Diagram and high-speed techniques 8B/10B encoder/decoder Digital Clock Management (DCM) 14

15 Inter-chip connectivity: Signal Integrity Issues Black box of Differential Pair Structure We established simple differential transmission line model in 3D EM solver/simulator and study the signal quality for specific trace-board design Differential output with different output terminations 15

16 Experiment Setup FPGA Development board V2P FPGA with DREN test system (loop-back Rocket IO) Planar circuit under test Infiniium DSO High-speed Differential probe One-pair of coax-cables emulating differential TRL 16

17 Pattern at Gbps Using different types of planar circuits to transmit/sample high-speed digital waveforms and measure eye-width, eye-jitters using DSO GHz 90º hybrid GHz 0º power splitter 90º hybrid has bigger eyes and less jitters 17

18 Random data sequence at Gbps BER: 90º hybrid BER: 0º power splitter 18

19 Observations Actual BER is affected by transmission line characteristics and the data pattern A better eye-diagram for one data pattern does not guarantee better BER Amplitude and phase imbalance affects the data transportation performance More experiments and tests needed to obtain quantitative comparisons 19

20 FY-08 Plan (System level) Modeling and simulation of MPAR as a DREN network (In-chip level) Enhance the existing DREN reference design RapidIO HDL behavior simulations (PHY+Tansport layer) Possible hardware evaluations Customization for radar operations (Inter-chip level) Improve signal integrity engineering model (HFSS + Ansoft Designer) Experimental PCB design Team organization Dr. Rockee Zhang MS student (Mr. Hernan): hardware and programming PhD student (Mr. Wang): system level study and performance evaluation 20

21 Experimental System Planning Adding data acquisition daughter cards Try to obtain hardware evaluation cores Tsi 578 Test on more advanced FPGAs (i.e., Virtex 5) Plan to extend to 2-node Network with FPGA DVK and serial switch Try to obtain support to manufacturers Evaluate Serial RIO switches Tsi 578 Demonstrate the data IO Speed and performance Explore various architectures Evaluate application on MPAR 21