Modeling MultiGigabit FPGA Channels with Agilent ADS 2008

Transcription

1 Modeling MultiGigabit FPGA Channels with Agilent ADS 2008 Andy Turudic Sr. Manager, High-End FPGAs Altera Amolak Badesha Field Applications Engineer - Agilent 2008 Altera Corporation Back Plane Studies S-Parameter Matrix S11 S12 S13 S14 S21 S22 S23 S24 S31 S32 S33 S34 S41 S42 S43 S44 2 Multigigabit FPGA Channels 1

2 Curve Fitting 3 - Pole Function 4 - Pole Function Minimum of 3 zeros are required to enable 6 Gbps. 4 zeros are preferred to improve flexibility 1 st Pole = 628MHz 2 nd Pole = 3.8GHz 3 rd Pole = 6.5GHz 4 th Pole = 7GHz 6G 10G 3 Back Planes Attenuation Curves Pole Locations Vary With Different BP, Cannot Use the Same Pole Function - Need Greater Flexibility! 4 Multigigabit FPGA Channels 2

3 Equalizer Transfer Function 16db DC Gain Adjustment [0dB-6dB] High Frequency Gain Adjustment [0dB-16dB] 0db Slope Adjustment [20dB-80dB] 5 Receiver Equalization Cascaded structure Different backplanes have different attenuation characteristics Need to accommodate backplane slopes of up to 80db/dec 4 cascaded stages have gain divided among them Require wide control and bandwidth optimization Zero insertion Each stage can contribute a zero in the transfer function Zero insertion is programmable Total of 4 zeros is sufficient for most legacy backplanes running up to 6.5 Gbps Total of 1,200 settings Low EQ settings available to prevent over-equalization in short reach 6 Multigigabit FPGA Channels 3

4 RD2A_RES[1:0] D2AOUTA[2:0] D2AOUTB[2:0] D2AOUTC[2:0] D2AOUTD[2:0] D2AOUTV[2:0] D2AOUTRGEN[2:0] RX Equalization FFE Feed Forward Equalization Linear with adaptive engine Requires no prior data knowledge Equalizer OFF Equalizer ON TX Near-end eye Far-end eye RX RX output 7 Altera s Adaptive Equalizer RRGEN_VOD[2:0] RRGEN_BW[1:0] RF_LPF[1:0] RF_HPF[1:0] RDC_FREQ[1:0] RRECT_ADJ[1:0] RXin EQ[A:D]_CTRL, EQV_CTRL D2As D2AOUTA[7:0] D2AOUTB[7:0] D2AOUTC[7:0] D2AOUTD[7:0] D2AOUTV[7:0] D2AOUTRGEN[7:0] RADCE_ADAPT RADCE_PDB RADCE_RST 4 stage EQ RGEN_CTRL Controls Digital Filter + Controls EQ_OUT RADCE_BYPASS RSEQ_SEL[1:0] RCLKDIV[3:0] RHYST[2:0] FIXED_CLK EQA_SET[2:0] EQB_SET[2:0] EQC_SET[2:0] EQD_SET[2:0] RRGEN_SET[2:0] EQV_SET[2:0] LF_CLK HF_CLK Rect UP_DNN_LF UP_DNN_HF Rect RGEN LPF HPF LPF UPDNN_LF UPDNN_HF RGEN_OUT Rect Adaptive Dispersion Compensation Engine RLF_OS[3:0] RHF_OS[3:0] HPF Rect RGEN Reference edge generator. This block generates an ideal reference edge to compare against the output of the equalizer. The adaptation is complete once the energy of the equalizer output is equal to the output energy of the RGEN block. LPF Low pass filter used to extract low frequency component of equalizer and RGEN outputs. HPF High pass filter used to extract high-frequency component of equalizer and RGEN outputs. RECT Rectifiers and integrators used to extract the envelope of the signal. Comparators Used to compare energy level of the two signals presented to it. Digital controls and filter Used to control rate of adaptation, sequence of adaptation and location of zeros for the equalizer. D2A Digital to analog converter used to generate the control voltage to the equalizer and RGEN blocks. 8 Multigigabit FPGA Channels 4

5 UP_DNN_LF UP_DNN_HF Adaptive Movie - XAUI Backplane Another example: Completely closed eye at RX running 6.5 G through XAUI 3G legacy backplane Go to and search for ADCE to see movie After Equalizer RRGEN_BW[1:0] VEQ1 VEQ2 VEQ3 VEQ4 VRGEN RXin EQ stage 1 VVAR EQ stage 2 EQ stage 3 EQ EQ_OUT stage 4 RGEN RGEN_OUT F[1:0] F[1:0] RGEN_CTRL LPF HPF LPF HPF Controls Rect Rect Rect Rect D2As D2As State Machine TX Adaptive Engine D2A controls CLK State Machine controls LF_OFFSET[2:0] HF_OFFSET[2:0] 9 TX Driver Considerations Low power: We use AB class design a.k.a charge conservation driver Half of quiescent current vs. A-class Inherent output symmetry (including single ended eye) Reduced EMI Improved link performance PCIe specification limits common mode driver fluctuation Superior ESD (2kV HBM) w/o dedicated structure - reduced capacitive pin load, better performance Variable VCCHTX power: 1.2V or 1.5V: Provides system flexibility and additional power reduction Output drive ranging from 200mVpp to 1.5V supply Programmable accurately calibrated termination Programmable common-mode: 0.7 and 0.6V 10 Multigigabit FPGA Channels 5

6 + - Altera s Stratix FPGA TX Driver Features Programmable common-mode output voltage. Ip_pre Ip_m ain Ip_post1 Ip_post2 Programmable On-chip Termination: 100, 120, 150 ohm, and off-state. outb 50/60/75 50/60/75 out In_pre In_post1 In_m ain In_post2 Programmable emphasis 1 Pre-tap 1 Main tap 2 Post taps Z Programmable tap polarity -1 Pre-em phasis D ig ita l F ilte r 11 Z +1 Z -2 +/- +/- 1 st pre-tap 2 nd post tap TX Equalization Transmit pre-emphasis (FIR): Pre-tap - compensates pre-cursor ISI Post-taps - compensates post-cursor ISI TX Near-end eye Far-end eye RX RX output 12 Multigigabit FPGA Channels 6

7 Molex 1m I-Trac Backplane Insertion Loss 13 Molex 1m I-Trac Gbps* Measured Pulse Responses of 1m Far End Sweep of Pre-Emphasis for 1m Far End Near End Pulse Response with Pre-emphasis Eye with Pre-Emphasis for 1m at Far End *From DesignCon 2007 paper 14 Multigigabit FPGA Channels 7

8 Stratix-II GX FPGA TxRx Design Kit for ADS Download Altera s Transceiver design kit for ADS for free Available now from 15 Stratix-II GX Design Kit in ADS Easy setup for corner case simulation Easy output voltage/current controls, taps & seeds 16 Multigigabit FPGA Channels 8

9 Stratix-II GX Design Kit in ADS Easy multi-tap pre-emphasis settings Easy settings for receiver equalization 17 Using Stratix-II GX Design Kit Remember to check Node Voltage on if you define your own node names. Insert Channel 18 Multigigabit FPGA Channels 9

10 1m Molex i-trac Backplane 19 Real-Time Simulation on ADS 2008 of Stratix II GX FPGA on a 1m Molex i-trac Channel For 6.25Gb/s case study, -20dB at F nyquist 20 Multigigabit FPGA Channels 10

11 FPGA Tx - No Pre-emphasis ADS Simulation with:tx_pre_em_1t = tx_1tap0 and no Cable 21 FPGA Tx Signal with Pre-emphasis ADS Simulation with:- eye_density(frontpanel_eye(out_p[0::sweep_size(out_p)-90],6.25e9,,80.90psec),451,321) TX_PRE_EM_1T = tx_1tap tim e, ps ec 22 Multigigabit FPGA Channels 11

12 Cable Empirical Model How to approximate scope cable? 23 Impact of Measurement Cables on Tx Out Measurement cable has significant impact on the response 24 Multigigabit FPGA Channels 12

13 Stratix-II GX Evaluation Kit 30,000~130,000 Logic Element FPGA 600 Mbps ~ Gbps operation Pre-emphasis and equalization Demonstrated on 1.25m FR-4 BP Direct-to-optics OC-48 jitter compliance Production qualified 25 Signal Integrity Kit board includes device, power, 6 channels -> one with a 40 inch serpentine 40 Differential Pair Layout in ADS Allegro layout files -> ADS extracted geometry and model 26 Multigigabit FPGA Channels 13

14 Insertion Loss of 40 Differential Channel 0-25 db(s(1,1)) db(s(1,2)) freq, GHz 27 Impact of Measurement Cables Measurement cable may have significant impact on the response db(channel_s_parameter_plus_cable..s(1,2)) db(channel_s_parameter..s(1,2)) freq, GHz 28 Multigigabit FPGA Channels 14

15 Transmitter Simulation- 40 Channel 29 eye_density(frontpanel_eye(out_p[0::sweep_size(out_p)-90],6.25e9,,109.90psec),451,32 Transmitter + Pre-emphasis on 40 inch Trace t im e, p s e c 30 Multigigabit FPGA Channels 15

16 Insertion Loss (s-21) of Molex i-trac Backplane For 6.25Gb/s case study, -20dB at F nyquist 31 Transmitter Simulation of 1m Molex i-trac Backplane 32 Multigigabit FPGA Channels 16

17 Stratix II GX with Molex 1m i-trac Far End 33 Simulate FPGA Channels with ADS 2008 ADS 2008 is available for download NOW From Agilent at Altera s ADS Design Kit for Stratix II GX FPGAs is available for free download NOW (40nm in April) from Altera s website: Availability of Altera s next generation FPGA s design kit: contact Andy Turudic at Altera aturudic@altera.com Use all of the features & libraries supported by ADS Imports layouts from common EDA platforms Excellent correlation between ADS and your bench 200 bit simulations in about 10~15 minutes! For more info, contact the Agilent or Altera sales teams 34 Multigigabit FPGA Channels 17